CN110890316A - Substrate structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a substrate structure and a manufacturing method thereof. And forming a first build-up circuit structure. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer covers the copper pillar. Forming a second build-up circuit structure and a capacitor element on the dielectric layer. The second build-up circuit structure and the first build-up circuit structure are respectively positioned at two opposite sides of the dielectric layer. The capacitance element is configured in the capacitance element arrangement area in the second layer-adding circuit structure. The copper column penetrates through the dielectric layer and is electrically connected with the second layer-adding circuit structure and the first layer-adding circuit structure. A substrate structure manufactured by the method for manufacturing the substrate structure is provided.

Description

Substrate structure and manufacturing method thereof

technical field

The invention relates to a substrate structure and a manufacturing method thereof, in particular to a substrate structure with copper pillars and capacitive elements and a manufacturing method thereof.

Background technique

At present, in order to pursue power integrity in circuit design, many passive components (such as resistors, capacitors, and inductors) are usually added to filter out noise. Generally, the volume of discrete capacitors is large, and they are usually directly welded on the substrate, but sometimes they are embedded in the substrate or the dielectric material layer to reduce the overall height. However, the length of the lines connecting the capacitors is related to the size of the capacitors. If the line is too long, the resistance of the line will increase, thereby increasing the power loss ratio.

Although the wafer process can be used to fabricate miniaturized capacitor elements to obtain thinner capacitors with larger capacitance values, the fabrication process of the miniaturized capacitor elements is complicated and the quality is difficult to control. In addition, due to the high cost of manufacturing the inductor formed by the through glass via (TGV) and the relatively long process time, high mass production cannot be achieved with the prior art. Therefore, how to integrate passive components in a simplified manufacturing process is an urgent problem to be solved in the art.

SUMMARY OF THE INVENTION

The invention provides a manufacturing method of a substrate structure, which has the advantages of simplifying the manufacturing process, reducing the cost and increasing the yield.

The present invention provides a substrate structure, which is prepared by using the above-mentioned manufacturing method of the substrate structure.

The manufacturing method of the substrate structure of the present invention includes the following steps. A first build-up wiring structure is formed. At least one copper column is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer covers the copper pillars. A second build-up circuit structure and capacitive elements are formed on the dielectric layer. Wherein, the second build-up circuit structure and the first build-up circuit structure are respectively located on opposite sides of the dielectric layer. The capacitance element is arranged in the capacitance element setting area in the second build-up circuit structure. The copper pillar penetrates through the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.

In an embodiment of the present invention, before forming the first build-up circuit structure, the following steps are further included. Supplied with glass substrate. A release layer is formed on the glass substrate. Wherein, the glass substrate and the dielectric layer are respectively located on opposite sides of the first build-up circuit structure. The release layer is located between the first build-up circuit structure and the glass substrate.

In an embodiment of the present invention, the above-mentioned step of forming the first build-up wiring structure includes the following steps. A first patterned circuit layer is formed on the release layer. A first dielectric layer is formed on the first patterned circuit layer. A first conductive via is formed on the first patterned circuit layer and penetrates through the first dielectric layer. A second patterned circuit layer is formed on the first dielectric layer. A second dielectric layer is formed on the second patterned circuit layer. Wherein, the first patterned circuit layer is electrically connected to the second patterned circuit layer through the first conductive through holes.

In an embodiment of the present invention, the above-mentioned copper pillars penetrate through the second dielectric layer of the first build-up circuit structure and are electrically connected to the second patterned circuit layer.

In an embodiment of the present invention, the above-mentioned step of forming the second build-up circuit structure and the capacitor element on the dielectric layer includes the following steps. A third patterned circuit layer is formed on the dielectric layer. The capacitor element is arranged in the capacitor element setting area on the dielectric layer. A third dielectric layer is formed on the third patterned circuit layer, and the third dielectric layer is made to cover the third patterned circuit layer and the capacitor element. A plurality of second conductive vias are formed on the third patterned circuit layer, and the second conductive vias penetrate through the third dielectric layer. A fourth patterned circuit layer is formed on the third dielectric layer, wherein the fourth patterned circuit layer and the third patterned circuit layer are respectively located on opposite sides of the third dielectric layer. The fourth patterned circuit layer is electrically connected to the third patterned circuit layer through the second conductive via. The fourth patterned circuit layer is electrically connected to the capacitive element through the second conductive via.

In an embodiment of the present invention, the above-mentioned capacitive element is disposed between the fourth patterned circuit layer and the dielectric layer.

In an embodiment of the present invention, the above-mentioned step of forming a capacitive element includes the following steps. When the third patterned circuit layer is formed, the first electrode is formed on the dielectric layer at the same time, and the first electrode is arranged in the capacitor element setting area. A fourth dielectric layer is formed on the first electrode. A second electrode is formed on the fourth dielectric layer in the capacitor element setting area. Parts of the second electrode and the fourth dielectric layer are removed.

In an embodiment of the present invention, the above-mentioned second electrode includes a titanium layer and a copper layer. The copper layer and the fourth dielectric layer are respectively located on opposite sides of the titanium layer.

In an embodiment of the present invention, the above-mentioned capacitive element includes a first electrode, a fourth dielectric layer and a second electrode. The first electrode is disposed on the dielectric layer. The fourth dielectric layer is disposed on the first electrode. The second electrode is disposed on the fourth dielectric layer. The second electrode and the first electrode are respectively located on opposite sides of the fourth dielectric layer.

In an embodiment of the present invention, after forming the second build-up circuit structure and the capacitor element on the dielectric layer, the following steps are further included. A patterned solder resist layer is formed on the second build-up circuit structure. Wherein, the patterned solder resist layer and the dielectric layer are respectively located on opposite sides of the second build-up circuit structure. Next, the release layer and the glass substrate are separated to form a substrate structure.

In an embodiment of the present invention, the above-mentioned manufacturing method of the substrate structure further includes: forming an adhesive layer. The capacitance element is disposed in the capacitance element setting area on the dielectric layer through the adhesive layer.

The substrate structure of the present invention includes a first build-up circuit structure, a dielectric layer, a second build-up circuit structure, at least one copper pillar and a capacitor element. The dielectric layer is disposed on the first build-up circuit structure. The second build-up circuit structure is disposed on the dielectric layer. The second build-up circuit structure and the first build-up circuit structure are respectively located on opposite sides of the dielectric layer. The copper pillar penetrates through the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. The capacitance element is arranged in the capacitance element setting area in the second build-up circuit structure.

In an embodiment of the present invention, the above-mentioned substrate structure further includes a glass substrate and a release layer. The glass substrate is disposed on the first build-up circuit structure, and the dielectric layer and the glass substrate are respectively located on opposite sides of the first build-up circuit structure. The release layer is disposed on the glass substrate, and the release layer is located between the first build-up circuit structure and the glass substrate.

In an embodiment of the present invention, the above-mentioned first build-up circuit structure includes a first patterned circuit layer, a first dielectric layer, a second patterned circuit layer, a second dielectric layer, and at least one first conductive via hole. Wherein, the first patterned circuit layer, the first dielectric layer, the second patterned circuit layer, and the second dielectric layer are sequentially stacked on the release layer. The first conductive via penetrates the first dielectric layer. The first patterned circuit layer is electrically connected to the second patterned circuit layer through the first conductive through holes.

In an embodiment of the present invention, the above-mentioned second build-up circuit structure includes a third patterned circuit layer, a third dielectric layer, a fourth patterned circuit layer, and a plurality of second conductive vias. The third patterned circuit layer is disposed on the dielectric layer. The third dielectric layer is disposed on the third patterned circuit layer. The fourth patterned circuit layer is disposed on the third dielectric layer. The fourth patterned circuit layer and the third patterned circuit layer are respectively located on opposite sides of the third dielectric layer. The second conductive via penetrates the third dielectric layer. The fourth patterned circuit layer is electrically connected to the third patterned circuit layer through the second conductive via. The fourth patterned circuit layer is electrically connected to the capacitive element through the second conductive through hole.

In an embodiment of the present invention, the above-mentioned capacitive element is disposed between the fourth patterned circuit layer and the dielectric layer.

In an embodiment of the present invention, the above-mentioned substrate structure further includes a patterned solder resist layer. The patterned solder resist layer is disposed on the second build-up circuit structure. The patterned solder resist layer and the dielectric layer are respectively located on opposite sides of the second build-up circuit structure.

Based on the above, in the substrate structure and the manufacturing method thereof of the present invention, a first build-up circuit structure, a copper pillar, a dielectric layer, a second build-up circuit structure and a capacitor element are sequentially formed. Wherein, the second build-up circuit structure and the first build-up circuit structure are respectively located on opposite sides of the dielectric layer. The capacitance element is arranged in the capacitance element setting area in the second build-up circuit structure. The copper pillar penetrates through the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. With this design, the substrate structure and the manufacturing method thereof of the present invention have the advantages of simplifying the manufacturing process, reducing the cost and increasing the yield.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

1A to 1H are schematic cross-sectional views illustrating a method for fabricating a substrate structure according to an embodiment of the present invention;

FIG. 1I is a schematic perspective view of the area A2 in FIG. 1H;

2A to 2F are schematic cross-sectional views illustrating a method for fabricating a substrate structure according to another embodiment of the present invention.

Description of reference numerals

100, 100a: Substrate structure

110: Glass substrate

120: release layer

130: First build-up circuit structure

131: The first patterned circuit layer

132: first dielectric layer

133: first conductive via

134: Second patterned circuit layer

135: Second Dielectric Layer

140, 141: Copper pillars

140a, 141a: upper surface

150: Dielectric layer

160: Second build-up circuit structure

161: The third patterned circuit layer

162: Third Dielectric Layer

163: Second conductive via

164: Fourth patterned circuit layer

170, 170a: Capacitive element

171: First Electrode

172: Fourth Dielectric Layer

173, 173a: second electrode

173a1: Titanium Layer

173a2: Copper Layer

180: Adhesive Layer

190: Patterned Solder Mask

A1, A2, A3: Area

C: Capacitive element setting area

Detailed ways

1A to 1I are schematic cross-sectional views illustrating a method for fabricating a substrate structure according to an embodiment of the present invention. FIG. 1I is a schematic perspective view of the area A2 in FIG. 1H .

Please refer to FIG. 1A and FIG. 1B simultaneously to form a first build-up circuit structure 130 . Specifically, in this embodiment, a glass substrate 110 is provided first, and a release layer 120 is formed on the glass substrate 110 . Next, the first build-up wiring structure 130 is formed according to the following steps: forming a first patterned wiring layer 131 (eg, by lithography etching) on the release layer 120 , forming a first dielectric layer 132 on the first pattern On the patterned circuit layer 131, the first dielectric layer 132 is drilled (for example, by means of a laser) to expose part of the first patterned circuit layer 131 to form at least one first conductive via 133 (shown in FIG. 1B ). (shown as 2) on the exposed portion of the first patterned wiring layer 131, forming a second patterned wiring layer 134 (eg, by lithography etching) on the first dielectric layer 132, and A second dielectric layer 135 is formed on the second patterned wiring layer 134 . The first conductive via 133 penetrates through the first dielectric layer 132 so that the first patterned wiring layer 131 can be electrically connected to the second patterned wiring layer 134 through the first conductive via 133 . At this point, the first build-up circuit structure 130 has been fabricated. In this embodiment, the release layer 120 is located between the first build-up circuit structure 130 and the glass substrate 110 . Here, the materials of the first dielectric layer 132 and the second dielectric layer 135 are, for example, polymer materials or resin materials.

Next, referring to FIG. 1C , at least one copper pillar 140 , 141 (two are schematically shown in FIG. 1C ) is formed on the first build-up circuit structure 130 . In detail, in this embodiment, the second dielectric layer 135 is first drilled by, for example, a laser, so as to expose part of the second patterned circuit layer 134 . In another example, at least one copper pillar 140 is formed on the second patterned circuit layer 134 of the exposed portion of the first build-up circuit structure 130 by means of photolithography. At this time, the heights of the formed copper pillars 140 and 141 may be the same or different.

Next, referring to FIG. 1D , a dielectric layer 150 is formed on the first build-up circuit structure 130 , and the dielectric layer 150 is coated on the copper pillars 140 and 141 . In detail, in this embodiment, the dielectric layer 150 is formed on the first build-up circuit structure 130 , the dielectric layer 150 covers the second dielectric layer 135 , and the dielectric layer 150 covers the copper pillars 140 , The sides of 141 or fully encapsulate the copper pillars 140 and 141 . Then, polishing is performed by chemical mechanical polishing, for example, to expose the upper surfaces 140a and 141a of the copper pillars 140 and 141 and to make the upper surfaces 140a and 141a of the copper pillars 140 and 141 flush with the dielectric layer 150 . At this time, the dielectric layer 150 and the glass substrate 110 are respectively located on opposite sides of the first build-up circuit structure 130 . Here, the material of the dielectric layer 150 is, for example, a silicone material or a resin mixed material.

Then, referring to FIG. 1E to FIG. 1G at the same time, a second build-up circuit structure 160 and a capacitor element 170 are formed on the dielectric layer 150 . Specifically, in this embodiment, the third patterned circuit layer 161 is first formed on the dielectric layer 150 , so that the third patterned circuit layer 161 covers the upper surfaces 140 a and 141 a of the copper pillars 140 and 141 , and then the capacitors The element 170 is disposed in the capacitance element setting region C on the dielectric layer 150 through the adhesive layer 180 . The capacitive element 170 is disposed between the fourth patterned circuit layer 164 and the dielectric layer 150 , and the capacitive element 170 is flush with the third patterned circuit layer 161 . Next, please refer to FIG. 1F , which is an enlarged view of the area A1 in FIG. 1E , wherein the capacitive element 170 includes a first electrode 171 , a fourth dielectric layer 172 and a second electrode 173 . The first electrode 171 is disposed on the dielectric layer 150 . The fourth dielectric layer 172 is disposed on the first electrode 171 . The second electrode 173 is disposed on the fourth dielectric layer 172 . The second electrode 173 and the first electrode 171 are respectively located on opposite sides of the fourth dielectric layer 172 . Here, the material of the fourth dielectric layer 172 is, for example, silicon oxide or other insulating resin or metal oxide material, preferably, aluminum oxide. Here, the material of the adhesive layer 180 is, for example, an adhesive polymer material or a resin material.

Next, referring to FIG. 1G again, a third dielectric layer 162 is formed on the third patterned circuit layer 161 , and the third dielectric layer 162 covers the third patterned circuit layer 161 and the capacitor element 170 . Then, the third dielectric layer 162 is drilled, for example, by means of a laser, so as to expose part of the third patterned circuit layer 161 , the second electrode 173 and the first electrode 171 . A plurality of second conductive vias 163 (three are schematically shown in FIG. 1G ) are formed on the exposed portions of the third patterned circuit layer 161 , the second electrodes 173 and the first electrodes 171 , and the second conductive vias 163 are formed. The through holes 163 penetrate through the third dielectric layer 162 . A fourth patterned wiring layer 164 is formed on the third dielectric layer 162 . The fourth patterned circuit layer 164 and the third patterned circuit layer 161 are located on opposite sides of the third dielectric layer 162 respectively. The fourth patterned wiring layer 164 is electrically connected to the third patterned wiring layer 161 through the second conductive via 163 . The fourth patterned circuit layer 164 is electrically connected to the capacitive element 170 through the second conductive via 163 . Here, the material of the third dielectric layer 162 is, for example, a polymer material or a resin material. At this point, the second build-up circuit structure 160 and the capacitive element 170 have been fabricated.

It should be noted that, although the adhesive layer 180 is used to dispose the formed capacitive element 170 on the dielectric layer 150 in this embodiment, it is not limited thereto. That is, in other embodiments, a capacitor element can also be fabricated on the dielectric layer 150 by means of a semiconductor process.

1H and FIG. 1I , a patterned solder resist layer 190 is formed on the second build-up circuit structure 160 , and the release layer 120 and the glass substrate 110 are separated to form the substrate structure 100 . In detail, in this embodiment, a patterned solder resist layer 190 is formed on the second build-up wiring structure 160 , so that the patterned solder resist 190 and the dielectric layer 150 are respectively located opposite to the second build-up wiring structure 160 . sides. The patterned solder resist layer 190 covers the third dielectric layer 162 and exposes part of the fourth patterned circuit layer 164 . Next, the release layer 120 and the glass substrate 110 are separated to complete the substrate structure 100 .

It should be noted that, in the substrate structure 100 of the present embodiment, the second build-up circuit structure 160 and the first build-up circuit structure 130 are respectively located on opposite sides of the dielectric layer 150 . The capacitive element 170 is disposed in the capacitive element arrangement region C in the second build-up circuit structure 160 . The copper pillars 140 and 141 penetrate through the dielectric layer 150 . The copper pillars 140 and 141 are electrically connected to the second build-up circuit structure 160 and the first build-up circuit structure 130 .

FIG. 1I is a schematic perspective view of the area A2 in FIG. 1H , and the second dielectric layer 135 is omitted. 1H and FIG. 1I at the same time, in this embodiment, since the third patterned circuit layer 161 , the copper pillars 140 , 141 and the second patterned circuit layer 134 can form an inductance element 200 , the The substrate structure 100 may include the inductive element 200 and the capacitive element 170 at the same time, wherein the inductive element 200 is disposed in the dielectric layer 150 and the capacitive element 170 is disposed on the dielectric layer 150 .

Based on the above, the substrate structure 100 of this embodiment includes a first build-up circuit structure 130 , a dielectric layer 150 , a second build-up circuit structure 160 , at least one copper pillar 140 , 141 and a capacitive element 170 . The dielectric layer 150 is disposed on the first build-up circuit structure 130 . The second build-up wiring structure 160 is placed on the dielectric layer 150 . The second build-up circuit structure 160 and the first build-up circuit structure 130 are respectively located on opposite sides of the dielectric layer 150 . The copper pillars 140 and 141 penetrate through the dielectric layer 150 and electrically connect the second build-up circuit structure 160 and the first build-up circuit structure 130 . The capacitive element 170 is disposed in the capacitive element arrangement region C in the second build-up circuit structure 160 .

It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and repeated descriptions in the following embodiments will not be repeated.

2A to 2F are schematic cross-sectional views illustrating a method for fabricating a substrate structure according to another embodiment of the present invention. 1A to FIG. 1I and FIGS. 2A to 2F at the same time, the manufacturing method of the substrate structure in this embodiment is similar to the manufacturing method of the substrate structure in FIG. 1A to FIG. 1I , but the main difference between the two is: For example, a capacitor element 170a is fabricated on the dielectric layer 150 by means of a semiconductor process.

In detail, in the method for fabricating the substrate structure of the present embodiment, the first build-up circuit structure 130 , the copper pillars 140 and 141 and the dielectric layer 150 are fabricated according to the steps of FIGS. 1A to 1D .

Next, please refer to FIG. 2A to FIG. 2E to fabricate the capacitive element 170a. FIG. 2E is an enlarged view of area A3 in FIG. 2D. In this embodiment, when the third patterned circuit layer 161 is formed, the first electrode 171 is formed on the dielectric layer 150 at the same time, and the first electrode 171 is disposed in the capacitance element setting region C. Next, by chemical vapor deposition, for example, a fourth dielectric layer 172 is formed on the first electrode 171 , and the fourth dielectric layer 172 covers the third patterned circuit layer 161 , the dielectric layer 150 and the first electrode 171. Then, for example, by sputtering, a titanium layer 173a1 and a copper layer 173a2 are sequentially formed on the fourth dielectric layer 172 . Then, parts of the titanium layer 173a1, the copper layer 173a2 and the fourth dielectric layer 172 are removed to form the capacitive element 170a. The titanium layer 173a1 and the copper layer 173a2 can be used as the second electrode 173a of the capacitor element 170a. The copper layer 173a2 and the fourth dielectric layer 172 are located on opposite sides of the titanium layer 173a1, respectively.

Finally, according to the steps of FIG. 1G to FIG. 1I, a second build-up circuit structure 160, a patterned solder mask layer 190 are fabricated, and the release layer 120 and the glass substrate 110 are separated to complete the substrate structure 100a of the present embodiment. As shown in Figure 2F.

To sum up, in the substrate structure and the manufacturing method thereof of the present invention, the first build-up circuit structure, the copper pillar, the dielectric layer, the second build-up circuit structure and the capacitor element are sequentially formed. Wherein, the second build-up circuit structure and the first build-up circuit structure are respectively located on opposite sides of the dielectric layer. The capacitance element is arranged in the capacitance element setting area in the second build-up circuit structure. The copper pillar penetrates through the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. With this design, the substrate structure of this embodiment can include both the inductance element and the capacitance element, wherein the inductance element is arranged in the dielectric layer, and the capacitance element is arranged on the dielectric layer. Therefore, the substrate structure and the manufacturing method thereof of the present invention have the advantages of simplifying the manufacturing process, reducing the cost and increasing the yield, compared to the conventional glass substrate where the conductive through holes of the inductor element are formed.

Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined in the claims.

Claims (20)

1. A method for fabricating a substrate structure includes:

forming a first build-up circuit structure;

forming at least one copper pillar on the first build-up circuit structure;

forming a dielectric layer on the first build-up circuit structure, wherein the dielectric layer covers the at least one copper column; and

forming a second build-up circuit structure and a capacitor element on the dielectric layer, wherein the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer, the capacitor element is configured in a capacitor element arrangement area in the second build-up circuit structure, and the at least one copper column penetrates through the dielectric layer and is electrically connected with the second build-up circuit structure and the first build-up circuit structure.

2. The method of claim 1, further comprising, before forming the first build-up circuitry structure:

providing a glass substrate; and

and forming a release layer on the glass substrate, wherein the glass substrate and the dielectric layer are respectively positioned at two opposite sides of the first build-up circuit structure, and the release layer is positioned between the first build-up circuit structure and the glass substrate.

3. The method of claim 2, wherein the step of forming the first build-up circuitry structure comprises:

forming a first patterned circuit layer on the release layer;

forming a first dielectric layer on the first patterned circuit layer;

forming at least one first conductive via on the first patterned circuit layer and penetrating through the first dielectric layer;

forming a second patterned circuit layer on the first dielectric layer; and

and forming a second dielectric layer on the second patterned circuit layer, wherein the first patterned circuit layer is electrically connected with the second patterned circuit layer through the at least one first conductive through hole.

4. The method of claim 3, wherein the at least one copper pillar penetrates the second dielectric layer of the first build-up circuitry structure and is electrically connected to the second patterned circuitry layer.

5. The method of claim 2, further comprising, after forming the second build-up circuitry structure and the capacitive element on the dielectric layer:

forming a patterned solder mask layer on the second build-up circuit structure, wherein the patterned solder mask layer and the dielectric layer are respectively located on two opposite sides of the second build-up circuit structure; and

and separating the release layer and the glass substrate to form the substrate structure.

6. The method of claim 1, wherein the step of forming the second build-up circuitry structure and the capacitive element on the dielectric layer comprises:

forming a third patterned circuit layer on the dielectric layer;

disposing the capacitive element on the capacitive element mounting region on the dielectric layer;

forming a third dielectric layer on the third patterned circuit layer, wherein the third dielectric layer covers the third patterned circuit layer and the capacitor element;

forming a plurality of second conductive vias on the third patterned circuit layer, wherein the plurality of second conductive vias penetrate through the third dielectric layer; and

forming a fourth patterned circuit layer on the third dielectric layer, wherein the fourth patterned circuit layer and the third patterned circuit layer are respectively located on two opposite sides of the third dielectric layer, the fourth patterned circuit layer is electrically connected to the third patterned circuit layer through the plurality of second conductive vias, and the fourth patterned circuit layer is electrically connected to the capacitor element through the plurality of second conductive vias.

7. The method of claim 6, wherein the capacitive element is disposed between the fourth patterned circuit layer and the dielectric layer.

8. The method of claim 6, wherein the step of forming the capacitive element comprises:

forming a first electrode on the dielectric layer while forming the third patterned circuit layer, the first electrode being disposed in the capacitive element disposing region,

forming a fourth dielectric layer on the first electrode;

forming a second electrode on the fourth dielectric layer in the capacitive element disposing region; and

removing portions of the second electrode and the fourth dielectric layer.

9. The method as claimed in claim 8, wherein the second electrode comprises a titanium layer and a copper layer, and the copper layer and the fourth dielectric layer are respectively disposed on opposite sides of the titanium layer.

10. The method of claim 1, wherein the capacitive element comprises:

a first electrode disposed on the dielectric layer;

a fourth dielectric layer disposed on the first electrode; and

the second electrode is configured on the fourth dielectric layer, and the second electrode and the first electrode are respectively positioned at two opposite sides of the fourth dielectric layer.

11. The method of claim 1, further comprising:

and forming an adhesion layer, and enabling the capacitor element to be arranged in the capacitor element arrangement area on the dielectric layer through the adhesion layer.

12. A substrate structure, comprising:

a first build-up line structure;

a dielectric layer configured on the first build-up circuit structure;

the second layer-adding circuit structure is configured on the dielectric layer, and the second layer-adding circuit structure and the first layer-adding circuit structure are respectively positioned at two opposite sides of the dielectric layer;

at least one copper column penetrating the dielectric layer and electrically connecting the second build-up circuit structure and the first build-up circuit structure; and

and the capacitance element is configured in the capacitance element arrangement area in the second layer-adding circuit structure.

13. The substrate structure of claim 12, further comprising:

the glass substrate is arranged on the first layer-adding circuit structure, and the dielectric layer and the glass substrate are respectively positioned at two opposite sides of the first layer-adding circuit structure; and

and the release layer is configured on the glass substrate and is positioned between the first build-up circuit structure and the glass substrate.

14. The substrate structure of claim 13, wherein the first build-up line structure comprises: the circuit board comprises a first patterning circuit layer, a first dielectric layer, a second patterning circuit layer, a second dielectric layer and at least a first conductive through hole, wherein the first patterning circuit layer, the first dielectric layer, the second patterning circuit layer and the second dielectric layer are sequentially stacked on a release layer, the at least one first conductive through hole penetrates through the first dielectric layer, and the first patterning circuit layer is electrically connected with the second patterning circuit layer through the at least one first conductive through hole.

15. The substrate structure of claim 14, wherein the at least one copper pillar extends through the second dielectric layer of the first build-up circuitry structure and is electrically connected to the second patterned circuitry layer.

16. The substrate structure of claim 12, wherein the second build-up line structure comprises:

a third patterned circuit layer disposed on the dielectric layer;

a third dielectric layer disposed on the third patterned circuit layer;

the fourth patterned circuit layer is configured on the third dielectric layer, and the fourth patterned circuit layer and the third patterned circuit layer are respectively positioned at two opposite sides of the third dielectric layer; and

a plurality of second conductive vias penetrating the third dielectric layer, wherein the fourth patterned circuit layer is electrically connected to the third patterned circuit layer through the plurality of second conductive vias, and the fourth patterned circuit layer is electrically connected to the capacitor element through the plurality of second conductive vias.

17. The substrate structure of claim 16, wherein the capacitive element is disposed between the fourth patterned line layer and the dielectric layer.

18. The substrate structure of claim 12, wherein the capacitive element comprises:

a first electrode disposed on the dielectric layer;

a fourth dielectric layer disposed on the first electrode; and

the second electrode is configured on the fourth dielectric layer, and the second electrode and the first electrode are respectively positioned at two opposite sides of the fourth dielectric layer.

19. The substrate structure of claim 12, further comprising:

and the patterned solder mask is configured on the second layer-adding circuit structure, and the patterned solder mask and the dielectric layer are respectively positioned at two opposite sides of the second layer-adding circuit structure.

20. The substrate structure of claim 12, further comprising:

and the adhesion layer enables the capacitor element to be arranged in the capacitor element arrangement area on the dielectric layer through the adhesion layer.

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