CN110867170B

CN110867170B - Display panel driving method, display driving device and electronic equipment

Info

Publication number: CN110867170B
Application number: CN201911205723.4A
Authority: CN
Inventors: 吴常志; 孙莹; 许育民
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2022-07-29
Anticipated expiration: 2039-11-29
Also published as: CN110867170A

Abstract

The embodiment of the invention discloses a display panel driving method, a display driving device and electronic equipment. The driving method includes: acquiring an image to be displayed; providing display signals to the sub-pixels by using the scanning lines and the data lines according to an image to be displayed; displaying an image to be displayed according to the display signal; the display signals comprise grid opening signals and data signals, and in one frame of scanning period, the grid opening signals are loaded to the scanning lines, and the corresponding data signals are sequentially loaded to the data lines; in a frame of picture to be displayed, the time lengths of at least two charging gaps are unequal; the charging gap is the time difference between the initial writing time of the (i + 1) th data signal and the finishing writing time of the ith data signal; i is a positive integer. According to the technical scheme, the duration of the at least two charging gaps is unequal, the inherent periodicity of the data signals can be damaged, electromagnetic interference is reduced, and the influence on other vehicle-mounted electronic products when the display panel is applied to a vehicle-mounted display screen is reduced.

Description

Display panel driving method, display driving device and electronic equipment

Technical Field

The present invention relates to the field of display technologies, and in particular, to a driving method for a display panel, a display driving apparatus, and an electronic device.

Background

With the development of Display technology, Liquid Crystal Display (LCD) panels and Organic Light Emitting Diode (OLED) Display panels gradually become two major Display panels in the Display field, and LCD panels and OLED Display panels are widely used in devices or scenes capable of integrating Display functions, known by those skilled in the art, such as computers, mobile phones, wearable devices, and vehicles.

Generally, the operation of electronic products causes Interference to other peripheral electronic products, and the Interference may be referred to as Electromagnetic Interference (EMI), and the electronic products subjected to the EMI may degrade or even fail to operate normally. Based on this, when the display panel is integrally arranged in some devices or applied to some scenes, for example, when the display panel is applied to vehicle-mounted display, the display panel can generate electromagnetic interference to other vehicle-mounted electronic products when being used as a vehicle-mounted display screen.

Disclosure of Invention

The invention provides a driving method of a display panel, a display driving device and electronic equipment, which are used for reducing electromagnetic interference radiated to the periphery by the display panel so as to reduce the electromagnetic interference to other vehicle-mounted electronic products when the display panel is used as a vehicle-mounted display screen.

In a first aspect, an embodiment of the present invention provides a driving method for a display panel, where the display panel includes scan lines and data lines, where the scan lines and the data lines intersect to define a plurality of sub-pixel regions, and the sub-pixel regions are provided with sub-pixels; the driving method includes:

acquiring an image to be displayed;

according to the image to be displayed, providing display signals to the sub-pixels by using the scanning lines and the data lines;

displaying the image to be displayed according to the display signal;

the display signals comprise grid opening signals and data signals, and in one frame of scanning period, the grid opening signals are loaded to the scanning lines, and the corresponding data signals are sequentially loaded to the data lines; in one frame of the picture to be displayed, the time lengths of at least two charging gaps are different; the charging gap is a time difference value between the initial writing time of the (i + 1) th data signal and the finishing writing time of the ith data signal; i is a positive integer.

In a second aspect, an embodiment of the present invention provides a display driving apparatus for performing any one of the driving methods provided in the first aspect, the display driving apparatus including:

The image acquisition module is used for acquiring an image to be displayed;

the signal providing module is used for providing display signals for the sub-pixels by utilizing the scanning lines and the data lines according to the image to be displayed;

and the image display module is used for displaying the image to be displayed according to the display signal.

In a third aspect, an embodiment of the present invention further provides an electronic device, which includes the display driving apparatus provided in the second aspect.

The driving method of the display panel provided by the embodiment of the invention loads the grid opening signal to the scanning lines, loads the corresponding data signals to the data lines in sequence and sets the time length of at least two charging gaps in a frame of picture to be displayed to be unequal by setting in a frame of scanning period, wherein the charging gap is the time difference between the initial writing time of the (i + 1) th data signal and the finishing writing time of the ith data signal; i is a positive integer, so that the duration of at least one charging gap in one frame of picture to be displayed is not equal to the duration of other charging gaps, the duration of the charging period of the data signal in one frame of picture to be displayed is not completely the same, namely, the natural frequency characteristic of the data signal is destroyed, the electromagnetic interference phenomenon caused by the fixed frequency of the data signal can be weakened, namely, the electromagnetic interference generated by the data signal is improved, the problem that the interference energy radiates to the periphery to cause interference on other electronic products on the vehicle is avoided, the improvement of the performance of other electronic products on the vehicle is facilitated, and the normal operation of the vehicle-mounted electronic products is facilitated.

Drawings

FIG. 1 is a timing diagram illustrating a driving method of a display panel according to the related art;

FIG. 2 is a schematic diagram illustrating an EMI effect corresponding to a driving timing of the display panel of FIG. 1;

fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 4 is a schematic flow chart of a driving method according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a driving timing sequence according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a multi-path selection circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of another driving timing sequence provided in the embodiment of the present invention;

fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 10 is a schematic flow chart of another driving method according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of another driving timing sequence provided by the embodiment of the present invention;

fig. 12 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 13 is a timing diagram illustrating a driving sequence according to another embodiment of the present invention;

fig. 14 is a schematic structural diagram of a display driving apparatus according to an embodiment of the present invention;

Fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

In the structure of the existing display panel, the display panel includes a display area and a non-display area; in the display area, scanning lines and data lines are arranged in a crossed manner to limit a sub-pixel area, and sub-pixels are arranged in the sub-pixel area; in the non-display region, a driver circuit including a scan driver circuit which is also commonly referred to as a shift register circuit and a data driver circuit which is commonly referred to as a multiplexer circuit is provided. The shift register circuit comprises cascade shift registers, the output end of each stage of shift register is electrically connected with a scanning line corresponding to a row of sub-pixels, and the scanning line provides scanning signals (also called gate opening signals) for the same row of scanning lines; the multi-path selection circuit comprises a plurality of multi-path selection units, the control ends of the multi-path selection units correspond to the output ends one by one, the output ends are correspondingly connected with the data lines, and the data lines are used for writing data signals into the sub-pixels under the action of the clock control signal lines.

The principle of the display panel generating electromagnetic interference is exemplarily described below with reference to fig. 1 and 2.

Referring to fig. 1 and 2, in the prior art, scan signals (shown as gate1, gate2, gate3, … …, gate in fig. 1) are arranged in a row-by-row (also referred to as "row-by-row")"progressive") scanning, one stage at a time; during the scan signal enable period (high period in fig. 1) of the current stage, the clock control signal (shown as MUX0 in fig. 1) controls each data line to write the data signal to the sub-pixel of the current row. Wherein, the scanning time of each line can be called as a line scanning period T _H-sync The scanning frequency corresponding to the line scanning period is f _H-sync ，f _H-sync ＝1/T _H-sync (ii) a Taking the multiplexing unit 1:3 as an example (as shown in fig. 1), the MUX0 includes three clock control sequences, and the overall frequency of the clock control signal (also referred to herein as "MUX frequency") is 3 times the scanning frequency, so that the writing frequency of the data signal is 3 times the scanning frequency for a row of sub-pixels. Because the scanning frequency, the frequency of the clock control signal and the writing frequency are all fixed, energy peaks occur at a plurality of fixed frequency positions of a low frequency band of the vehicle gauge, namely the energy peaks occur periodically, and a large energy value at the energy peaks radiates outwards, which easily causes that other electronic products on the vehicle cannot work normally due to electromagnetic interference. For example, the EMI test results may be as shown in fig. 2. Wherein, the abscissa X represents frequency in hertz (Hz), and the ordinate Y represents intensity of radiation energy, which can be understood as DB value (i.e. count value) in absolute unit (a.u.), that is, the EMI test result is obtained by pure counting method; wherein, L011 and L012 respectively represent the average value and the maximum value of the same specification requirement limit value of the vehicle, and L021 and L022 respectively represent the average value curve and the maximum value curve of the EMI radiation energy at different frequencies obtained by testing. As can be seen from fig. 2, energy peaks occur at positions which are multiples of both the scanning frequency and the writing frequency. Thus, the energy at the energy peak is radiated to the periphery of the display panel, which may affect the normal operation of other electronic products in the vehicle.

In view of the foregoing problems, embodiments of the present invention provide a driving method for a display panel, a display driving apparatus, and an electronic device, which break the inherent periodicity of a data signal to disperse energy at each frequency position, so as to weaken energy at an energy peak and further improve an electromagnetic interference phenomenon. Specifically, in the embodiment of the present invention, by setting the time lengths of at least two charging gaps in one frame of the to-be-displayed picture to be different, wherein the charging gap is a time difference between a start writing time of the (i + 1) th data signal and an end writing time of the ith data signal, the time length of at least one charging gap in a frame of picture to be displayed is not equal to the time length of other charging gaps, so that the duration of the charging period of the data signal in one frame of the picture to be displayed is not completely the same, i.e., the natural frequency characteristics of the data signal are destroyed, and thus the electromagnetic interference caused by the fixed frequency of the data signal can be weakened, the problem that electromagnetic interference generated by data signals is radiated out to cause interference to other electronic products on the vehicle is solved, and the improvement of the performance of the other electronic products on the vehicle is facilitated, namely the normal operation of the electronic products is facilitated.

A driving method of a display panel, a display driving apparatus, and an electronic device according to an embodiment of the present invention are exemplarily described below with reference to fig. 3 to fig. 15.

Illustratively, referring to fig. 3, the display panel 90 includes a display area 920 and a non-display area 910 surrounding the display area 920; the display panel 90 includes scan lines 931 and data lines 932, where the scan lines 931 and the data lines 932 are arranged to intersect to define a plurality of sub-pixel regions 934, and each sub-pixel region 934 has a sub-pixel 933 disposed therein.

The display area 920 of the display panel 90 is used for displaying an image to be displayed.

For example, the display panel 90 may be an LCD panel, an OLED display panel, or other types of display panels known to those skilled in the art, and the embodiment of the invention is not limited thereto.

The non-display area 910 of the display panel 90 is used for disposing a driving circuit, an anti-static circuit, an integrated circuit, and other circuit structures, optical structures, or supporting and fixing structures known to those skilled in the art, which is not limited in the embodiments of the present invention.

Illustratively, the non-display area 910 is shown in FIG. 3, by way of example only, as being disposed around the display area 920. In other embodiments, the non-display area 910 may be further configured to half surround the display area 920, or the non-display area 910 is further configured to be adjacent to the display area 920 in the left and right direction, or the non-display area 910 is configured to be adjacent to the display area 920 in the up and down direction, or other relative position relationships known to those skilled in the art may be provided, which is not limited in this embodiment of the present invention.

For example, the scan lines 931 and the data lines 932 in fig. 3 may intersect vertically or not, and the angle at which the scan lines 931 and the data lines intersect may be set according to the actual requirement of the display panel 90, which is not limited in this embodiment of the invention.

It should be noted that fig. 3 shows only the scan lines 931 and the data lines 932 in a straight line as an example. In the actual product structure of the display panel 90, the actual shapes of the scan lines 931 and the data lines 932 may be set according to the actual requirements of the display panel 90, which is not limited in the embodiment of the invention.

Illustratively, only the sub-pixel region 934 is exemplarily shown in fig. 3 as a rectangle. In the actual product structure of the display panel 90, the shape of the sub-pixel region 90 may be set according to the wiring manner of the display panel 90 and other requirements, which is not limited in the embodiment of the invention.

It should be noted that fig. 3 only shows the scan lines 931 and the data lines 932 extending from the display area 920 to the non-display area 910 by way of example. In other embodiments, the lengths of the scan lines 931 and the data lines 932 and the relative position relationship between the scan lines and the data lines and the boundary of the display area 920 may also be set according to actual requirements of the display panel 90, which is not limited by the embodiment of the present invention.

Based on the structure of the display panel, referring to fig. 4, the driving method of the display panel includes:

and S110, acquiring an image to be displayed.

The image to be displayed may also be referred to as a picture to be displayed, and the image to be displayed is an image that needs to be displayed by the display panel. For example, the frame of image to be displayed may be a frame of picture in a static image or a frame of picture in a dynamic scene image.

For example, if the display panel is applied to a mobile phone, the mobile phone may include a main board (including a driving system) and an Integrated Circuit (IC) connecting the main board and the display panel. Based on this, the step may include the IC receiving the to-be-displayed picture output by the main board.

For example, if the display panel is applied to a computer, the computer may include a graphics card and an IC connecting the graphics card and the display panel. Based on this, the step may include the IC receiving the picture to be displayed output by the display card.

In other embodiments, when the display panel is applied to other display devices (or called electronic apparatuses, also called electronic products), this step may include the IC obtaining the picture to be displayed by the overall control system of the display device, and the present invention does not limit the actual product structure form of the overall control system.

And S120, providing a display signal to the sub-pixel by using the scanning line and the data line according to the image to be displayed.

The display signals comprise grid opening signals and data signals; the gate-on signal determines the row of the sub-pixel where the data signal can be written, and the magnitude of the data signal determines the display gray scale (which can be understood as the display brightness) of the sub-pixel; the scanning lines are used for providing gate opening signals to the sub-pixels step by step, and the data lines are used for providing data signals to the sub-pixels which are opened in the row.

Wherein, a frame of frame to be displayed is refreshed correspondingly in a frame scanning period. In one frame scanning period, the scanning lines 931 arranged row by row can gradually load the gate-on signals to the sub-pixels 933 of the corresponding row, and at this time, the data signals are written into each sub-pixel 933 of the row by the data lines 932; and the process of completing the writing of the data signals from the first row of sub-pixels to the last row of sub-pixels correspondingly refreshes a complete picture.

With reference to fig. 3 and 5, the display signals include Gate-on signals (Gate signals, which are respectively shown as Gate1, Gate2, and Gate3 in fig. 5) and Data signals (Data signals, which are respectively shown as Data1, Data2, and Data3 in fig. 5), and in one frame of scanning period, the Gate-on signals are applied to the scanning lines 931, and the corresponding Data signals are sequentially applied to the Data lines 932; in a frame of picture to be displayed, the time lengths of at least two charging gaps delta TD are different; the charging gap delta TD is a time difference value between the initial writing time of the (i + 1) th data signal and the finishing writing time of the ith data signal; i is a positive integer. Meanwhile, in order to ensure that the display panel has a better display effect, the time lengths of all data writing periods are set to be equal; the duration of the data writing period may be understood as a time difference between the start writing timing of the ith data signal and the end writing timing of the ith data signal. For example, the data writing period of the data signal may be a period corresponding to a duration of one color writing process of the data signal in fig. 5.

Wherein the entire duration of the data write period and the immediately following adjacent charging gap may be regarded as a charging period of one data signal; that is, a "charging period" herein is understood to be a time interval between two consecutive start write timings in the data signal, that is, a time interval between start timings of two consecutive data write periods in the data signal. Exemplarily, in FIG. 5, T is respectively _D1 、T _D2 、T _D3 、T _D4 、T _D5 And T _D6 A plurality of charging periods with different moments in time as the starting writing moments are shown. It can be understood that, when a plurality of data writing periods are all covered by the same scanning time sequence section, the charging period in which the last data writing period covered by the scanning time sequence section is located is ended by the enabling level of the scanning time sequence section. For example, the charging period in which the data writing period denoted by "i + 1" in fig. 5 is present is by the end time of the enable level of the Gate1 signal; that is, when 1 scan period covers 3 data writing periods, the charging period in which the 3 rd data writing period is located is up to the end time of the enable level of the scan period. The duration of at least two charging gaps is unequal, the duration of the data writing period is equal, the duration of at least two charging periods of the data signal is unequal, so that the inherent periodic characteristic (also called inherent frequency characteristic) of the data signal is destroyed, the electromagnetic interference phenomenon caused by the fixed duration of the charging period of the data signal can be weakened, namely, the problem that the electromagnetic interference generated by the data signal is radiated to the periphery to cause the electromagnetic interference to other peripheral electronic products is solved, the improvement of the performance of other electronic products on the vehicle is facilitated, namely, the normal operation of other electronic products is facilitated And (6) rows.

Meanwhile, the time length of at least two charging gaps is set to be unequal, so that the correlation between the frequency of the data signal and the frequency of the scanning signal can be reduced, the overall energy of the display panel is dispersed, the energy value at a frequency doubling position is reduced, and the electromagnetic interference phenomenon is weakened.

Illustratively, this step may include the IC providing display signals associated with the image to be displayed to the subpixels using the scan lines and the data lines. When the image to be displayed changes, the display signal changes accordingly.

Illustratively, in fig. 5, each Data signal corresponds to a sub-pixel of one color, specifically Data1 corresponds to a red (R) sub-pixel, Data2 corresponds to a green sub-pixel (G), and Data3 corresponds to a blue (B) sub-pixel; meanwhile, fig. 5 shows only three-level Gate signals, namely, Gate1, Gate2, and Gate 3; but are not to be construed as limiting the display panel in the embodiment of the present invention. In other embodiments, the number of the Date signals and the Gate signals may be set according to actual requirements of the display panel, which is not limited in the embodiment of the present invention.

It will be appreciated that the voltage across the charging gap is shown in fig. 5, which is merely exemplary, as being maintained at 0V, and is represented by a line segment having no width. In other embodiments, in the period of the charging gap, the data signal corresponding to the sub-pixel of each color may also maintain its respective voltage signal in the data writing period, that is, the charging gap is filled in a data maintaining manner, and the data maintaining time of the data signal corresponding to the sub-pixel of different color may be different, and may be set according to the actual requirements of the display panel and the driving method thereof, which is not limited in the embodiments of the present invention.

And S130, displaying the image to be displayed according to the display signal.

In a frame scanning period, each sub-pixel in the display panel can realize the refreshing of a complete image to be displayed after receiving a display signal.

Illustratively, the step may include the display panel displaying the image to be displayed according to the display signal.

According to the driving method of the display panel provided by the embodiment of the invention, the charging time periods of the data signals are not completely the same by setting the different durations of the at least two charging gaps, so that the radiation energy can be dispersed at more frequency positions, the energy value at a frequency doubling position is reduced, the electromagnetic interference is improved, and the normal work of electronic products around the display panel is facilitated.

On the basis of the embodiment, in order to reduce the number of routing lines of the fan-out area, the narrow frame design is realized; meanwhile, in order to reduce the number of IC wiring pins and the cost of the IC and the whole display panel, a multi-path selection circuit can be arranged at the position of a lower frame of the display panel. The multiplexer circuit may also be referred to as a multiplexer, a data selector, a multiplexer switch or a data selection switch, and is configured to transmit a data signal on a data source line to at least one data line through a signal input from the control terminal during transmission of the data signal. On the basis, in order to obtain data signals of different charging periods, the signals of the control terminal of the multiplexing circuit can be adjusted, and the adjustment mode can include hardware improvement or software improvement, which is respectively described below.

Fig. 6-8 illustrate exemplary hardware improvement correlation structures and timing.

Optionally, referring to fig. 6 and 7, the display panel 90 further includes a multi-path selection circuit 940, a plurality of data source lines 942 and m clock control signal lines 943, the multi-path selection circuit 940 includes a plurality of multi-path selection units 941, an input end of one multi-path selection unit 941 is correspondingly disposed and electrically connected to one data source line 942, the multi-path selection unit 941 has m output ends and m control ends, m output ends of one multi-path selection unit 941 are correspondingly disposed and electrically connected to m data lines 932, and m clock control signal lines 943 are correspondingly disposed and electrically connected to m control ends of each multi-path selection unit 941; the display panel 90 further includes an inverter unit 950, the inverter unit 950 including at least one inverter 951; the m clock control signal lines 943 include a clock selection control signal line 9431, the clock selection control signal line 9431 includes a first sub-line segment 4311 and a second sub-line segment 4312, a first end of the first sub-line segment 4311 is electrically connected to a control end of the inverter unit 951, a first end of the second sub-line segment 4312 is electrically connected to an output end of the inverter unit 951, and a second end of the second sub-line segment 4312 is electrically connected to a control end of the corresponding multi-path selection unit 941; the first signal (shown as SW2 and SW3 in fig. 7) transmitted by the first sub-line segment 4311 passes through the inverter unit 920 to form a second signal (shown as SW2 'and SW 3' in fig. 7), and the second signal and the first signal have a time delay.

Taking an operation mode in which the multiplexing units 941 in the multiplexing circuit 940 are 1 dm, each multiplexing unit 941 is configured to transmit a data signal on one data source line 942 to m data lines 932 in a time-sharing manner; the clock control signal line 943 provides specific timing for time-sharing control.

Exemplarily, in fig. 6 and 7, m has a value of 3; the operation of the multiplexing unit 941 is described as follows.

One of the multiplexer units 941 includes 3 control switches, which are shown as N-type Thin Film Transistors (TFTs), and the input terminals of the 3 control switches are connected to the same data source line 942, 3 control terminals are connected to 3 different clock control signal lines 943, and 3 output terminals are connected to 3 different data lines 932. According to the orientation sequence from top to bottom and from left to right in fig. 7, when the first clock control signal line 943 controls the first control switch to be turned on, the data signal on the data source line 942 is transmitted to the first data line 932 through the control switch, when the second clock control signal line 943 controls the second control switch to be turned on, the data signal on the data source line 942 is transmitted to the second data line 932 through the control switch, when the third clock control signal line 943 controls the third control switch to be turned on, the data signal on the data source line 942 is transmitted to the third data line 932 through the control switch, the enable signals on the 3 clock control signal lines 943 are sequentially staggered in time sequence, and thus the effective writing periods of the data signals on the 3 data lines 932 are sequentially staggered in time sequence.

In other embodiments, the number of the data source lines 942, the clock control signal lines 943 and the data lines 932 connected to each multiplexing unit 941 may also be set according to the actual requirements of the display panel 90, which is not limited in this embodiment of the present invention.

In other embodiments, the control switches in one multiplexing unit 941 may also be all P-type thin film transistors, or a combination of P-type thin film transistors and N-type thin film transistors; or other switch control structures known to those skilled in the art, and the embodiments of the present invention are not limited thereto.

The inverters 951 of the inverter units 950 are connected in series, and one inverter 951 may invert the phase of an input signal by 180 degrees and output the inverted signal. When the number of the inverters 951 arranged in series in the inverter unit 950 is an odd number, the output signal of the inverter unit 950 is phase-inverted by 180 degrees with respect to its input signal; when the number of the inverters 951 arranged in series in the inverter unit 950 is an even number, the output signal of the inverter unit 950 is phase-inverted by 360 degrees with respect to its input signal, i.e., the output signal is the same phase as its input signal.

For example, the phase inversion is described by taking the high and low levels as an example: when the number of the inverters 951 in the inverter unit 950 is odd, the input end of the inverter unit 950 inputs a low level, and the output end thereof outputs a high level; the inverter unit 950 has an input terminal to which a high level is input and an output terminal to which a low level is output.

Meanwhile, the inverter 951 has a propagation delay effect, and the delay duration of the propagation delay depends on the load capacitance existing in the circuit trace of the inverter 951. Based on this, a time delay of the second signal relative to the first signal can be achieved. It will be appreciated that the "time delay" appears chronologically as: the timing of switching between the high-level signal and the low-level signal of the second signal is delayed with respect to the timing of switching between the corresponding high-level signal and the corresponding low-level signal of the first signal. Since the enable levels of the second signal and the first signal are the same in duration, the time delay is reflected by the difference in the gap Δ TS between the enable signals.

In this way, the inverter 951 structure is added to a different clock control signal line 943, and a time delay of the clock control signal can be realized. The time sequence of the data signal is consistent with the time sequence of the corresponding clock control signal, so that the time delay of the data signal can be realized, and when the time delay duration is different, the charging gaps of the data signal can be different, so that the charging time periods are different, the inherent periodicity of the data signal is damaged, the radiation energy is dispersed at different frequency positions, and the electromagnetic radiation is reduced.

Alternatively, referring to fig. 7 and 8, the clock selection control signal lines 9431 include a first control signal line and a second control signal line, and the m clock control signal lines 943 further include a clock reference control signal line 9432; the inverter unit 950 disposed corresponding to the first control signal line includes one inverter 951, and the inverter unit 950 disposed corresponding to the second control signal line includes two inverters 951 disposed in series; on the first control signal line, the second signal SW2 'is delayed with respect to the first signal SW2 by a first duration, and the second signal SW 2' is opposite in phase to the first signal SW 2; on the second control signal line, the second signal SW3 'is delayed with respect to the first signal SW3 by a second duration, and the second signal SW 3' is in the same phase as the first signal SW 3; the clock reference control signal line 9432 is not provided with the inverter unit 950, and the signal SW 1' at the output of the clock reference control signal line 9432 is the same as the signal SW1 at the input of the clock reference control signal line 9432; wherein the second duration is greater than the first duration.

Wherein, when the structural parameters of the inverters 951 are the same, each inverter 951 can realize the time delay with the same time length. Based on this, when the number of inverters 951 in the different inverter units 950 is set to be different, time delays of different time lengths can be realized.

Illustratively, in the clock control signal at the input terminal of the clock control signal line 943, the time interval between the start times of two consecutive adjacent enable signals is fixed, and is denoted by T in fig. 8 _S0 Shown. By providing the inverter unit 950 and providing the different inverter units 950 including 1 inverter 951 and 2 inverters 951, respectively, the first control signal line and the second control signal line can be made to be identicalThe signal at the output of the line is delayed with respect to the signal at its input by a first duration and a second duration, respectively, such that, in the signal at the output: the time length of a scanning gap delta TS1 between the start time of an enable signal on a first control signal line and the end time of the enable signal on a clock reference control signal line is less than the time length of a scanning gap delta TS2 between the start time of an enable signal on a second control signal line and the end time of the enable signal on the first control signal line; since the durations of the high level enable phases of the clock control signals are all equal, the duration T of the second control period in fig. 8 is thus _S2 A duration T greater than the first control period _S1 . Since the timing of the data signal corresponds to the timing of the clock control signal, it is possible to realize that the duration Δ TD2 of the second charging gap in fig. 8 is longer than the duration Δ TD1 of the first charging gap based on the adjustment of the clock control signal, and thus the durations of the data writing periods of the data signal are all equal, whereby the second charging period T in fig. 8 is _D2 Is longer than the duration T of the first charging period _D1 Therefore, the duration of the charging period of the data signal is not fixed, and the electromagnetic interference is reduced.

It should be noted that fig. 7 only illustrates the structure of the inverter unit 950 by the number of the inverters 951 being 1 and 2 for example, in other embodiments, the structure of the inverter unit 950 (for example, the number of the inverters 951 in the inverter unit 950) may also be set according to actual requirements of the display panel and the driving method thereof, and the embodiment of the present invention does not limit this.

Optionally, with continued reference to fig. 7, inverter 951 includes a P-type transistor 9511 and an N-type transistor 9512; a control terminal of the P-type transistor 9511 and a control terminal of the N-type transistor 9512 are electrically connected to the first sub-line segment 4311; a first terminal of the P-type transistor 9511 is electrically connected to a first potential terminal VGH, a first terminal of the N-type transistor 9512 is electrically connected to a second potential terminal VGL, and a potential of the first potential terminal VGH is higher than a potential of the second potential terminal VGL; a second terminal of the P-type transistor 9511 is electrically connected to a second terminal of the N-type transistor 9512, and is electrically connected to a control terminal of the corresponding multiplexing unit 941 through the second sub-line 4312.

The operation principle of the inverter 951 will be described with reference to fig. 8 by taking signals SW2 and SW 2' as examples. When the SW2 is a low level signal, the P-type transistor 9511 is turned on, and the voltage signal at the first voltage terminal VGH is output to the SW 2', that is, a high level signal is output; when the SW2 is a high level signal, the N-type transistor 9512 is turned on, and the potential signal of the second potential terminal VGL is output to the SW 2', i.e., a low level signal is output, thereby achieving phase inversion.

In other embodiments, other circuit structures known to those skilled in the art may be adopted to implement the phase inversion logic of the inverter 951, which is not described and limited in this embodiment of the present invention.

In the above, improvements of the hardware circuit that realizes the timing adjustment are exemplified in conjunction with fig. 6 to 8. Hereinafter, timing adjustment in software improvement is exemplarily explained with reference to fig. 9 to 13.

Optionally, referring to fig. 9, the display panel 90 further includes a multi-path selection circuit 940, a plurality of data source lines 942 and m clock control signal lines 943, where the multi-path selection circuit 940 includes a plurality of multi-path selection units 941, an input end of one multi-path selection unit 941 is disposed corresponding to and electrically connected to one data source line 942, the multi-path selection unit 941 has m output ends and m control ends, m output ends of one multi-path selection unit 941 are disposed corresponding to and electrically connected to m data lines 932, and m clock control signal lines 943 are disposed corresponding to and electrically connected to m control ends of each multi-path selection unit 941.

Note that the structure of the display panel 90 is mainly different from the structure of the display panel 90 shown in fig. 6 in that: the inverter unit 950 connected to the multi-path selection unit 941 is not disposed in the display panel 90, and other structures of the display panel 60 may be the same as those of the display panel 90 shown in fig. 6, and the same points can be understood with reference to the above description.

On this basis, referring to fig. 10, the driving method of the display panel may include:

and S210, acquiring an image to be displayed.

Thereafter, S220 is performed, and S220 may include S221 and S222.

And S221, according to the image to be displayed, the clock control signal line provides a clock control signal, and the signal of the data source line provides a data signal to the data line through the multi-path selection unit under the control of the corresponding clock control signal.

The time sequence of the data signals is consistent with the time sequence of the corresponding clock control signals, and in the effective level period of each grid opening signal, a plurality of data signals corresponding to the same row are written into the sub-pixels corresponding to the row.

Exemplarily, referring to fig. 9 and 11, the Gate-on signal (Gate signal) includes a plurality of scan timing segments GAA sequentially arranged, which can be understood as including a high level period of a Gate1 signal, a high level period of a Gate2 signal, and a high level period of a Gate3 signal sequentially arranged; each scanning time sequence section GAA correspondingly triggers a row of sub-pixels 933; each clock control signal (such as SW1 ', SW2 ' and SW3 ') correspondingly controls the writing of Data signals (such as Data1, Data2 and Data3) of at least one column of sub-pixels; the same scanning time section GAA covers at least two clock control signals; the durations of the enable gaps Δ TS (also referred to as clock gaps Δ TS above) of the at least two clock control signals are unequal; enabling a time gap delta TS of the clock control signal is a time difference value between the non-enabling time of the jth clock control signal and the enabling time of the j +1 th clock control signal; j is a positive integer.

Wherein, the time sequence of the data signal is consistent with the time sequence of the clock control signal. Therefore, the unequal duration of the enabling gap delta TS of the at least two clock control signals can realize the unequal duration of the charging gap delta TD of the at least two data signals, so that the unfixed duration of the charging period of the data signals is facilitated, and the electromagnetic interference is facilitated to be reduced.

Meanwhile, in order to ensure that the display panel has a better display effect, the enabling level periods of the clock control signals are equal in duration, and further, the data writing periods of the data signals are equal in duration.

Wherein the enable level period of the clock control signal can be understood asThe time difference between the start enable time of the j clock control signals and the end enable time of the j clock control signals. For example, the enable level period of the clock control signal may be a long period of time in which a high level of the clock control signal in fig. 11 lasts. The whole duration of the enabling level period and the enabling gap adjacent to the enabling level period can be regarded as the clock period of a clock control signal; that is, "clock period" herein is understood to be a time interval between start times of two consecutive enable level periods in the clock control signal. Exemplarily, T is shown in FIG. 11 _S1 、T _S2 、T _S3 、T _S4 、T _S5 And T _S6 A plurality of clock periods are shown with different times being start enable times. It can be understood that the clock period in which the enable level period denoted by "j + 1" in fig. 11 is present ends by the time of the enable level of the Gate1 signal.

S222, the data line provides the data signal to the sub-pixel, and the scan line provides the gate-on signal to the sub-pixel.

Illustratively, the gate-on signals are supplied to the sub-pixels row by row through the scan lines to allow data signal writing; and writing a data signal into the sub-pixels of the opened row through the data line in the enabling level duration period of the gate opening signal of the sub-pixels of the current row so as to update the data signal.

And S230, displaying the image to be displayed according to the display signal.

Therefore, refreshing of one frame of image presented by the display panel is achieved.

On the basis of adjusting the timing of the clock control signal shown in fig. 10 and 11, the timing can be set in different ways, hereinafter in connection with the charging period T in fig. 11 _D1 、T _D2 、T _D3 、T _D4 、T _D5 And T _D6 And in conjunction with the clock period T _S1 、T _S2 、T _S3 、T _S4 、T _S5 And T _S6 The length of the clock period is exemplified by the cases.

Optionally, with reference to fig. 11, the durations of the enable gaps Δ TS of the clock control signals covered by the same scanning timing segment GAA are not equal, and the durations of the enable gaps Δ TS of the clock control signals at the same position of different scanning timing segments GAA are equal.

The number of the clock control signals covered by each scanning time sequence GAA can be the same, so that the adjustment mode of the clock control signals can be simplified, and the driving method is simpler.

Wherein, the enabling gap Δ TS of the clock control signal at the same position of different scanning time segments GAA can be understood as: the enable gap Δ TS of the clock control signal at a time position delayed by the same time length by the start time of the enable level of the respective scanning timing section GAA as a time start point.

Exemplarily, the 2 nd enable gap Δ TS covered by the scan timing segment GAA of the Gate1 signal, the 2 nd enable gap Δ TS covered by the scan timing segment GAA of the Gate2 signal, and the 2 nd enable gap Δ TS covered by the scan timing segment GAA of the Gate3 signal can be considered as the enable gap Δ TS of the clock control signal at the same position of 3 different scan timing segments GAA.

The time lengths of the enabling level time periods of the clock control signals are equal, and the clock time periods of the clock control signals covered by the same scanning time sequence section GAA are unequal by setting the enabling gaps delta TS of the clock control signals covered by the same scanning time sequence section GAA to be unequal; and setting the enabling intervals delta TS of the clock control signals at the same positions of different scanning time sequence sections GAA to be equal in time length, so that the clock time periods of the clock control signals at the same positions of different scanning time sequence sections GAA are equal.

Exemplary, T _S1 ＝T _S3 ＝T _S5 ，T _S2 ＝T _S4 ＝T _S6 ；T _S1 ≠T _S2 . Because the timing of the data signal is kept consistent with the timing of the clock control signal, based on this, it is possible to realize: t is a unit of _D1 ＝T _D3 ＝T _D5 ，T _D2 ＝T _D4 ＝T _D6 ；T _D1 ≠T _D2 Thereby, the inherent cycles of the data signal and the clock control signal can be destroyedPeriodically, the radiation energy can be dispersed at a plurality of different frequency positions, so that the energy peak value radiated to the periphery by the display panel can be reduced, and the electromagnetic interference can be improved; meanwhile, the time sequence adjustment mode is simple, and the driving method is simple and convenient.

Optionally, with reference to fig. 11, the enabling intervals Δ TS of the clock control signals covered by the same scanning timing section GAA are equal in duration but not equal to the enabling intervals Δ TS of the clock control signals covered by another scanning timing section GAA.

With such an arrangement, the adjustment mode of the clock control signal can be simplified while the difference of the time lengths of the at least two enabling gaps Δ TS, namely the difference of the time lengths Δ TD of the at least two charging gaps, is realized, so that the driving method is simpler.

The time lengths of the enabling level time periods of the clock control signals are equal, and the time lengths of the enabling gaps delta TS of the clock control signals covered by the same scanning time sequence section GAA are equal, so that the clock time periods of the clock control signals covered by the same scanning time sequence section GAA are equal; and by setting that the duration of the enable gap Δ TS is not equal to the duration of the enable gap Δ TS of the clock control signal covered by another scanning timing section GAA, the durations of the clock time periods covered by at least two different scanning timing sections GAA can be unequal, that is, the differential design of the clock time periods is realized, thereby realizing the differential design of the charging time periods of the data signals.

Exemplary, T _S1 ＝T _S2 ，T _S3 ＝T _S4 ，T _S5 ＝T _S6 (ii) a And T _S1 、T _S3 And T _S5 At least two clock periods are of unequal duration. Because the timing of the data signal is kept consistent with the timing of the clock control signal, based on this, it is possible to realize: t is _D1 ＝T _D2 ，T _D3 ＝T _D4 ，T _D5 ＝T _D6 (ii) a And T _D1 、T _D3 And T _D5 The time lengths of at least two clock periods are different, so that the inherent periodicity of the data signal and the clock control signal can be destroyed, the radiation energy can be dispersed at a plurality of different frequency positions, and the display panel direction can be reducedThe energy peak value of peripheral radiation is beneficial to improving electromagnetic interference; meanwhile, the time sequence adjustment mode is simple, and the driving method is simple and convenient.

Optionally, with reference to fig. 11, in a frame of the to-be-displayed picture, the durations of the enable gaps Δ TS of the clock control signals are not equal.

By the arrangement, the distribution of the radiation energy at different frequency positions can be more dispersed, so that the electromagnetic radiation can be reduced.

The time lengths of the enabling level time periods of the clock control signals are equal, and the time lengths of the enabling gaps delta TS of the clock control signals in a frame of picture to be displayed are different, so that the clock time periods of the clock control signals in the frame of picture to be displayed are different, namely the differential design of the clock time periods is realized, and the differential design of the charging time periods of the data signals is realized.

Exemplary, T _S1 ≠T _S2 ≠T _S3 ≠T _S4 ≠T _S5 ≠T _S6 . Because the timing of the data signal is kept consistent with the timing of the clock control signal, based on this, it is possible to realize: t is _D1 ≠T _D2 ≠T _D3 ≠T _D4 ≠T _D5 ≠T _D6 (ii) a Thus, the inherent periodicity of the data signal and the clock control signal can be destroyed, and the radiation energy can be dispersed at a plurality of different frequency positions, so that the energy peak value radiated to the periphery by the display panel can be reduced.

It should be noted that fig. 11 only exemplarily illustrates the timing adjustment manner by taking 9 clock periods, 9 charging periods, and 3 scan timing periods as an example. In other embodiments, the number of the scan timing segments, the number of the clock control signals covered by each scan timing segment, and the adjustment manner of the clock control signals may all be set according to actual requirements of the display panel and the driving method thereof, which is not limited in the embodiments of the present invention. It is understood that "timing adjustment" herein refers to a manner of changing the fixed period in the prior art to realize the time length differentiation of the clock period and the time length differentiation of the charging period.

In the above embodiment, when the data signals of the adjacent rows are written, the last color sub-pixel of the data signal written in the current row is the same as the first color sub-pixel of the data signal written in the next row, and the data signal can be set to continue from the current row to the next row, so that the frequency of data signal switching can be reduced, which is beneficial to reducing the power consumption of the display panel. This is exemplified below in connection with fig. 12-13.

Alternatively, referring to fig. 12 and 13, the sub-pixel 933 includes sub-pixels 933 of a plurality of different light emission colors; when the scanning timing section GAA is switched line by line, the data line 932 of the sub-pixel 933 of the same emission color is controlled by the multiplexing unit 941 to continuously input a data signal.

Illustratively, the sub-pixels may include a first color sub-pixel 9331, a second color sub-pixel 9332, and a third color sub-pixel 9333. In other embodiments, a sub-pixel of a fourth color or a sub-pixel of a plurality of colors may be further included, which may be set according to actual requirements of the display panel, and this is not limited in this embodiment of the present invention.

Taking the example that the sub-pixel 933 includes three sub-pixels 933 of different colors, when the display panel is driven, the first color sub-pixel 9331, the second color sub-pixel 9332 and the third color sub-pixel 9333 in the display panel are all lighted by color within the enabling period of the gate-on signal corresponding to one row of the sub-pixels 933. Since the difference between the voltage amplitudes of the data signals written in the sub-pixels 933 of different colors is large, when the data lines 932 corresponding to the sub-pixels 933 of different colors need to change with large voltage amplitudes for many times, the power consumption of the display panel driving circuit is large.

In the embodiment of the present invention, by setting the data line 932 for controlling the sub-pixels 933 of the same light-emitting color by using the multi-path selection unit 941 to continuously input the data signals, the amplitude difference based on the input data signals of the sub-pixels 933 of the same color is small, so that the continuous input of the data signals of the sub-pixels 933 of the same color can effectively reduce the voltage amplitude value change on the data line 932, thereby reducing the driving power consumption of the display panel.

Illustratively, referring to fig. 13, in the active level period of the Gate1 signal, data signals corresponding to the first color sub-pixel 9331, the second color sub-pixel 9332, and the third color sub-pixel 9333 are written in sequence; in the effective level period of the Gate2 signal, data signals corresponding to a third color sub-pixel 9333, a second color sub-pixel 9332 and a first color sub-pixel 9331 are written in sequence; in the active level period of the Gate3 signal, data signals corresponding to the first color sub-pixel 9331, the second color sub-pixel 9332, and the third color sub-pixel 9333 are sequentially written. Therefore, the sub-pixel 933 corresponding to the data signal written by the Gate1 signal at last and the sub-pixel 933 corresponding to the data signal written by the Gate2 signal at first are both the third color sub-pixel 9333; when the Gate1 signal and the Gate2 signal are switched, the voltage amplitude of the data signal on the data line 932 can be adjusted without switching the data signal; similarly, the sub-pixel 933 corresponding to the data signal written by the Gate2 signal last and the sub-pixel 933 corresponding to the data signal written by the Gate3 signal first are both the first color sub-pixel 9331; even when the Gate2 signal and the Gate3 signal are switched, the voltage amplitude of the data signal on the data line 932 may be adjusted without switching the data signal.

It should be noted that, when the scanning timing segment GAA is switched line by line, the data signal to be written to the sub-pixel 933 of the next row may be the same as or different from the data signal to be written to the sub-pixel 933 of the previous row. Based on this, if the data signal remains the same, the data potential is maintained at the same location; when the data signals are different, that is, when the data signals are changed, the data signals are switched from data written by the previous row of sub-pixels 933 to data written by the next row of sub-pixels 933 when the Gate1 is switched to the Gate2 or when the Gate2 is switched to the Gate 3.

It should be noted that, in other embodiments, the writing sequence of the data signals of the sub-pixels with different colors may be set according to the actual requirements of the display panel and the driving method thereof, so as to ensure that the colors of the adjacent sub-pixels in the adjacent rows are the same in the data signal writing process, which is not limited in the embodiment of the present invention. Alternatively, referring to fig. 12 and 13, in two adjacent rows of sub-pixels 933, the clock control signal of the data line corresponding to the sub-pixel 933 to which the data signal is last written in the k-th row (e.g., the 1 st row) is continuously maintained at the enable level to the clock control signal of the data line corresponding to the sub-pixel 933 to which the data signal is first input in the k + 1-th row (e.g., the 2 nd row), and the enable level of the clock control signal of the data line corresponding to the sub-pixel 933 which is the data signal is first input in the k + 1-th row (e.g., the 2 nd row); k is a positive integer.

Wherein the timing of the data signal is consistent with the timing of the clock control signal. By the arrangement, when the data signals are switched in the scanning time sequence section of the adjacent row, the data signals can be continuously written in, so that the switching times of the data signals are reduced, and the driving power consumption of the display panel is reduced.

For example, referring to fig. 13, one enable level period of the clock control signal (duration of high level denoted by "k" and "k + 1" in fig. 13) may span into the active level period of two Gate signals (Gate 1 signal and Gate2 signal in fig. 13); in this way, it is possible to realize that one data writing period of the data signal (the high level duration marked by "k" and "k + 1" in fig. 13) can span into the active level period of the two Gate signals, thereby reducing the number of switching of the clock control signal and the data signal and reducing the driving power consumption of the display panel.

It should be noted that fig. 13 also schematically shows a clock control signal MUX0 in the prior art, which is only used as a comparison example with the clock control signal MUX provided by the embodiment of the present invention. In the driving method of the display panel according to the embodiment of the present invention, the clock control signal MUX0 in the prior art is adjusted to change the inherent clock period (T) of the clock control signal _S0 ) The time length of the clock time interval is set differently, so that the electromagnetic interference phenomenon can be improved.

Optionally, with continued reference to fig. 12 and 13, the timing for inputting the data signal to the sub-pixel 933 of the k-th row (e.g., row 1) is sequentially: a first color sub-pixel 9331, a second color sub-pixel 9332, and a third color sub-pixel 9333; the timing at which the data signal is input to the sub-pixel 933 of the (k + 1) th row (for example, the 2 nd row) is sequentially: a third color sub-pixel 9333, a second color sub-pixel 9332, and a first color sub-pixel 9331; the light emission colors of the first color sub-pixel 9331, the second color sub-pixel 9332 and the third color sub-pixel 9333 are any one of red (R), green (G) and blue (B), and are different from each other.

In this way, when the gate on signals of the k-th row and the (k + 1) -th row are switched, that is, when the gate on signals of two adjacent rows are switched, the data signal input by the data line third color sub-pixel 9333 may not be interrupted, but only the amplitude of the data signal is changed, so that the number of times of switching the data signal and the clock control signal may be reduced, and the driving power consumption of the display panel may be reduced.

For example, the driving sequence of the sub-pixels 933 of the k-th and k + 1-th rows may include:

First, rgbgr;

second, RBGGBR;

third, GBRRBG;

fourth, GRBBRG;

fifth, BRGGRB;

sixth, BGRRGB.

In other embodiments, the number of the sub-pixels with different colors, the color of the sub-pixels, and the driving order in the display panel may all be set according to actual requirements of the display panel and the driving method thereof, which is not limited in the embodiments of the present invention.

On the basis of the foregoing embodiments, embodiments of the present invention further provide a display driving device, which can be used to execute the driving method provided by the foregoing embodiments. Therefore, the display driving apparatus also has the advantages of the driving method of the display panel provided by the above embodiments, and the same points are not repeated in the following, and can be understood by referring to the above.

For example, referring to fig. 14, the display driving apparatus 80 may include: an image obtaining module 810, configured to obtain an image to be displayed; a signal providing module 820, configured to provide display signals to the sub-pixels by using scan lines and data lines according to an image to be displayed; and an image display module 830, configured to display an image to be displayed according to the display signal.

The display signals comprise grid opening signals and data signals, and in one frame of scanning period, the grid opening signals are loaded to the scanning lines, and the corresponding data signals are sequentially loaded to the data lines; in a frame of picture to be displayed, the duration of at least two charging gaps is unequal. Therefore, the design of the time difference of the charging time interval of the data signal can be realized, the problem that the radiation energy at the fixed frequency position is overlarge due to the fixed time interval of the charging time interval of the data signal is solved, and the electromagnetic interference phenomenon caused by the fact that higher electromagnetic energy is radiated to the periphery of the display panel in the working process of the display panel is improved. For example, when the display panel is applied to a vehicle-mounted display screen, the influence of the display panel on other vehicle-mounted electronic products (such as a vehicle-mounted radio, a vehicle-mounted sound box or other vehicle-mounted display screens) can be reduced, and normal operation of the other vehicle-mounted electronic products is facilitated.

For example, the image capturing module 810 may be an IC connected to a motherboard in a mobile phone, or an IC connected to a display card in a computer, or other configurations known to those skilled in the art, and the embodiment of the invention is not limited thereto.

For example, the signal providing module 820 may include a scan driving circuit, a multiplexing circuit, and other circuit structures known to those skilled in the art, which are not described or limited in the embodiments of the present invention.

Illustratively, the image display module 830 may be a display panel.

It should be noted that, when the driving method of the display panel provided by the embodiment of the present invention is implemented by setting a hardware structure, the signal providing module 820 may further include an inverter, and may include other circuit structures capable of implementing signal delay.

On the basis of the foregoing embodiments, an embodiment of the present invention further provides an electronic device, where the electronic device includes any one of the display driving apparatuses provided in the foregoing embodiments, and therefore the electronic device also has the beneficial effects of the display driving apparatus provided in the foregoing embodiments and the driving method of the display panel, and the same points can be understood with reference to the foregoing description, and are not described in detail below.

For example, referring to fig. 15, the electronic device 70 includes the display driving apparatus 80 provided in the foregoing embodiment, a part of modules in the driving method performed by the display driving apparatus 80 may be integrated into a driving chip of the display panel, or the display driving apparatus 80 may be provided separately from the display panel, and signals may be transmitted between the display driving apparatus and the display panel through an electrical connection line, which is not limited in this embodiment of the present invention.

For example, the electronic device 70 may be a mobile phone, a computer, a smart wearable device (e.g., a smart watch), a vehicle-mounted display screen, a vehicle-mounted touch screen, or other types of electronic devices known to those skilled in the art, and the embodiments of the invention are not limited thereto. When the electronic device is applied to a vehicle such as an automobile, a ship or an airplane and used as a carrying display screen, the electronic device may be a local structure independent of an inherent structure in the vehicle or integrated with other structural components in the vehicle, for example, the electronic device may be integrated with a front windshield or integrated with a table top around an instrument panel, which is not limited in the embodiments of the present invention.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. The driving method of the display panel is characterized in that the display panel comprises scanning lines and data lines, the scanning lines and the data lines are intersected to define a plurality of sub-pixel regions, and sub-pixels are arranged in the sub-pixel regions; the driving method includes:

acquiring an image to be displayed;

displaying the image to be displayed according to the display signal;

the display signals comprise grid opening signals and data signals, and in one frame of scanning period, the grid opening signals are loaded to the scanning lines, and the corresponding data signals are sequentially loaded to the data lines; in one frame of the image to be displayed, the time lengths of at least two charging gaps are different; the charging gap is a time difference value between the initial writing time of the (i + 1) th data signal and the finishing writing time of the ith data signal; i is a positive integer;

the display panel further comprises a multi-path selection circuit, a plurality of data source lines and m clock control signal lines, wherein the multi-path selection circuit comprises a plurality of multi-path selection units, the input end of one multi-path selection unit is correspondingly arranged and electrically connected with one data source line, the multi-path selection unit is provided with m output ends and m control ends, the m output ends of one multi-path selection unit are respectively correspondingly arranged and electrically connected with the m data lines, and the m clock control signal lines are respectively correspondingly arranged and electrically connected with the m control ends of each multi-path selection unit; the display panel further includes an inverter unit including at least one inverter;

The m clock control signal lines comprise clock selection control signal lines, each clock selection control signal line comprises a first sub-line segment and a second sub-line segment, the first end of each first sub-line segment is electrically connected with the control end of the corresponding inverter unit, the first end of each second sub-line segment is electrically connected with the output end of the corresponding inverter unit, and the second end of each second sub-line segment is electrically connected with one control end of the corresponding multi-path selection unit;

a first signal transmitted by the first sub-line segment forms a second signal after passing through the inverter unit, and the second signal and the first signal have time delay; the number of inverters in at least two of the inverter units is different.

2. The driving method according to claim 1, wherein the clock selection control signal line includes a first control signal line and a second control signal line, and the m clock control signal lines further include a clock reference control signal line; the inverter unit corresponding to the first control signal line comprises an inverter, and the inverter unit corresponding to the second control signal line comprises two inverters which are connected in series; wherein

On the first control signal line, the second signal is delayed for a first time length relative to the first signal, and the second signal is opposite in phase to the first signal;

on the second control signal line, the second signal is delayed for a second time length relative to the first signal, and the phase of the second signal is the same as that of the first signal;

the clock reference control signal line is not provided with the inverter unit, and the signal of the output end of the clock reference control signal line is the same as the signal of the input end of the clock reference control signal line;

wherein the second duration is greater than the first duration.

3. The driving method according to claim 2, wherein the inverter includes a P-type transistor and an N-type transistor;

the control end of the P-type transistor and the control end of the N-type transistor are electrically connected to the first sub-line segment; the first end of the P-type transistor is electrically connected to a first potential end, the first end of the N-type transistor is electrically connected to a second potential end, and the potential of the first potential end is higher than that of the second potential end; and the second end of the P-type transistor is electrically connected with the second end of the N-type transistor and is electrically connected to the control end of the corresponding multi-path selection unit through the second sub-wire section.

4. The driving method of the display panel is characterized in that the display panel comprises scanning lines and data lines, the scanning lines and the data lines are intersected to define a plurality of sub-pixel regions, and sub-pixels are arranged in the sub-pixel regions; the driving method includes:

acquiring an image to be displayed;

displaying the image to be displayed according to the display signal;

the display panel further comprises a multi-path selection circuit, a plurality of data source lines and m clock control signal lines, wherein the multi-path selection circuit comprises a plurality of multi-path selection units, the input end of one multi-path selection unit is correspondingly arranged and electrically connected with one data source line, the multi-path selection unit is provided with m output ends and m control ends, the m output ends of one multi-path selection unit are respectively correspondingly arranged and electrically connected with the m data lines, and the m clock control signal lines are respectively correspondingly arranged and electrically connected with the m control ends of each multi-path selection unit;

In the driving method, the providing display signals to the sub-pixels by using the scan lines and the data lines according to the image to be displayed includes:

according to the image to be displayed, the clock control signal line provides a clock control signal, and the signal of the data source line provides a data signal to the data line through the multi-path selection unit under the control of the corresponding clock control signal;

the data line provides the data signal to the sub-pixel, and the scan line provides a gate turn-on signal to the sub-pixel;

the grid opening signal comprises a plurality of scanning time sequence sections which are sequentially arranged, and each scanning time sequence section correspondingly triggers one row of the sub-pixels; each clock control signal correspondingly controls the data signal writing of at least one column of the sub-pixels; the same scanning time sequence section covers at least two clock control signals; the enabling intervals of at least two clock control signals are different in duration; the enabling interval of the clock control signal is the time difference between the non-enabling time of the jth clock control signal and the enabling time of the jth +1 clock control signal; j is a positive integer.

5. The driving method according to claim 4, wherein the durations of the enable gaps of the clock control signals covered by the same scan timing segment are not equal, and the durations of the enable gaps of the clock control signals at the same position in different scan timing segments are all equal.

6. The driving method as claimed in claim 4, wherein the duration of the enable interval of the clock control signal covered by the same scan timing segment is equal to each other, but not equal to the duration of the enable interval of the clock control signal covered by another scan timing segment.

7. The driving method according to claim 4, wherein the lengths of the enable gaps of the clock control signals in one frame of the image to be displayed are not equal to each other.

8. The driving method according to claim 4, wherein the sub-pixels include sub-pixels of a plurality of different emission colors;

and when the scanning time sequence section is switched line by line, the data signals are continuously input by controlling the data lines of the sub-pixels with the same light-emitting color through the multi-path selection unit.

9. The driving method according to claim 8, wherein the clock control signal of the data line corresponding to the sub-pixel to which the data signal is written last in the k-th row among the sub-pixels in two adjacent rows continuously maintains the enable level to the clock control signal of the data line corresponding to the sub-pixel to which the data signal is input first in the k + 1-th row and serves as the enable level of the clock control signal of the data line corresponding to the sub-pixel to which the data signal is input first in the k + 1-th row; k is a positive integer.

10. The driving method according to claim 9, characterized in that:

the time sequence for inputting the data signals by the sub-pixels of the k-th row sequentially comprises the following steps: a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel;

the time sequence of the sub-pixels of the (k + 1) th row inputting the data signals is as follows in sequence: a third color sub-pixel, a second color sub-pixel and a first color sub-pixel;

wherein, the light emission colors of the first color sub-pixel, the second color sub-pixel and the third color sub-pixel are any one of red, green and blue respectively and are different from each other.

11. A display driving apparatus for performing the driving method according to any one of claims 1 to 10; the display driving device includes:

the image acquisition module is used for acquiring an image to be displayed;

12. An electronic device characterized by comprising the display drive apparatus according to claim 11.