CN110855257A - Automatic correction circuit for output offset voltage of class-D power amplifier circuit - Google Patents

Abstract

The invention discloses an automatic correction circuit for the output offset voltage of a class D power amplifier circuit, which can automatically detect the deviation of the output DC voltage when the class D power amplifier circuit starts to work, and correct the deviation through a control circuit, thereby reducing the startup time. POP noise.

Description

Class D power amplifier circuit output offset voltage automatic correction circuit

technical field

The invention relates to the technical field of circuits, in particular to an automatic correction circuit for output offset voltage of a class D power amplifier circuit.

Background technique

Class D power amplifier circuit is a switch-type power amplifier circuit. Its working principle is based on PWM mode. It compares the audio signal with the triangular wave, and outputs a PWM waveform whose pulse width is proportional to the amplitude of the audio signal. Then the amplitude of the PWM waveform is obtained. Amplify, and then restore the amplified PWM waveform to an amplified audio signal after filtering. Compared with linear power amplifier circuits, class D power amplifier circuits have the characteristics of high efficiency and less heat generation. Therefore, class D power amplifier circuits are widely used in the field of consumer electronic products such as smart TVs and smart phones.

Since the audio input of the class D power amplifier circuit must work at the bias point to transmit the audio input, the two differential input ends of the class D power amplifier circuit will be connected to capacitors. The capacitance of the two differential input terminals of the class D power amplifier circuit is charged to the bias point, but because the charging speed of the capacitance of the two differential input terminals is different, the two differential input terminals will form a differential input and amplify the output to form POP noise. Similarly, in the early stage of power failure of consumer electronic products, the discharge rates of the capacitors at the two differential input terminals are different, and the two differential input terminals will also form a differential input to form POP noise.

Therefore, various developers and staff have adopted different methods to solve the problem of POP noise in Class D power amplifier circuits. For example, as disclosed in a Chinese patent application "Method and Device for Noise Suppression of Class-D Power Amplifier and Class-D Power Amplifier for Noise Suppression" (Patent Publication No. CN200710199380.6), the method of suppressing noise using the delay method is disclosed. POP noise caused by voltage difference caused by mismatch of external input signals during the electrical process. Another example is a Chinese patent application "Class D Power Amplifier Circuit with POP Noise Suppression" (patent publication number CN201510514693.0) that uses a delay method to suppress noise, which aims to suppress the noise of the external input signal during the power-on process. POP noise caused by voltage difference due to matching.

However, according to the method disclosed in the above-mentioned document, the researchers further found that the above-mentioned method cannot effectively suppress the POP noise caused by the adaptation of the circuit itself. That is, in the prior art, during the power-on start-up process of the class D power amplifier, due to the influence of manufacturing process deviation and device mismatch, in the absence of an input signal, there will still be a DC voltage difference between the two output ends. , resulting in POP noise when powering on.

Therefore, there is an urgent need to provide a novel circuit that can automatically correct the output offset voltage of a class D power amplifier circuit.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an automatic correction circuit for the output offset voltage of a class D power amplifier circuit, which can automatically detect the deviation of the output DC voltage when the class D power amplifier circuit starts to work, and correct the deviation through the control circuit, thereby reducing the Small boot POP noise.

In order to solve the above problems, the present invention provides an automatic correction circuit for output offset voltage of a class D power amplifier circuit, which includes: a power amplifier module, including a power amplifier circuit; a detection module, electrically connected to the power amplifier module, the detection module The module is used to obtain the output voltage of the power amplifier circuit, and compare the output voltage with a reference voltage; a control logic module is electrically connected to the detection module, and the control logic module is used for according to the power amplifier The comparison result between the output voltage of the circuit and the reference voltage is logically processed, and a plurality of different control signals are output; an execution module is electrically connected to the control logic module and the power amplifier module respectively, and the execution module uses to receive a plurality of different control signals, and adjust the resistance value of the resistance array in the power amplifier module accordingly according to the control signals, so as to make the difference between the two outputs in the power amplifier module to the output voltage of the tube zero.

On the basis of the above technical solutions, the present invention can also be improved as follows.

Further, the resistor array includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor; wherein the first resistor, the third resistor The second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are all fixed resistors, and the seventh resistor and the eighth resistor are all variable resistors.

Further, the power amplifier module includes: a first operational amplifier, a second operational amplifier, a first capacitor, a second capacitor, a first comparator, a second comparator, a first gate driver, a second gate driver, a first output pair tube, a second output pair tube, and the resistor array; wherein one end of the first resistor is electrically connected to a positive input end, and the other end of the first resistor is electrically connected to a positive input end. One end is electrically connected to the first input end of the first operational amplifier and one end of the third resistor respectively; one end of the second resistor is electrically connected to a negative input end, and the other end of the second resistor is respectively is electrically connected to the second input end of the first operational amplifier and one end of the fourth resistor; the first output end of the first operational amplifier is electrically connected to the other end of the third resistor and the other end of the fourth resistor, respectively. one end of the fifth resistor, the second output end of the first operational amplifier is respectively electrically connected to the other end of the fourth resistor and one end of the sixth resistor; the other end of the fifth resistor is electrically connected to is electrically connected to one end of the seventh resistor, one end of the first capacitor and the first input end of the second operational amplifier; the other end of the sixth resistor is electrically connected to the eighth resistor respectively one end, one end of the second capacitor, and the second input end of the second operational amplifier; the first output end of the second operational amplifier is electrically connected to the other end of the first capacitor and the first A first input end of a comparator, a second output end of the second operational amplifier are respectively electrically connected to the other end of the second capacitor and the first input end of the second comparator; the first The second input terminal of the comparator and the second input terminal of the second comparator both receive a triangular wave signal, and the output terminal of the first comparator is electrically connected to the input terminal of the first gate driver, The output end of the second comparator is electrically connected to the input end of the second gate driver; the output end of the first gate driver is electrically connected to the first output pair tube; the second The output end of the gate driver is electrically connected to the second output pair tube; the other end of the seventh resistor is electrically connected to the first output end of the first output pair tube, and the other end of the eighth resistor is electrically connected to the first output end of the first output pair tube. One end is electrically connected to the second output end of the second output pair tube.

Further, the first output pair tube includes a first switch tube and a second switch tube electrically connected to the first switch tube; the second output pair tube includes a third switch tube and the third switch tube The fourth switch tube that is electrically connected to the tube.

Further, the detection module includes: a first filter, a second filter, a third comparator, and a fourth comparator; the input end of the first filter is electrically connected to the first output pair tube a first output end, the output end of the first filter is electrically connected to the first input end of the third comparator; the input end of the second filter is electrically connected to the second output pair tube The first output end of the second filter is electrically connected to the first input end of the fourth comparator; the second input end of the third comparator and the fourth comparator Each of the second input terminals receives a reference voltage, and the output terminal of the third comparator and the output terminal of the fourth comparator are both electrically connected to the control logic module.

Further, the control logic module includes a logic circuit, the first input terminal of the logic circuit is electrically connected to the output terminal of the third comparator, and the second input terminal of the logic circuit is electrically connected to the output terminal of the third comparator. the output end of the fourth comparator; the logic circuit is electrically connected to the power amplifier circuit.

Further, the execution module includes: a first output end of the logic circuit, a second output end of the logic circuit, and a third output end of the logic circuit; the first output end of the logic circuit outputs a a first control signal is sent to the seventh resistor in the resistor array to adjust the resistance value of the seventh resistor; the second output end of the logic circuit outputs a second control signal to the eighth resistor in the resistor array resistor to adjust the resistance value of the eighth resistor; the third output end of the logic circuit outputs a third control signal to the first switch in the power amplifier module, wherein two ends of the first switch are respectively electrically connected is electrically connected to one end of the first resistor and one end of the second resistor.

Further, both the first filter and the second filter are low-pass filters, wherein the low-pass filter includes an RC circuit or an RC active filter with an operational amplifier and an RC element.

Further, the third control signal outputs a high enable or a low enable according to the type of the first switch.

Further, the third control signal is electrically connected to the first switch through a delay circuit.

The advantage of the present invention is that the automatic correction circuit for the output offset voltage of the class D power amplifier circuit of the present invention can automatically detect the deviation of the output DC voltage when the class D power amplifier circuit starts to work, and correct the deviation through the control circuit, thereby reducing the POP noise at boot.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a schematic diagram of a framework of an automatic correction circuit for output offset voltage of a class D power amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of the output offset voltage automatic correction circuit of the class D power amplifier circuit in the embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of the resistor array shown in FIG. 2 .

FIG. 4 is a schematic circuit diagram of the first filter and the second filter shown in FIG. 2 .

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

The terms "first", "second", "third", etc. (if present) in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion.

In this patent document, the drawings discussed below and the embodiments used to describe the principles of the present disclosure are by way of illustration only and should not be construed as limiting the scope of the present disclosure. Those skilled in the art will understand that the principles of the invention may be implemented in any suitably arranged system. Exemplary embodiments will be described in detail, examples of which are illustrated in the accompanying drawings. Also, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. The same reference numbers in the figures refer to the same elements.

The terms used in the present specification are only used to describe specific embodiments, and are not intended to illustrate the concepts of the present invention. Expressions used in the singular cover expressions in the plural unless the context clearly indicates a different meaning. In the present specification, it should be understood that terms such as "including", "having" and "comprising" are intended to indicate the presence of the possibility of the features, numbers, steps, actions or combinations thereof disclosed in the present specification, and are not intended to be The possibility that one or more other features, numbers, steps, actions, or combinations thereof may be present or may be added is excluded. The same reference numbers in the drawings refer to the same parts.

An embodiment of the present invention provides an automatic correction circuit for output offset voltage of a class D power amplifier circuit. The detailed descriptions will be given below.

Referring to FIG. 1 , the present invention provides an automatic correction circuit for output offset voltage of a class D power amplifier circuit, which includes: a power amplifier module 110 , a detection module 120 , a control logic module 130 and an execution module 140 .

Specifically, the power amplifier module 110 includes a power amplifier circuit. The power amplifier circuit is a power amplifier circuit well known to those skilled in the art. In this embodiment, the power amplifier circuit is a class D power amplifier circuit, which is a switch-type power amplifier circuit. The working principle of the Class D power amplifier circuit is based on the PWM mode. The audio signal is compared with the triangular wave, and the output is a PWM waveform whose pulse width is proportional to the audio signal amplitude. Then the amplitude of the PWM waveform is amplified, and then the amplified PWM waveform is passed through After filtering, it reverts to an amplified audio signal.

The detection module 120 is electrically connected to the power amplifier module 110 , and the detection module 120 is used for acquiring the output voltage of the power amplifier circuit and comparing the output voltage with a reference voltage.

The control logic module 130 is electrically connected to the detection module 120, and the control logic module 130 is configured to perform logic processing according to the comparison result between the output voltage of the power amplifier circuit and the reference voltage, and output a plurality of different control signal. In this embodiment, the number of the control signals is three, but not limited to this.

The execution module 140 is electrically connected to the control logic module 130 and the power amplifier module 110 respectively. The execution module 140 is configured to receive a plurality of different control signals (such as CT1, CT2, CT3 shown in FIG. 2 ), and adjust the resistance value of the resistance array in the power amplifier module 110 accordingly according to the control signals , so that the difference between the output voltages of the two output pairs in the power amplifier module 110 is zero.

Further, the resistor array can stepwise increase or decrease the resistance value of the corresponding resistor in the resistor array according to the control signal, so that the two outputs in the power amplifier module 110 are equal to the tube output voltage. The difference between the two outputs gradually decreases until the difference between the output voltages of the two output pairs is zero, that is, the two are equal. In this way, it can effectively solve the influence of manufacturing process deviation and device mismatch in the class D power amplifier circuit in the prior art during the power-on and start-up process, and in the absence of an input signal, the two outputs are paired to the tube (as shown in FIG. 2 ). The output voltage of the label I7, I8) will still have the problem of DC voltage difference and cause POP noise when it is turned on.

Preferably, the difference between the output voltages of the two output-to-tubes is zero, that is, after the two are equal, the output voltage of the output-to-tubes is further adjusted to be the same as the reference voltage. At this time, the control signal of the control logic module 130 The resistor array is in a locked state, so that the resistance values of the corresponding resistors in the resistor array no longer change. In addition, a control signal in the control signal causes the first switch SW1 in the power amplifier circuit to be switched to an on state, so that the power amplifier circuit can receive an external input signal and is in a normal working state.

In this embodiment, the resistor array includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8 . The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are all fixed resistors. The seventh resistor R7 and the eighth resistor R8 are both variable resistors, and the seventh resistor R7 and the eighth resistor R8 serve as adjustable resistance resistors in the resistor array, and are subject to the control of the execution module 140 . Adjustment control. Of course, in other embodiments, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 It can also be designed as a variable resistor, which is also used as a resistor with an adjustable resistance value in the resistor array, and is adjusted and controlled by the execution module 140 .

In addition, the seventh resistor R7 and the eighth resistor R8 in the resistor array may further include a parallel resistor array or a series resistor array respectively according to the actual situation, and the specific structure is shown in FIG. 3 .

With reference to FIG. 2 , the circuit schematic diagram of the output offset voltage automatic correction circuit of the class D power amplifier circuit.

In this embodiment, the power amplifier module 110 includes: a first operational amplifier I1, a second operational amplifier I2, a first capacitor C1, a second capacitor C2, a first comparator I3, a second comparator I4, a first gate driver I5, a second gate driver I6, a first output pair tube I7, a second output pair tube I8 and the resistor array (not marked in the figure). One end of the first resistor R1 is electrically connected to a positive input end INP, and the other end of the first resistor R1 is electrically connected to the first input end of the first operational amplifier I1 and the third One end of the resistor R3; one end of the second resistor R2 is electrically connected to a negative input terminal INN, and the other end of the second resistor R2 is electrically connected to the second input terminal of the first operational amplifier I1 and the other end respectively. one end of the fourth resistor R4; the first output end of the first operational amplifier I1 is electrically connected to the other end of the third resistor R3 and one end of the fifth resistor R5, respectively, the first operational amplifier The second output end of I1 is electrically connected to the other end of the fourth resistor R4 and the other end of the sixth resistor R6 respectively; the other end of the fifth resistor R5 is electrically connected to the seventh resistor R7 respectively one end of the first capacitor C1 and the first input end of the second operational amplifier I2; the other end of the sixth resistor R6 is electrically connected to one end of the eighth resistor R8, the other end of the One end of the second capacitor C2 and the second input end of the second operational amplifier I2; the first output end of the second operational amplifier I2 is electrically connected to the other end of the first capacitor C1 and the first A first input terminal of a comparator I3, and a second output terminal of the second operational amplifier I2 are respectively electrically connected to the other terminal of the second capacitor C2 and the first input terminal of the second comparator I4; The second input terminal of the first comparator I3 and the second input terminal of the second comparator I4 both receive a triangular wave signal, and the output terminal of the first comparator I3 is electrically connected to the first The input terminal of the gate driver I5, the output terminal of the second comparator I4 is electrically connected to the input terminal of the second gate driver I6; the output terminal of the first gate driver I5 is electrically connected to the the first output pair tube I7; the output end of the second gate driver I6 is electrically connected to the second output pair tube I8; the other end of the seventh resistor R7 is electrically connected to the first output For the first output end of the tube I7, the other end of the eighth resistor R8 is electrically connected to the second output end of the second output pair of the tube I8.

Further, the first output pair tube I7 includes a first switch tube and a second switch tube electrically connected to the first switch tube. The second output pair tube I8 includes a third switch tube and a fourth switch tube electrically connected to the third switch tube. In this embodiment, the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are MOS transistors, which are not limited in other embodiments. That is, the first output pair transistor I7 includes a first MOS transistor M1 and a second MOS transistor M2 electrically connected to the first MOS transistor M1; the second output pair transistor I8 includes a third MOS transistor M3 and a fourth MOS transistor M4 electrically connected to the third MOS transistor M3. Specifically, the gate of the first MOS transistor M1 is electrically connected to the first gate driver I5, and the source of the first MOS transistor M1 is electrically connected to the drain of the second MOS transistor M2 , the drain of the first MOS transistor M1 receives an input voltage. The gate of the second MOS transistor M2 is electrically connected to the first gate driver I5, the drain of the second MOS transistor M2 is electrically connected to the source of the first MOS transistor M1, and the The source of the second MOS transistor M2 is grounded. The common connection point of the first MOS transistor M1 and the second MOS transistor M2 is electrically connected to the first output terminal of the first output pair transistor I7. Likewise, the gate of the third MOS transistor M3 is electrically connected to the second gate driver I6, the source of the third MOS transistor M3 is electrically connected to the drain of the fourth MOS transistor M4, The drain of the third MOS transistor M3 receives an input voltage. The gate of the fourth MOS transistor M4 is electrically connected to the second gate driver I6, the drain of the fourth MOS transistor M4 is electrically connected to the source of the third MOS transistor M3, and the The source of the fourth MOS transistor M4 is grounded. The common connection point of the third MOS transistor M3 and the fourth MOS transistor M4 is electrically connected to the first output terminal of the second output pair transistor I8. As shown in FIG. 2 , the first output end of the first output pair tube I7 and the first output end of the second output pair tube I8 are coupled to a load (the load is an electronic component, such as a speaker) , but not limited to).

In this embodiment, the detection module 120 includes: a first filter I9, a second filter I10, a third comparator I11, and a fourth comparator I12.

The input terminal of the first filter I9 is electrically connected to the first output terminal of the first output pair tube I7, and the output terminal of the first filter I9 is electrically connected to the third comparator I11. first input. That is, the input end of the first filter I9 is electrically connected to the common node of the first MOS transistor M1 and the second MOS transistor M2.

The input terminal of the second filter I10 is electrically connected to the first output terminal of the second output pair tube I8, and the output terminal of the second filter I10 is electrically connected to the fourth comparator I12. first input. The input end of the second filter I10 is electrically connected to the common node of the third MOS transistor M3 and the fourth MOS transistor M4.

The first filter I9 and the second filter I10 are both low-pass filters, wherein the low-pass filters include RC circuits or RC active filters with operational amplifiers and RC elements, as shown in Figure 4 shown.

The second input terminal of the third comparator I11 and the second input terminal of the fourth comparator I12 both receive a reference voltage, and the output terminal of the third comparator I11 and the fourth comparator I12 The output terminals are all electrically connected to the control logic module 130 .

Continuing to refer to FIG. 2 , in this embodiment, the control logic module 130 includes a logic circuit I13 , and the first input end of the logic circuit I13 is electrically connected to the output end of the third comparator I11 , The second input terminal of the logic circuit I13 is electrically connected to the output terminal of the fourth comparator I12. The logic circuit I13 is electrically connected to the power amplifier circuit.

The execution module 140 includes: a first output end of the logic circuit I13, a second output end of the logic circuit I13 and a third output end of the logic circuit I13; the first output end of the logic circuit I13 A first control signal CT1 is output to the seventh resistor R7 in the resistor array to adjust the resistance value of the seventh resistor R7; the second output terminal of the logic circuit I13 outputs a second control signal CT2 to the seventh resistor R7. The eighth resistor R8 in the resistor array is used to adjust the resistance value of the eighth resistor R8; the third output terminal of the logic circuit I13 outputs a third control signal CT3 to the first switch in the power amplifier module 110 SW1, wherein two ends of the first switch SW1 are respectively electrically connected to one end of the first resistor R1 and one end of the second resistor R2.

In this embodiment, further, the third control signal CT3 outputs a high enable or a low enable according to the type of the first switch SW1.

In this embodiment, the third control signal CT3 is directly electrically connected to the first switch SW1. Of course, in other embodiments, the third control signal may also be electrically connected to the first switch SW1 through a delay circuit.

After the output offset voltage automatic correction circuit of the class D power amplifier circuit of the present invention is powered on, the first switch SW1 is in a closed state to prevent external input signals (through the positive and negative input terminals) from entering the power amplifier circuit inside the chip. The voltage difference between the two output-to-tube output voltages is generated by the chip itself due to manufacturing process deviation and component mismatch. The two sets of output pair tube voltages are compared with the reference level after the low-pass filtering of the first filter I9 and the second filter I10 to generate three logic control signals CT1, CT2, CT3. The CT1 and CT2 respectively control the seventh resistor R7 and the eighth resistor R8 in the resistor array. The resistance array increases or decreases the corresponding resistance step by step according to the control signal, so that the voltage difference between the output and the output voltage of the tube is gradually reduced. After the output voltage of the output pair tube is the same as the reference level, the first control signal CT1 and the second control signal CT2 of the control logic circuit I13 make the resistor array in a locked state, and the resistance value of the corresponding resistor in the resistor array no longer occurs. At the same time, the third control signal CT3 switches the first switch SW1 to an on state, and the chip can accept an external input signal and is in a normal working state.

The advantage of the present invention is that the automatic correction circuit for the output offset voltage of the class D power amplifier circuit of the present invention can automatically detect the deviation of the output DC voltage when the class D power amplifier circuit starts to work, and correct the deviation through the control circuit, thereby reducing the POP noise at boot.

In addition, on the basis of the above technical solutions, the present invention can also be improved as follows.

The first switch SW1 is to prevent external input signals from entering the chip during the power-on process, and the first switch SW1 is connected to the first resistor R1 and the second resistor R2. This signal can also be connected to the near differential op amp terminals of the first resistor R1 and the second resistor R2.

As an improvement of the present invention, the third control signal CT3 controls the first switch SW1. While this signal controls the first switch SW1, the third resistor R3 and the fourth resistor R4 can also be short-circuited during the power-on process.

As an improvement of the present invention, the seventh resistor R7 and the eighth resistor R8 are used as the object (resistor array) of the execution module 140, and the fifth resistor R5 and the sixth resistor R6 can also be accepted and executed as the resistor array.

As an improvement of the present invention, the seventh resistor R7 and the eighth resistor R8 are used as the object (resistor array) of the execution module 140, and the third resistor R3 and the fourth resistor R4 can also be accepted and executed as the resistor array.

As an improvement of the present invention, the seventh resistor R7 and the eighth resistor R8 are used as the object (resistor array) of the execution module 140, and the first resistor R1 and the second resistor R2 can also be accepted and executed as the resistor array.

The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can also be made, and these improvements and modifications should also be regarded as It is the protection scope of the present invention.

Claims (10)

1. The utility model provides a D class power amplifier circuit output offset voltage automatic correction circuit which characterized in that includes:

the power amplifier module comprises a power amplifier circuit;

the detection module is electrically connected with the power amplifier module and is used for acquiring the output voltage of the power amplifier circuit and comparing the output voltage with a reference voltage;

the control logic module is electrically connected with the detection module and is used for carrying out logic processing according to the comparison result of the output voltage of the power amplification circuit and the reference voltage and outputting a plurality of different control signals;

and the execution module is electrically connected with the control logic module and the power amplifier module respectively, and is used for receiving a plurality of different control signals and correspondingly adjusting the resistance value of the resistor array in the power amplifier module according to the control signals so as to enable the difference value between the output voltages of the two output geminate transistors in the power amplifier module to be zero.

2. The automatic correction circuit for output offset voltage of class-D power amplifier circuit according to claim 1, wherein said resistor array comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor; the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are all fixed resistors, and the seventh resistor and the eighth resistor are all variable resistors.

3. The class-D power amplifier circuit output offset voltage auto-calibration circuit of claim 2, wherein the power amplifier module comprises: a first operational amplifier, a second operational amplifier, a first capacitor, a second capacitor, a first comparator, a second comparator, a first gate driver, a second gate driver, a first output pair transistor, a second output pair transistor and the resistor array; one end of the first resistor is electrically connected to a positive input end, and the other end of the first resistor is electrically connected to the first input end of the first operational amplifier and one end of the third resistor, respectively; one end of the second resistor is electrically connected with a negative input end, and the other end of the second resistor is respectively and electrically connected with the second input end of the first operational amplifier and one end of the fourth resistor; a first output end of the first operational amplifier is electrically connected to the other end of the third resistor and one end of the fifth resistor respectively, and a second output end of the first operational amplifier is electrically connected to the other end of the fourth resistor and one end of the sixth resistor respectively; the other end of the fifth resistor is electrically connected to one end of the seventh resistor, one end of the first capacitor and the first input end of the second operational amplifier respectively; the other end of the sixth resistor is electrically connected to one end of the eighth resistor, one end of the second capacitor and the second input end of the second operational amplifier respectively; a first output end of the second operational amplifier is electrically connected to the other end of the first capacitor and a first input end of the first comparator respectively, and a second output end of the second operational amplifier is electrically connected to the other end of the second capacitor and a first input end of the second comparator respectively; the second input end of the first comparator and the second input end of the second comparator both receive a triangular wave signal, the output end of the first comparator is electrically connected to the input end of the first grid driver, and the output end of the second comparator is electrically connected to the input end of the second grid driver; the output end of the first grid driver is electrically connected to the first output pair transistor; the output end of the second grid driver is electrically connected to the second output pair transistor; the other end of the seventh resistor is electrically connected to the first output end of the first output pair transistor, and the other end of the eighth resistor is electrically connected to the second output end of the second output pair transistor.

4. The automatic output offset voltage correction circuit of a class-D power amplifier circuit according to claim 3, wherein said first pair of output transistors comprises a first switch transistor and a second switch transistor electrically connected to said first switch transistor; the second output pair transistor comprises a third switch transistor and a fourth switch transistor electrically connected with the third switch transistor.

5. The circuit of claim 3, wherein the detection module comprises: the first filter, the second filter, the third comparator and the fourth comparator; the input end of the first filter is electrically connected to the first output end of the first output geminate transistor, and the output end of the first filter is electrically connected to the first input end of the third comparator; the input end of the second filter is electrically connected to the first output end of the second output geminate transistor, and the output end of the second filter is electrically connected to the first input end of the fourth comparator; the second input end of the third comparator and the second input end of the fourth comparator both receive a reference voltage, and the output end of the third comparator and the output end of the fourth comparator are both electrically connected to the control logic module.

6. The circuit of claim 5, wherein the control logic module comprises a logic circuit, a first input terminal of the logic circuit is electrically connected to the output terminal of the third comparator, and a second input terminal of the logic circuit is electrically connected to the output terminal of the fourth comparator; the logic circuit is electrically connected to the power amplifier circuit.

7. The circuit of claim 5, wherein the execution module comprises: a first output of the logic circuit, a second output of the logic circuit, and a third output of the logic circuit; the first output end of the logic circuit outputs a first control signal to a seventh resistor in the resistor array so as to adjust the resistance value of the seventh resistor; the second output end of the logic circuit outputs a second control signal to an eighth resistor in the resistor array so as to adjust the resistance value of the eighth resistor; and a third output end of the logic circuit outputs a third control signal to a first switch in the power amplifier module, wherein two ends of the first switch are electrically connected to one end of the first resistor and one end of the second resistor respectively.

8. The automatic output offset voltage correction circuit of class-D power amplifier circuit of claim 5, wherein said first filter and said second filter are both low pass filters, and wherein said low pass filters comprise RC type circuits or RC active filters with operational amplifiers and RC elements.

9. The class-D power amplifier circuit output offset voltage auto-calibration circuit of claim 7, wherein the third control signal outputs a high enable or a low enable according to a type of the first switch.

10. The class-D power amplifier circuit output offset voltage auto-calibration circuit of claim 7, wherein said third control signal is electrically connected to said first switch through a delay circuit.

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