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CN110828389A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN110828389A
CN110828389A CN201811600286.1A CN201811600286A CN110828389A CN 110828389 A CN110828389 A CN 110828389A CN 201811600286 A CN201811600286 A CN 201811600286A CN 110828389 A CN110828389 A CN 110828389A
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CN
China
Prior art keywords
wiring
substrate
semiconductor device
electrically connected
pad electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811600286.1A
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English (en)
Inventor
片冈忠
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Kioxia Corp
Original Assignee
Toshiba Memory Corp
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Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of CN110828389A publication Critical patent/CN110828389A/zh
Pending legal-status Critical Current

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Abstract

实施方式提供一种能够抑制来自镀覆布线的腐蚀向内部布线前进的半导体装置及其制造方法。本实施方式的半导体装置具备基板、焊垫电极、内部布线、第1布线、绝缘物、半导体芯片、及第1树脂。基板具有第1面、该第1面的相反侧的第2面、及从第1面的端部向上升至第2面的端部的面即侧面。焊垫电极设置在基板的第1面侧。内部布线设置在基板内，且电连接在焊垫电极。第1布线设置在基板内，且在侧面从基板露出。绝缘物设置在第1布线与内部布线之间，将第1布线与内部布线之间分离。半导体芯片设置在第1面，且电连接在焊垫电极。第1树脂被覆半导体芯片。

Description

半导体装置及其制造方法
[相关申请]
本申请享有以日本专利申请2018-148750号(申请日：2018年8月7日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本实施方式涉及一种半导体装置及其制造方法。
背景技术
BGA(Ball Grid Array package，球栅阵列封装)封装等半导体封装是在布线基板上搭载半导体芯片，将半导体芯片与布线基板连接，并利用树脂被覆半导体芯片而形成。在此种半导体封装中，布线基板的接合垫的表面经金属材料进行镀覆处理。在使用电镀法对接合垫的表面进行镀覆处理的情况下，为了对接合垫施加电压，必须设置电连接在接合垫的镀覆布线。
镀覆布线共同设置在单片化前的多个布线基板，在同时对多个布线基板进行镀覆处理时被用作电极。镀覆处理后，当对布线基板进行单片化时，位于切割线的镀覆布线被去除，但一部分镀覆布线残留在布线基板并从布线基板的外侧面露出。
发明内容
实施方式提供一种能够抑制来自镀覆布线的腐蚀向内部布线前进的半导体装置及其制造方法。
本实施方式的半导体装置具备基板、焊垫电极、内部布线、第1布线、绝缘物、半导体芯片、及第1树脂。基板具有第1面、该第1面的相反侧的第2面、及从第1面的端部向上升至第2面的端部的面即侧面。焊垫电极设置在基板的第1面侧。内部布线设置在基板内，且电连接在焊垫电极。第1布线设置在基板内，且在侧面从基板露出。绝缘物设置在第1布线与内部布线之间，将第1布线与内部布线之间分离。半导体芯片设置在第1面，且电连接在焊垫电极。第1树脂被覆半导体芯片。
附图说明
图1是表示第1实施方式的半导体装置的构成例的剖视图。
图2是表示接合垫及其周边构成的剖视图。
图3是表示第1实施方式的树脂基板的构成例的俯视图。
图4(A)～(C)是表示第1实施方式的半导体装置的制造方法的一例的图。
图5(A)及(B)、图6(A)及(B)、图7(A)及(B)、图8(A)及(B)、图9(A)及(B)、图10是表示基板面板的制造方法的剖视图。
图11是表示第2实施方式的半导体装置的构成例的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。本实施方式并不限定本发明。在以下的实施方式中，基板的上下方向表示将设置着半导体芯片的面设为上方的情况下的相对方向，存在与依据重力加速度的上下方向不同的情况。附图是示意图或概念图，各部分的比率等未必与实物相同。在说明书与附图中，对于关于已经出现过的附图而在上文中说明过的要素相同的要素标注相同的符号，并适当省略详细的说明。
(第1实施方式)
图1表示第1实施方式的半导体装置的构成例的剖视图。本实施方式的半导体装置1是面安装型的半导体封装，例如可以为BGA(Ball Grid Array package)、MAP(Mold ArrayPackage，模塑型封装)、LGA(Land Grid Array Package，焊盘网格阵列封装)或CSP(ChipSize Package，芯片尺寸封装)等。半导体装置1例如也可以为NAND(Not AND，与非) 型闪速存储器等半导体存储装置。
半导体装置1具备树脂基板10、半导体芯片41、42、模具树脂50、及金属球60。
树脂基板10具有第1面F1、第1面F1的相反侧的第2面F2、及位于第1面F1与第2面F2之间的侧面F3。树脂基板10的平面形状并无特别限定，可以为大致长方形或者大致正方形。树脂基板10例如可以为将多个绝缘层11与多个布线层12积层并一体化而成的多层布线基板。绝缘层11例如使用玻璃环氧树脂、有机高分子材料或陶瓷材料(例如氧化铝(Al2O3))等。作为内部布线的布线层12设置在树脂基板10内，并电连接在接合垫BP。布线层12例如使用铜等低电阻的导电性材料。此外，布线层12的布局任意，能够根据半导体装置1来变更设计。
在树脂基板10的第1面F1设置着阻焊剂SR、及作为焊垫电极的接合垫BP。未在接合垫BP上设置阻焊剂SR，而在第1面F1上，接合垫BP从阻焊剂SR露出。接合垫 BP的电极材料主要是由与布线层12相同的材料(例如铜)构成，其表面如图2所示那样经金属膜13、14进行镀覆处理。
图2是表示图1的虚线框B的接合垫BP及其周边构成的剖视图。金属膜13、14 例如使用镍、金等低电阻性导电性材料。如果将金属膜13设为镍、将金属膜14设为金，那么金属膜13、14成为镍及金的积层膜。金属膜13、14例如是使用电镀法成膜在接合垫BP的电极材料(例如铜)的表面。金属膜13的镍将作为金属膜14的金与作为电极材料的铜之间相对牢固地接合。金属膜14的金是用于当接合金属导线20时将金属导线20 以低电阻接合在接合垫BP而设置。金属导线20使用与金属膜14相同的材料(例如金)。由此，金属导线20能够相对牢固地接合在金属膜14。
在树脂基板10的侧面F3设置作为第1布线的镀覆布线15。镀覆布线15设置在树脂基板10内，在侧面F3从树脂基板10露出。镀覆布线15作为布线层12的一部分，是由与布线层12相同的材料构成。例如，镀覆布线15使用铜。镀覆布线15是用来将金属膜13、14镀覆处理在接合垫BP表面的布线，在进行镀覆处理时，经由布线层12 电连接在接合垫BP。镀覆处理后，在镀覆布线15与布线层12之间设置凹部16，而将镀覆布线15与布线层12之间电性且物理分离。因此，在所完成的半导体装置1中，镀覆布线15与布线层12分断而成为电性浮动状态。如此一来，镀覆布线15从树脂基板 10的侧面F3露出，并且与布线层12分断。
半导体芯片41、42经由粘接层(DAF(Die Attachment Film，芯片粘接膜))30粘接在树脂基板10的第1面F1上。半导体芯片41例如可以为NAND型闪速存储器的控制器芯片。半导体芯片42例如可以为NAND型闪速存储器的存储器芯片。半导体芯片41、 42经由金属导线20电连接在树脂基板10的接合垫BP。此外，半导体芯片41、42并不限定于NAND型闪速存储器的控制器芯片或存储器芯片，可以为任意半导体芯片。
作为第1树脂的模具树脂50在树脂基板10的第1面F1上被覆半导体芯片41、42 及金属导线20，保护它们免受半导体装置1的外部的伤害。另外，在树脂基板10的第 1面F1设置着凹部16，模具树脂50进入并填充至凹部16内。凹部16内的模具树脂50 将镀覆布线15与布线层12之间绝缘。因此，在凹部16内，镀覆布线15的切断面由模具树脂50被覆而与模具树脂50接触。
在本实施方式中，镀覆布线15设置在相比于第2面F2更靠近第1面F1。因此，凹部16形成在树脂基板10的第1面F1，并将镀覆布线15与布线层12之间分离。另外，在设置着凹部16的镀覆布线15与布线层12之间的区域上，不仅将镀覆布线15去除，还将阻焊剂膜去除。在该凹部16中填充着模具树脂50。
在树脂基板10的第2面F2上设置着金属球60。虽未图示，但金属球60连接在位于第2面F2侧的布线层12，并经由布线层12电连接在半导体芯片41、42中的任一个。金属球60例如使用焊料等导电性金属。此外，也可以为平坦的焊盘部以代替金属球60。
图3是表示第1实施方式的树脂基板10的构成例的俯视图。图3的俯视图是从第1面F1侧观察时的俯视图。布线层12_1是第1信号线，布线层12_2是第2信号线，布线层12_3是第3信号线。另外，布线层12_4是接地布线或电源布线。以下，12_1～12_3 称为第1～第3信号线，12_4称为接地/电源布线。
第1～第3信号线12_1～12_3是向控制器芯片41或NAND型存储器芯片42传递控制信号或数据的布线。接地/电源布线12_4是连接在地面或电源的布线，用作控制器芯片41或NAND型存储器芯片42的地线或电源。第1～第3信号线12_1～12_3及接地/电源布线12_4由设置在第1面F1上的阻焊剂SR被覆。
接合垫BP连接在第1～第3信号线12_1～12_3及接地/电源布线12_4中的任一个，为了将金属导线20接合而从阻焊剂SR露出。
此处，为了对接合垫BP的表面进行电镀处理，在镀覆处理时，必须将接合垫BP 电连接在外部电极(未图示)。镀覆处理时尚未形成凹部16、18，接地/电源布线12_4连接在镀覆布线15_1。由此，接地/电源布线12_4经由镀覆布线15_1电连接在外部电极。第3信号线12_3连接在镀覆布线15_2，经由镀覆布线15_2电连接在外部的镀覆用电极。进而，第1信号线12_1经由镀覆布线17_1电连接在接地/电源布线12_4。第2信号线 12_2经由镀覆布线17_2电连接在接地/电源布线12_4。由此，第1及第2信号线12_1、 12_2经由镀覆布线17_1、17_2及接地/电源布线12_4电连接在镀覆布线15_1。结果，在镀覆处理时，所有接合垫BP均能够电连接在镀覆布线15_1、15_2中的任一个而被进行电镀处理。
另一方面，如果在电镀处理之后形成凹部16，那么从侧面F3露出的镀覆布线15_1、15_2与接地/电源布线12_4及第3信号线12_3分离。在后续步骤中向凹部16中填充模具树脂50。因此，在镀覆布线15_1与接地/电源布线12_4之间及镀覆布线15_2与第3 信号线12_3之间设置模具树脂50。由此，从镀覆布线15_1、15_2的露出部前进的腐蚀在模具树脂50被阻止，而不会前进至接地/电源布线12_4及第3信号线12_3。因此，凹部16及其内部的模具树脂50能够保护接地/电源布线12_4及第3信号线12_3免受腐蚀。
另外，如果形成凹部18，那么第1及第2信号线12_1、12_2与接地/电源布线12_4 之间被电切断。随之，第1及第2信号线12_1、12_2也相互电分离。由此，第1及第2 信号线12_1、12_2能够分别将单个信号(控制信号或数据)传递至控制器芯片41或NAND 型存储器芯片42。另外，接地/电源布线12_4能够向控制器芯片41或NAND型存储器芯片42施加接地电压或电源电压。
接下来，对本实施方式的半导体装置1的制造方法进行说明。
图4(A)～图4(C)是表示第1实施方式的半导体装置1的制造方法的一例的图。首先，为了形成树脂基板10，形成如图4(A)所示那样的多个树脂基板10连接而成的基板面板100。在基板面板100内，相邻的多个树脂基板10由镀覆布线15连接。也就是说，相邻的多个树脂基板10的镀覆布线15遍及多个树脂基板10间而设置，且在多个树脂基板10间被连接。另外，沿着相邻的树脂基板10间的切割区域DA设置共用镀覆布线15m，且相邻的树脂基板10各自的镀覆布线15连接在该共用镀覆布线15m。共用镀覆布线15m 延伸至基板面板100的外周，且共用镀覆布线15m的一端部从基板面板100的侧面露出。共用镀覆布线15m电连接在基板面板100内的多个树脂基板10的接合垫BP(参照图3)。由此，能够从基板面板100的外部经由共用镀覆布线15m对接合垫BP施加电压，从而能够以基板面板100的状态同时对多个树脂基板10的接合垫BP进行镀覆处理。
镀覆处理之后，使用光刻技术及蚀刻技术形成图3的凹部16、18，将镀覆布线15_1、15_2从布线层12_1～12_4切断。参照图5(A)～图10在下文中对凹部的形成步骤更详细地进行说明。
接下来，使用切割刀片对基板面板100进行切割。此时，切割刀片将相邻的树脂基板10间的切割区域DA与共用镀覆布线15m一起去除。在切割步骤中，如图4(B)及图 4(C)所示，在包含多个树脂基板10的区块99将基板面板100切断，进而，将该区块99 切断，由此单片化成树脂基板10。由此，将相邻区块99间的共用镀覆布线15m及相邻树脂基板10间的镀覆布线15切断。但是，镀覆布线15在树脂基板10的各端部少量残留，在侧面F3露出。树脂基板10如图1所示那样被用作控制器芯片41及存储器芯片 42的安装基板。
图5(A)～图10是表示图4(A)的基板面板100的制造方法的剖视图。图5(A)～图10表示与图4(A)所示的基板面板100的1个树脂基板10对应的端面。
首先，如图5(A)所示，例如在包含玻璃环氧树脂的绝缘层(预浸体)11的两面形成布线层(例如铜膜)12。绝缘层11及布线层12的积层构造109被搭载在支持基板101上。
接下来，如图5(B)所示，使用光刻技术及蚀刻技术将位于积层构造109上表面的布线层12加工成所需的布线图案。进而，如图6(A)所示，在积层构造109上积层另一绝缘层11及另一布线层12。如此一来，形成将多个绝缘层11与多个布线层12积层并一体化而成的积层构造109。
将积层构造109从支持基板101分离后，使用光刻技术及蚀刻技术如图6(B)所示那样，在积层构造109的上表面及背面形成到达至内部的布线层12的VIA孔。
在向VIA孔中填充导电体(例如铜)后，如图7(A)所示，进而将另一布线层12积层在积层构造109的上表面及背面。
接下来，使用光刻技术及蚀刻技术，如图7(B)所示，对位于积层构造109的上表面及背面的布线层12进行加工。
接下来，如图8(A)所示，在积层构造109的正面及背面形成阻焊剂SR，使用光刻技术及蚀刻技术将接合垫BP及焊料球60的形成区域Rbp的阻焊剂SR去除。同时，也将图3所示的凹部16、18的形成区域Rc的阻焊剂SR去除。
接下来，如图8(B)所示，使用光刻技术在区域Rc形成掩模120。
接下来，如图9(A)所示，对形成接合垫BP及焊料球60的区域Rbp进行电镀处理。此时，布线层12与镀覆布线15电连接，能够通过电镀在区域Rbp形成金属膜13、14。此时，因为在区域Rc设置着掩模120，所以金属膜13、14并未被镀覆在凹部16、18 的形成区域Rc。
接下来，如图9(B)所示，在将掩模120去除后，如图10所示，将阻焊剂SR用作掩模来对区域Rc的布线层12进行蚀刻。由此，形成凹部16、18，而将镀覆布线15从布线层12切断。另外，图3的布线17_1、17_2也被切断。此时，金属膜13、14也会略微受到蚀刻，但是能够通过例如使用如金那样难以被蚀刻的材料而残留下来。
此种积层构造109是以图4(A)的基板面板100的状态形成，之后，进行切割而单片化成图4(C)所示的树脂基板10。
进而，如图1所示，利用粘接层30将半导体芯片41、42粘接在树脂基板10上，并利用金属导线20将半导体芯片41、42的焊垫(未图示)与树脂基板10的接合垫BP之间接合。
接下来，在树脂基板10的第1面F1上形成模具树脂50，利用模具树脂50被覆半导体芯片41、42及金属导线20。此时，图10的凹部16、18由模具树脂50填充。由此，模具树脂50将半导体芯片41、42密封，并且设置在镀覆布线15与布线层12之间，而将镀覆布线15与布线层12之间电分离。
在将镀覆布线15与布线层12之间连接的情况下，如果在高温多湿的环境下使用半导体封装，那么存在从露出至树脂基板10的外侧面的镀覆布线15开始腐蚀的顾虑。如果腐蚀前进，那么存在腐蚀会到达连接在镀覆布线15的接合垫、进而连接在接合垫的信号布线、电源布线、接地布线等布线层12的顾虑。接合垫、信号布线、电源布线、接地布线等的腐蚀成为故障等的原因。
相对于此，根据本实施方式，通过在镀覆布线15与布线层12之间设置模具树脂50，从镀覆布线15的露出部开始前进的腐蚀在模具树脂50被阻止，从而能够抑制腐蚀前进至内部的布线层12(例如图3的接地/电源布线12_4及信号线12_3)。
(第2实施方式)
图11是表示第2实施方式的半导体装置的构成例的剖视图。在第2实施方式中，镀覆布线15不仅设置在第1面F1侧，还设置在第2面F2侧。例如，图11的镀覆布线 15a设置在相比于第2面F2更靠近第1面F1。然而，镀覆布线15b设置在相比于第1 面F1更靠近第2面F2。在此情况下，为了将镀覆布线15a从布线层12切断而在第1 面F1设置凹部16。为了将镀覆布线15b从布线层12切断而在第2面F2设置凹部26。如上所述，第2实施方式在第2面F2也具有凹部26这一点与第1实施方式不同。在设置在第2面F2的凹部26中填充供给至树脂基板10与供半导体装置1安装的安装基板 200之间的底部填充树脂300。第2实施方式的其它构成可以与对应的第1实施方式的构成相同。
凹部26在制造半导体装置1时成为空腔并曝露在大气中。在将半导体装置1安装在安装基板200时，向半导体装置1的第2面F2与安装基板200之间供给底部填充树脂300。底部填充树脂300将半导体装置1粘接在安装基板200上，并且填充至凹部26 内。由此，底部填充树脂300将镀覆布线15b与布线层12之间电分离。如上所述，通过在镀覆布线15b与布线层12之间设置底部填充树脂300，能够抑制从树脂基板10的侧面F3中的镀覆布线15b的露出部前进的腐蚀前进至布线层12。
镀覆布线15a与第1实施方式同样地，通过凹部16及填充至该凹部16中的模具树脂50而与布线层12电分离。因此，第2实施方式也能够获得第1实施方式的效果。
已对本发明的若干实施方式进行了说明，但这些实施方式是作为例子而提出的，并无意图限定发明的范围。这些实施方式能够以其它各种方式加以实施，且能够在不脱离发明主旨的范围内进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或主旨中，同样包含在权利要求书所记载的发明与其均等的范围内。
[符号的说明]
1 半导体装置
10 树脂基板
41、42 半导体芯片
50 模具树脂
60 金属球
F1 第1面
F2 第2面
F3 侧面
11 绝缘层
12(12_1～12_4) 布线层
13、14 金属膜
15(15_1、15_2、15a、15b) 镀覆布线
16、26 凹部
BP 接合垫
20 金属导线
30 粘接层

Claims (9)

1.一种半导体装置，具备：
基板，具有第1面、该第1面的相反侧的第2面、及从所述第1面的端部向上升至所述第2面的端部的面即侧面；
焊垫电极，设置在所述基板的第1面侧；
内部布线，设置在所述基板内，并电连接在所述焊垫电极；
第1布线，设置在所述基板内，并在所述侧面从所述基板露出；
绝缘物，设置在所述第1布线与所述内部布线之间，将所述第1布线与所述内部布线之间分离；
半导体芯片，设置在所述第1面，并电连接在所述焊垫电极；以及
第1树脂，被覆所述半导体芯片。
2.根据权利要求1所述的半导体装置，其中所述焊垫电极具有设置在焊垫电极上的金属镀覆膜，
所述第1布线是用来对所述焊垫电极表面的所述金属膜进行电镀处理的镀覆布线。
3.根据权利要求1所述的半导体装置，其中所述第1布线为电性浮动状态。
4.根据权利要求1所述的半导体装置，其中所述基板在所述第1布线与所述内部布线之间具有凹部，
所述第1布线在所述凹部内的切断面与所述绝缘物接触。
5.根据权利要求1所述的半导体装置，其中所述第1布线设置在相比于所述第2面更靠所述第1面，
所述绝缘物为所述第1树脂。
6.一种半导体装置，具备：
基板，具有第1面、该第1面的相反侧的第2面、及从所述第1面的端部向上升至所述第2面的端部的面即侧面；
焊垫电极，设置在所述基板的第1面，且具有金属镀覆膜；
内部布线，设置在所述基板内，且电连接在所述焊垫电极；
第1布线，在所述基板内设置在相比于所述第2面更靠所述第1面，在所述侧面从所述基板露出，且处于电性浮动状态；
绝缘物，在将所述第1布线与所述内部布线分离的凹部内的切断面与所述第1布线及所述内部布线接触；
半导体芯片，设置在所述第1面，且电连接在所述焊垫电极；
第1树脂，被覆所述半导体芯片；以及
所述第2面的端子，与所述内部布线电连接。
7.一种半导体装置的制造方法，包括如下步骤：
准备具有第1面及该第1面的相反侧的第2面，在所述第1面与所述第2面之间形成着内部布线，在所述第1面具有与所述内部布线电连接的焊垫电极的基板、
将多个所述基板物理连接且相邻的所述基板彼此通过与所述内部布线电连接的第1布线电连接的区块、及
将多个所述区块物理连接且相邻的所述区块彼此通过与所述第1布线电连接且一部分露出至外部的第2布线电连接的基板面板；
对所述第2布线施加电流，而在所述焊垫电极形成金属膜；
在所述基板形成将所述第1布线与所述内部布线分离的凹部；
将所述面板切断并分离成所述区块；
在所述基板积层与所述焊垫电极电连接的半导体芯片；
利用树脂被覆所述基板与所述半导体芯片；以及
将所述区块切断并分离成所述基板。
8.根据权利要求7所述的半导体装置的制造方法，其中所述凹部是通过蚀刻形成。
9.根据权利要求7或8所述的半导体装置的制造方法，其中所述内部布线包含铜，
在所述第2面设置着与所述内部布线电连接的端子。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113823603A (zh) * 2020-06-19 2021-12-21 铠侠股份有限公司 半导体装置及其制造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11716117B2 (en) * 2020-02-14 2023-08-01 Texas Instruments Incorporated Circuit support structure with integrated isolation circuitry
JP2023121355A (ja) * 2022-02-21 2023-08-31 キオクシア株式会社 半導体装置および半導体装置の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004055846A (ja) * 2002-07-19 2004-02-19 Matsushita Electric Works Ltd プリント配線板の配線パターン絶縁方法並びにその方法で配線パターンが絶縁されたプリント配線板を備える火災感知器
US7902660B1 (en) * 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
JP2011170948A (ja) * 2010-01-25 2011-09-01 Dainippon Printing Co Ltd サスペンション用基板、外枠付サスペンション用基板、サスペンション用基板の製造方法、外枠付サスペンション用基板の製造方法、サスペンション、素子付サスペンションおよびハードディスクドライブ
CN102802352A (zh) * 2012-08-22 2012-11-28 广州市鸿利光电股份有限公司 一种便于电镀的cob基板及其制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4719424B2 (ja) 2004-03-15 2011-07-06 ルネサスエレクトロニクス株式会社 パッド
JP2005327984A (ja) 2004-05-17 2005-11-24 Shinko Electric Ind Co Ltd 電子部品及び電子部品実装構造の製造方法
JP6050975B2 (ja) 2012-03-27 2016-12-21 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
JP6163421B2 (ja) * 2013-12-13 2017-07-12 株式会社東芝 半導体装置、および、半導体装置の製造方法
JP2015154032A (ja) * 2014-02-19 2015-08-24 株式会社東芝 配線基板とそれを用いた半導体装置
US9343434B2 (en) * 2014-02-27 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Laser marking in packages
JP6414637B2 (ja) * 2015-06-04 2018-10-31 株式会社村田製作所 高周波モジュール
JP2017041617A (ja) * 2015-08-21 2017-02-23 株式会社東芝 電子装置基板及び磁気シールドパッケージ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004055846A (ja) * 2002-07-19 2004-02-19 Matsushita Electric Works Ltd プリント配線板の配線パターン絶縁方法並びにその方法で配線パターンが絶縁されたプリント配線板を備える火災感知器
US7902660B1 (en) * 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
JP2011170948A (ja) * 2010-01-25 2011-09-01 Dainippon Printing Co Ltd サスペンション用基板、外枠付サスペンション用基板、サスペンション用基板の製造方法、外枠付サスペンション用基板の製造方法、サスペンション、素子付サスペンションおよびハードディスクドライブ
CN102802352A (zh) * 2012-08-22 2012-11-28 广州市鸿利光电股份有限公司 一种便于电镀的cob基板及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113823603A (zh) * 2020-06-19 2021-12-21 铠侠股份有限公司 半导体装置及其制造方法

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