CN110827898B

CN110827898B - Voltage-resistance type reversible logic circuit based on memristor and operation method thereof

Info

Publication number: CN110827898B
Application number: CN201910999054.6A
Authority: CN
Inventors: 缪向水; 杨岭; 李祎; 程龙; 黄晓弟
Original assignee: Huazhong University of Science and Technology
Current assignee: Huazhong University of Science and Technology
Priority date: 2019-10-21
Filing date: 2019-10-21
Publication date: 2021-07-27
Anticipated expiration: 2039-10-21
Also published as: CN110827898A

Abstract

The invention belongs to the field of microelectronic devices, and provides a voltage-resistance reversible logic circuit based on a memristor and an operation method thereof. The method comprises the steps that a memristor array is utilized and comprises word lines, bit lines, memristor units and grounding resistors, wherein the memristor units are used as operation units and comprise input units and output units; one end of each memristor unit is connected with a word line, the other end of each memristor unit is connected with a corresponding bit line, and the other end of each word line is connected with a grounding resistor; the input unit is used for writing in corresponding input signals, the bit line is used for receiving operation voltage signals, and operation results are stored in the output unit in a resistance mode; the invention is based on voltage-resistance logic, and uses a logic operation mode that voltage-resistance signals simultaneously participate in operation. The circuit structure has reconfigurability, reversible operation does not have energy loss caused by information loss, and only one step is needed for operation, so that accumulated errors are reduced.

Description

Voltage-resistance type reversible logic circuit based on memristor and operation method thereof

Technical Field

The invention belongs to the field of microelectronic devices, and particularly relates to a voltage-resistance reversible logic circuit based on a memristor and an operation method thereof.

Background

Reversible logic is a basic way to realize reversible computation, and has irreplaceable advantages in reducing computation power consumption because the reversible computation process does not generate the problem of energy loss caused by information loss. With the increase of data volume, the processing of mass data needs to consume a large amount of energy, and the rising of technologies such as edge calculation and the like has higher and higher requirements on the power consumption of a calculation-intensive chip, and under the background, the reversible calculation has great application value.

Meanwhile, the memristor is a novel microelectronic device and is a core device for realizing memory calculation, and the memory calculation is expected to replace a von Neumann structure to become a basic framework of a next generation computer. A resistance change switch having a memory effect has natural nonvolatile characteristics because its resistance can be stably maintained after power is turned off. In addition, the memristor has the characteristics of simple structure, compatibility with a CMOS (complementary metal oxide semiconductor) process, high resistance change speed, small size, high integration density and the like, so that the memristor has incomparable advantages in realizing logic operation.

The existing reversible logic implementation scheme is mainly based on the CMOS technology except for quantum computation, but the reversible logic implementation scheme consumes more hardware resources and is unfavorable for reducing the chip area; there have been studies in other fields such as molecular calculation, DNA calculation, etc., but these calculation media and information carriers are not compatible with current computer systems (they are not solid-state circuits), so that there are problems in stability and practicality. The memristor has the characteristic of integrating calculation, and as an operation device, the memristor has been studied more deeply in the classical boolean logic operation, for example, chinese patent CN109994139A discloses a complete non-volatile logic implementation method based on a unipolar memristor, and a single unipolar memristor is utilized to implement complete 16 boolean logic functions. However, at present, the research on realizing reversible logic by using memristors is still blank at home, and the invention provides a scheme for realizing the reversible logic gate by single-step operation in the memristor array structure based on the research so as to achieve better performance.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a method for realizing reversible operation by using a novel microelectronic device, namely a memristor, in a circuit layer, and aims to reduce the calculation power consumption and the circuit complexity and eliminate the accumulated error.

The memristor array structure is utilized, a voltage-resistance logic is based, a logic operation mode that voltage-resistance signals participate in operation at the same time is used, after initialization, operation is completed in one step by applying corresponding operation voltage to a designated bit line, and an operation result is stored in a memristor unit in a resistance mode.

The invention provides a voltage-resistance type reversible logic circuit based on a memristor, which is characterized in that the circuit adopts a cross bar structure memristor array and comprises word lines, bit lines, memristor units and grounding resistors, wherein the memristor units are used as operation units and comprise input units and output units; one end of each memristor unit is connected with a word line, the other end of each memristor unit is connected with a corresponding bit line, and the other end of each word line is connected with a grounding resistor;

the high level and the high resistance state in the circuit are defined as logic '1', and the low level and the low resistance state are defined as logic '0'; the input unit is used for writing in corresponding resistance state signals participating in reversible operation, the bit line is used for receiving operation voltage signals, and operation results are stored in the output unit in a resistance mode; level signals corresponding to reversible operation are applied to bit lines connected to the input unit, and constant voltage V is applied to bit lines connected to the output unit_DD(ii) a The circuit is based on voltage-resistance logic, and uses voltage-resistance signals to participate in operation at the same time.

The reversible operation includes a Feynman gate, a Toffoli gate, or a Fredkin gate.

Further, the Feynman gate has an input of A, B and an output of P, Q, where P ═ a,

implemented with a 1 × 3 array; the memristor unit comprises a first memristor, a second memristor and a third memristor, wherein the first memristor is used as an input unit, the second memristor is used as the input unit and an output unit at the same time, and the third memristor is used as the output unit; the values of B and A are written into the first memristor and the second memristor respectively, and A, B and V are applied to a bit line I, a bit line II and a bit line III respectively_DDAnd storing the result P in the second memristor and storing the target operation result Q in the third memristor.

Further, the toffee gate has inputs of A, B and a control bit C, and an output of P, Q, R, where P ═ a, Q ═ B,

implemented with a 1 × 5 array; memory resistance sheetThe element comprises a first memristor, a second memristor, a third memristor, a fourth memristor and a fifth memristor, wherein the first memristor and the second memristor are simultaneously used as an input unit and an output unit, the third memristor and the fourth memristor are used as the input unit, the fifth memristor is used as the output unit, values of A and B are respectively written into the first memristor and the second memristor, and C is written into the third memristor and the fourth memristor; an operation signal C, A, B is simultaneously applied to bit line one, bit line two, bit line three, and bit line four, respectively, where the C signal occupies two bit lines, bit line one and bit line two, and the V signal is applied to bit line five_DDThe result P, Q is stored in the first memristor and the second memristor, respectively, and the target bit operation result R is stored in the fifth memristor.

Further, the inputs of the Fredkin gate are control bit a and controlled bit B, C, and the output is P, Q, R, where P ═ a, Q, R outputs the target bit result, implemented with a 2 × 3 array; the memristor unit comprises a first memristor, a second memristor and a third memristor which are communicated by a first word line, and a fourth memristor, a fifth memristor and a sixth memristor which are communicated by a second word line, wherein the first memristor and the fourth memristor are positioned on a first bit line, the second memristor and the fifth memristor are positioned on a second bit line, the third memristor and the sixth memristor are positioned on a third bit line, and an operation signal B, C and a voltage V are simultaneously and respectively applied to the first bit line, the second bit line and the third bit line_DDWriting A into the first memristor and the fifth memristor, writing A into the second memristor and the fourth memristor

The third memristor and the sixth memristor output the target operation result Q, R.

Furthermore, the value of the input unit is not changed in the operation process and can be simultaneously used as the output of the control bit.

The invention also provides an operation method of the voltage-resistance type reversible logic circuit based on the memristor, which comprises the following steps:

writing operation is carried out on the memristive units, the input units are set to corresponding resistance states respectively, and the output units are initialized to high-resistance states;

applying an operation voltage to the bit line, wherein the bit line of the output unit is applied with an operation voltageAll operating voltages of (A) are constant voltages V_DDAt this time, if the divided voltage of the output unit is higher than the SET threshold voltage of the memristor, the output unit is SET to be in a low-resistance state, otherwise, the high-resistance state is kept unchanged.

Three basic reversible logic gates can be completed through the technical scheme: feynman gates, toffrani gates and Fredkin gates, wherein Feynman gates and toffrani gates only require a 1 × N array and Fredkin gates require a 2 × 3 array and are scalable to multi-bit reversible logic gates as needed. Has the following beneficial effects:

(1) the method conforms to the essential requirement of reversible calculation, and input information can be kept and not erased in the operation process, so that the problem of energy loss caused by information loss can be solved;

(2) the circuit structure has reconfigurability, and different operation functions can be completed by applying different operation signals in the same circuit structure;

(3) the operation result is stored in the memristor unit and can be directly used as the input of the next operation, so that repeated writing and reading are avoided, a reversible network with a complex cascade structure is very convenient, the integration of storage and operation is realized, and the circuit complexity is reduced;

(4) the operation process is only one step, so that accumulated errors in some operation processes are avoided to a great extent, the operation speed is improved, and the operation power consumption is reduced.

Drawings

Fig. 1 is a schematic diagram of a memristive voltage-resistance reversible logic circuit.

FIG. 2 is a flow chart of an operational method of a memristor array circuit to perform an arithmetic function.

Fig. 3(a) is a circuit symbol of a Feynman gate in the present invention, fig. 3(b) is a logic truth table of the Feynman gate, and fig. 3(c) is a schematic diagram of a Feynman gate structure and an operation signal based on a memristor array designed in the present invention.

Fig. 4(a) is a symbol of the toffsol gate circuit in the present invention, fig. 4(b) is a logic truth table of the toffsol gate, and fig. 4(c) is a schematic diagram of the structure and operation signals of the toffsol gate circuit based on the memristor array designed in the present invention.

Fig. 5(a) is a Fredkin gate symbol in the present invention, fig. 5(b) is a logic truth table of the Fredkin gate, and fig. 5(c) is a schematic diagram of the structure and operation signals of the Fredkin gate based on the memristor array designed by the present invention.

FIG. 6(a) is a symbol of a multi-bit controlled NOT gate circuit in the present invention, and FIG. 6(b) is a schematic diagram of a multi-bit controlled NOT gate circuit structure and operation signals based on a memristor array designed according to the present invention.

Detailed Description

In order that the invention may be more readily understood and appreciated, reference will now be made to the following examples.

To facilitate understanding of the contents and basic principles of the present invention, fig. 1 shows a memristive voltage-resistance reversible logic circuit, including a cross-bar structure memristor array, in which word lines, bit lines, and memristive cells M are included₁～M_nAnd a ground resistance R_XOne end of each memristor unit is connected with a word line, and the other end of each memristor unit is connected with a corresponding bit line; word line connection ground resistor R_XThe resistance value of the ground resistor is

As a voltage dividing resistor; in operation of the circuit, a level signal V from a peripheral circuit 1 is applied at the bit line₁～V_n. The invention defines that the high level and the high resistance state are logic '1', the low level and the low resistance state are logic '0', and the operating voltage applied on the bit line and the value of the operation unit are binary signals. When the memristor is initialized, the input unit writes corresponding input signals, the output units are all SET to be in a high-resistance state, and after corresponding operation voltage signals are applied to bit lines corresponding to the operation units, when the partial voltage of the output units is larger than the SET voltage of the output units, the output units are in the high-resistance state R_HAnd converting to a low resistance state RL, otherwise keeping the high resistance state unchanged, and completing the operation.

Fig. 2 illustrates an operational method for performing an arithmetic function using the above-described circuit. Firstly, writing operation is carried out, the input units are respectively set to corresponding resistance states, and the output units are initialized to high resistance states. Then, an operation voltage is applied to the bit line, wherein the bit line of the output unit is appliedThe applied operating voltages are all V_DD(operating voltage of chip or device, which is a constant value), if the voltage of output unit is divided (i.e. V)_DDAnd word line voltage V_WLThe difference) above the SET threshold voltage of the memristor, the output cell will be placed into a low resistance state, otherwise, the high resistance state is left unchanged. In the whole operation process, the value of the input unit is not changed, namely the operation voltage does not influence the value of the input unit, so the operation voltage can be simultaneously used as the output of the control bit.

Example one

In fig. 3, fig. 3(a) shows circuit symbols of the Feynman gate, and fig. 3(b) shows a truth table of the Feynman gate. This is a 2 x 2 logic gate, input signal A, B, output signal P ═ a,

the designed circuit structure is shown in FIG. 3(c) according to the operation function and logic truth table, wherein M₁，M₂，M₃As memristive cells, i.e., arithmetic cells.

The operation steps are as follows:

(1) and (5) initializing. M₁，M₂As an input unit, values of B and A are written into M, respectively₁And M₂High resistance state R_HRepresents "1", and the low resistance state RL represents "0"; m₃As an output unit, it is initialized to a high resistance state.

(2) An operating voltage is applied. A, B, V are simultaneously applied to bit line one, bit line two and bit line three, respectively_DDA and B are operation signals, high level V_HRepresents "1", low level V_LRepresents "0".

According to kirchhoff's current law:

V_irepresenting the operating voltage applied to each bit line, only V_HAnd VL, which represent logic "1" and "0", respectively, V_WLDenotes a word line voltage, when A is 0, V_A＝V_L，R_A＝R_LWhen A is 1, V_A＝V_H，R_A＝R_H. When B is 0, V_B＝V_L，R_B＝R_L(ii) a When B is 1, V_B＝V_H，R_B＝R_H. Therefore, in the circuit configuration shown in fig. 3(c), from kirchhoff's current law, it is possible to obtain:

if:

V_DD-V_WL＞V_SET (4)

then M₃Will be set to a low resistance state, otherwise the high resistance state will remain unchanged. Applying operation signal voltage to complete operation, and keeping the values of A and B in M during operation₂And M₁The target operation result Q is stored in M₃In, M₂Meanwhile, the circuit can be used as an input unit and an output unit, and the increase of the circuit complexity caused by garbage bits is reduced.

When A is 0 and B is 0, M₁And M₂Both are in the low resistance state, and the bit line voltages of both cells are also at the low voltage VL, at which time the word line voltage is set by M₁And M₂Is pulled down so that M₃Higher partial pressure, greater than V_SET，M₃Executing SET operation, setting the SET operation to be in a low impedance state, and setting the operation result to be Q to be 0; when A is 0 and B is 1, M₁Writing a value of B, so that it is in a high resistance state, M₂Writing the value of A, so that it is in the low resistance state, and applying an operating voltage V of A to the bit line_LThe bit line two applies the operating voltage V of B_HBecause M is₂Is in a low resistance state, pulls the word line high, M₃The partial pressure is lower than V_SETFail to execute SET operation, secureThe high impedance state is kept unchanged, so the operation result is Q is 1; for the same reason, when a is 1 and B is 0, the word line voltage is set by M₁Is pulled up so that M₃The partial pressure is low, the SET operation cannot be finished, and the operation result is Q1; when A is 1 and B is 1, M is₁And M₂All are in high impedance state, and both bit line one and bit line two are applied with high level, at this time R_XIs the minimum, so the word line voltage is R_xPulling down, M₃Has a higher partial pressure of greater than V_SET，M₃Is set to the low impedance state, so the operation result is Q ═ 0. In summary, the Feynman gate can be realized by the circuit structure and the operation method.

If the above four cases are described by constraint equations, it is expressed as:

since the circuit structure is symmetrical, the second and third of the four sets of equations are equivalent, so that there are only three sets of equations, specific values, for solving V using the constraint equations_H、VL、V_DDThe optimum combination of (1) is sufficient.

Example two

In fig. 4, the toffee gate has A, B inputs and a target bit C output of P, Q, R, where P ═ a, Q ═ B,

implemented with a 1 × 5 array; because the toffee gate is added with a control bit on the basis of the Feynman gate, the same design concept is adopted, as shown in fig. 4(c), and a corresponding operation unit is added in the circuit structure.

The operation steps are as follows:

(1) and (5) initializing. A, B, C are written into M respectively₁、M₂、M₃、M₄Wherein C occupies two arithmetic units M₃And M₄，M₅As an output unit, initializing to a high-resistance state;

(2) simultaneously and respectively applying operations on the first bit line, the second bit line, the third bit line and the fourth bit lineSignals C, A, B, where the C signal occupies two bit lines, bit line one and bit line two, and V is applied to bit line five_DD。

The resistance value of the input unit is not changed in the operation process, and the target bit operation result R is stored in M₅In (1). The Toffoli gate adds a bit on the basis of the Feynman gate, but two operation units are added in the circuit structure, so the voltage division situation is more complicated, and the value sum V of the operation voltage is more complicated_DDThe selection of the value of (a) needs to be more accurate, so that a constraint equation solution needs to be established according to 8 input combinations.

EXAMPLE III

Shown in fig. 5 is the design of the Fredkin gate of the present invention. The inputs to the Fredkin gate are control bit a and controlled bit B, C, and the output is P, Q, R, where P ═ a, Q, R outputs the target bit result. The Fredkin gate is also a 3 x 3 reversible logic gate, but has two target bits, so a 2 x 3 array is required. As shown in FIG. 5(c), the word line-connected operation unit M₁、M₂、M₃Calculated is Q, word line two connected arithmetic unit M₄、M₅、M₆It is calculated that the R, Fredkin gate functions as two data selectors, so a functions as one valve.

The operation steps are as follows:

(1) and (5) initializing. M₁And M₅Writing A, M₂And M₄Writing in

M₃And M₆As an output unit, initializing to a high-resistance state;

(2) simultaneously applying an operating voltage B, C, V to bit line one, bit line two, and bit line three, respectively_DDWhen the operation is completed, the target bit operation results Q and R are stored in M, respectively₃And M₆In, M₁The value of (b) is kept constant during the operation, so that the value of (b) can be used as the output P of the control bit at the same time.

Example four

To illustrate the excellent expandability of the circuit structure and operation method provided by the inventionExamples of multi-bit reversible logic gates are further described herein. Fig. 6 shows a 4 × 4 multi-bit controlled not gate, and the logic operation of the circuit is as follows:

fig. 6(a) is a circuit symbol thereof, fig. 6(b) is a circuit diagram, and a truth table can be derived from a logical expression. The circuit structure comprises 7 memristive devices and a voltage dividing resistor, A, B, C, D is used as an input variable, the output is O, P, Q, R, wherein A, B, C is a control bit, D is a target bit, O is A, P is B, Q is C, and R is the target bit of the output. Assuming that an input 1101, i.e., a is 1, B is 1, C is 0, and D is 1, for convenience of explanation, 7 devices are numbered M sequentially here₁、M₂、M₃、M₄、M₅、M₆、M₇The resistance states are respectively: m₁＝R_H，M₂＝R_H，M₃＝R_H，M₄＝R_H，M₅＝R_H，M₆＝R_L，M₇＝R_HThe corresponding voltages are: v_H，V_H，V_L，V_H，V_H，V_H，V_DD，M₁～M₅All in high impedance state, blocking the voltage signal on the bit line, M₆The word line voltage is pulled high by turning on the voltage signal D, which is high level when D is 1, so that M is in low resistance state₇The resistance state can not be set to be a low resistance state, the high resistance state is maintained unchanged, and 1 is output; assume the input is 1110, at which time M₁～M₆The resistance states of (A) are respectively: m₁＝R_L，M₂＝R_L，M₃＝R_L，M₄＝R_H，M₅＝R_H，M₆＝R_H，M₁～M₃All are in low resistance state, and the conducting of the corresponding bit line signals is: a, B and C. At this time, ABC is all '1', so that the voltage level is high, M₄～M₆Is in high impedance state, and blocks the voltage signal of corresponding bit line, so that the word line voltage is pulled high by the three high levels, M₇Will not be set to low resistance state, and maintain high resistance stateInstead, a "1" is output.

Claims

1. A voltage-resistance reversible logic circuit based on a memristor is characterized in that the circuit adopts a cross bar structure memristor array and comprises word lines, bit lines, memristor units and grounding resistors, wherein the memristor units are used as operation units, and comprise input units and output units; one end of each memristor unit is connected with a word line, the other end of each memristor unit is connected with a corresponding bit line, and the other end of each word line is connected with a grounding resistor;

the high level and the high resistance state in the circuit are defined as logic '1', and the low level and the low resistance state are defined as logic '0'; the input unit is used for writing in corresponding resistance state signals participating in reversible operation, the bit line is used for receiving operation voltage signals, and operation results are stored in the output unit in a resistance mode; during operation, level signals corresponding to reversible operation are applied to bit lines connected with the input unit, and constant voltage V is applied to bit lines connected with the output unit_DD(ii) a The circuit is based on voltage-resistance logic, and uses voltage and resistance signals to participate in operation simultaneously.

2. The voltage-resistive reversible logic circuit of claim 1, wherein: the reversible operation includes a Feynman gate, a Toffoli gate, or a Fredkin gate.

3. The voltage-resistive reversible logic circuit of claim 2, wherein: the Feynman gate has an input of A, B and an output of P, Q, where P ═ a,

implemented with a 1 × 3 array; the memristive cell includes a first memristor (M)₁) Second memristor (M)₂) The third memristor (M)₃) Wherein the first memristor (M)₁) As an input cell, a second memristor (M)₂) Third memristor (M) as both input and output cells₃) As an output unit; first memristor (M)₁) And a second memristor (M)₂) In which B is written respectivelyAnd A, A, B and V being applied to bit line one, bit line two, and bit line three, respectively_DDThe result P is stored in the second memristor (M)₂) The target operation result Q is stored in the third memristor (M)₃)。

4. The voltage-resistive reversible logic circuit of claim 2, wherein: the toffee gate has A, B inputs and a control bit C, and P, Q, R outputs, where P ═ a, Q ═ B,

implemented with a 1 × 5 array; the memristive cell includes a first memristor (M)₁) Second memristor (M)₂) The third memristor (M)₃) Fourth memristor (M)₄) The fifth memristor (M)₅) Wherein the first memristor (M)₁) Second memristor (M)₂) Third memristor (M) as both input and output cells₃) Fourth memristor (M)₄) As an input cell, a fifth memristor (M)₅) As an output unit, a first memristor (M)₁) And a second memristor (M)₂) In which the values of A and B, respectively, the third memristor (M)₃) And a fourth memristor (M)₄) C is written in; an operation signal C, A, B is simultaneously applied to bit line one, bit line two, bit line three, and bit line four, respectively, where the C signal occupies two bit lines, bit line one and bit line two, and the V signal is applied to bit line five_DDThe result P, Q is stored in the first memristor (M)₁) Second memristor (M)₂) The target bit operation result R is stored in the fifth memristor (M)₅)。

5. The voltage-resistive reversible logic circuit of claim 2, wherein: the inputs of the Fredkin gate are control bit a and controlled bit B, C, the output is P, Q, R, where P is a, Q, R outputs the target bit result, implemented with a 2 × 3 array; the memristive cell comprises a first memristor (M) communicated by a word line one₁) Second memristor (M)₂) The third memristor (M)₃) And a fourth memristor (M) connected by word line two₄) The fifth memristor (M)₅) Sixth memristor (M)₆) WhereinFirst memristor (M)₁) Fourth memristor (M)₄) On bit line one, second memristor (M)₂) The fifth memristor (M)₅) On bit line two, third memristor (M)₃) Sixth memristor (M)₆) On bit line three, an operation signal B, C and a voltage V are simultaneously applied to bit line one, bit line two and bit line three, respectively_DDFirst memristor (M)₁) The fifth memristor (M)₅) Write A, second memristor (M)₂) Fourth memristor (M)₄) Writing in

Third memristor (M)₃) And sixth memristor (M)₆) The target operation result Q, R is output.

6. The voltage-resistive reversible logic circuit according to any of claims 3-5, wherein: and in the operation process, the value of the input unit is unchanged and is used as the output of the control bit.

7. A method of operating a memristor-based voltage-resistance reversible logic circuit, according to claim 1, comprising the steps of:

applying operation voltages to the bit lines, wherein the operation voltages applied to the bit lines of the output unit are all constant voltages V_DDAt this time, if the divided voltage of the output unit is higher than the SET threshold voltage of the memristor, the output unit is SET to be in a low-resistance state, otherwise, the high-resistance state is kept unchanged.

8. The method of claim 7 wherein the Feynman gate has an input of A, B and an output of P, Q, wherein P ═ A,

applying on the bit line of the memristor corresponding to the A unitAdding B signal voltage, applying A signal voltage on the bit line of the memristor corresponding to the B unit, and applying V signal voltage on the bit line of the memristor corresponding to the output unit_DD。

9. The method of claim 7, wherein the Toffoli gate has inputs of A, B and a target bit of C, and an output of P, Q, R, wherein P ═ A, Q ═ B,

the voltage signal of the target bit C is applied to the bit lines of the control bits A and B cells, two memristive cells are used as C, the voltage signals of A and B are respectively applied to the C, and V is applied to the bit line of the output cell R_DD。

10. The method of claim 7, wherein Fredkin gates have inputs of control bit a and controlled bit B, C and an output of P, Q, R, wherein P ═ a, Q, R outputs the target bit result; the first row word line in a 2 x 3 array writes a sequentially,

at the same time, the Q of the output unit is set to high resistance state, and the second row of word lines are written in sequence

A, simultaneously, the output unit R is set to high impedance state, B, C signal voltage and V are applied to the first bit line, the second bit line and the third bit line respectively_DD。