CN110797076B - NAND Flash time sequence testing method - Google Patents
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Abstract
The invention discloses a NAND Flash time sequence testing method, which comprises the following steps: acquiring all storage data in the NAND Flash; reading the NAND Flash, moving the sampling pulse position, and acquiring read data to obtain a plurality of acquired data; comparing the stored data with the acquired data, and storing the comparison result of each byte in the Page into an error capturing memory; dividing an error capture memory into a plurality of regions, and acquiring a data valid window time t corresponding to each regionDVWAnd data valid region time tstrobe(ii) a According to the respective corresponding t of each regionDVWAnd tstrobeAnd judging whether the NAND Flash has a fault. The time sequence testing method tests the time sequence parameters in a partition mode, so that the measured parameters are more accurate, the application of the multi-clock setting memory enables the ATE to overcome the interference generated by the time sequence offset of the chip in the DDR3 mode and correctly collect the output data of the chip, a reliable testing environment is provided for the subsequent functional testing, the hardware of the ATE is not required to be improved, and the testing cost is saved.
Description
Technical Field
The invention relates to the technical field of memory chip testing, in particular to a NAND Flash time sequence testing method.
Background
At present, because the chip integration level is higher, the test of the NAND Flash chip is usually executed by Automatic Test Equipment (ATE); in the test process, whether the chip has faults is judged by comparing whether the data input and output by the chip are the same.
Most of the interfaces of the existing NAND Flash chips are in a DDR3 mode, the data transmission rate is 800MT/S in the DDR3 mode, and the data transmission period is 2.5 ns; as the data transmission rate increases, parasitic capacitance interference caused by defects caused by the ATE process is amplified; in particular, when the chip operating frequency is high, the charge stored by the parasitic capacitance will interfere with the circuit characteristics. Because the pulse interval is too short, the parasitic capacitance is not in time to discharge, and the reference voltage which should be constant is continuously increased; the related time sequence parameters measured in the test process are inaccurate, and finally, the subsequent test cannot be carried out; the time sequence test of the NAND Flash in the DDR3 mode can not be normally carried out.
Disclosure of Invention
In order to solve the technical problem that the conventional automatic test equipment cannot normally perform time sequence test on the NAND Flash under the DDR3 mode, the invention provides a NAND Flash time sequence test method.
The NAND Flash time sequence testing method comprises the following steps:
acquiring all storage data in each Page of the NAND Flash;
reading each Page of the NAND Flash to obtain a plurality of read data, moving the position of the sampling pulse, and acquiring the read data to obtain a plurality of acquired data;
comparing the stored data with the acquired data, and storing the comparison result of each byte in the Page into an error capturing memory;
dividing all comparison results stored in an error capture memory into a plurality of regions, and acquiring the effective window time t of data corresponding to each regionDVWAnd data valid region time tstrobe；
According to the effective window time t of the data corresponding to each regionDVWAnd data valid region time tstrobeAnd judging whether the NAND Flash has a fault.
Preferably, the step of dividing all comparison results stored in the error trapping memory into a plurality of regions comprises:
storing the comparison result in a corresponding position in an error capturing memory according to a corresponding row address and a corresponding column address, wherein the row address represents the shifting times of the sampling pulse, and the column address represents the byte address;
the error trapping memory is divided into N regions by column addresses.
Preferably, the data valid window time t corresponding to each region is obtainedDVWComprises the following steps:
scanning the comparison result in each area in the error capturing memory according to rows, and recording the number a of the comparison result in each area as 0;
obtaining the test time T corresponding to each comparison result being 0;
according to the ratio of each regionComparing the result to 0, corresponding to the test time T and the number a, and calculating the effective window time T of the data corresponding to each areaDVWThe calculation formula is as follows:
tDVW＝aT；
wherein, tDVWThe unit of (A) is: ns, T is in units of: ns.
Preferably, the data valid region time t corresponding to each region is acquiredstrobeComprises the following steps:
scanning the comparison result in each area in the error capturing memory according to rows, and sequentially judging whether the comparison result stored in each row of each area is 0;
if all the comparison results stored in one row in the area are 0 for the first time, the scanning time corresponding to the row is the data valid area time t corresponding to the areastrobe。
Preferably, the step of judging whether the NAND Flash fails includes:
calculating the time t of the effective data area corresponding to the first areastrobeData valid region time t corresponding to the second regionstrobeObtaining the absolute value of the difference to obtain a calculation result; judging the relation between the calculation result and the difference value requirement;
if the calculation result is larger than the difference requirement, the time t of the effective data area corresponding to the first area is determinedstrobeWriting the data into a clock setting memory, and adding 1 to the number of the clock setting memory; if the calculation result is less than or equal to the difference requirement, continuing to calculate, and keeping the number of the used clock setting memories unchanged; the initial value of the number of the used clock setting memories is 1;
sequentially calculate the YthnRegion and the Ythn+2Calculating the result of the region; judging the relation between the calculation result and the difference value requirement; wherein N is 1, 2, 3 … … (N-2);
if the calculated result is greater than the difference requirement, the Y-th value is setnData valid region time t corresponding to regionstrobeWriting into the clock setting memory, adding 1 to the number of the clock setting memory, and judging the clock setting memoryThe number of the used faults and the number of the faults required; if the calculation result is less than or equal to the difference requirement, continuing the previous operation until the end;
if the number of the used clock setting memories is larger than the requirement of the number of faults, judging that the NAND Flash has the faults; and if the current value is less than or equal to the preset value, judging that the NAND Flash does not have a fault.
Preferably, the sampling frequency of the sampling pulse is 400MHz, and the duty cycle of the sampling pulse is: 0.5.
preferably, the position of the sampling pulse is shifted by a time interval of 0.01 ns.
Preferably, the difference value is required to be in a range of: greater than 0ns and less than or equal to 0.17 ns.
Preferably, the required value range of the number of faults is as follows: 1 to 16.
Preferably, the value range of the number N of the regions in the error trapping memory is: 1 to 64.
In summary, compared with the existing testing method, the NAND Flash timing sequence testing method of the present invention expands the comparison result of only recording the input and output of the whole Page into the comparison result of recording the input and output of all bytes in the whole Page, and correspondingly stores the comparison result of each byte in the error capturing memory divided into a plurality of areas, and obtains the corresponding data valid window time t by testing each areaDVWAnd data valid region time tstrobeAnd according to the effective window time t of the data corresponding to each regionDVWAnd data valid region time tstrobeWhether the NAND Flash fails or not can be judged, and the problem that the test cannot be carried out due to the parasitic capacitance interference phenomenon of the test equipment is avoided; meanwhile, the application of the multi-clock setting memory enables the ATE to overcome the interference generated by the time sequence offset of the chip in the DDR3 mode and correctly collect the output data of the chip, provides a reliable test environment for subsequent functional tests, does not need to transform equipment hardware, can still perform time sequence test on the NAND Flash in the DDR3 mode, overcomes the frequency limitation of test equipment and reduces the test cost.
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FIG. 1 is a flow chart of a NAND Flash timing sequence test method related to the invention;
FIG. 2 is a diagram showing the effective time t of each byte when a signal is output by the conventional timing test methodACAnd an invalid time tInvalidA distribution diagram;
FIG. 3 is a logical address of data stored in an error trapping memory of NAND Flash of 32 GB;
FIG. 4 is a diagram showing that the effective time t of each byte is used for testing the NAND Flash in DDR3 mode by adopting the traditional time sequence testing methodACAnd an invalid time tInvalidA statistical chart;
FIG. 5 is a diagram showing a data valid window time t of each region when a signal is outputted by the timing test method according to the present inventionDVWAnd data valid region time tstrobeA distribution diagram;
FIG. 6 is a graph showing a data valid window time t of each region measured by a conventional time series test method and a time series test method according to the present inventionDVWThe results are compared with the figures.
Detailed Description
The following describes an embodiment according to the present invention with reference to the drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
At present, because the chip integration level is higher, the test of the NAND Flash chip is usually executed by Automatic Test Equipment (ATE); in the test process, whether the chip has faults is judged by comparing whether the data input and output by the chip are the same.
The DDR3 mode has more data select pulses (DQS) than the SDR mode. The DQS signal is generated in the chip after the read operation is enabled, and is used for accurately distinguishing each transmission cycle in one clock cycle, so that signals between the memory and the memory controller are synchronized, and a receiving party can accurately receive data; therefore, the interface of the existing NAND Flash chip is mostly in a DDR3 mode; but at a data transfer rate of DDR3 mode800MT/S, the data transmission period is 2.5 ns; as the data transmission rate increases, parasitic capacitance interference caused by defects caused by the ATE process is amplified; in particular, when the chip operating frequency is high, the charge stored by the parasitic capacitance will interfere with the circuit characteristics. Because the pulse interval is too short, the parasitic capacitance is not in time to discharge, and the reference voltage which should be constant is continuously increased; as shown in fig. 2, the effective time t in the test process is enabledAC(lower curve) and dead time tInvalid(upper curve) is gradually reduced, so that the measured relevant time sequence parameters in the test process are inaccurate, and finally, the subsequent test cannot be carried out; the time sequence test of the NAND Flash in the DDR3 mode can not be normally carried out.
In order to solve the technical problem that the conventional automatic test equipment cannot normally perform time sequence test on the NAND Flash in the DDR3 mode, the invention provides a NAND Flash time sequence test method, which comprises the steps of recording comparison results of all bytes in the whole Page when input data and output data are compared, correspondingly storing the comparison results into an error capturing memory divided into a plurality of areas, and respectively testing each area in the error capturing memory to obtain time sequence parameters corresponding to each area and conforming to the actual condition, and meanwhile, setting the application of the memory by a plurality of clocks to ensure that ATE can normally perform time sequence test on the NAND Flash in the DDR3 mode and overcome the frequency limitation of the test equipment.
Specifically, as shown in fig. 1, the NAND Flash timing sequence testing method of the present invention includes the steps of:
s1, acquiring all storage data in each Page of the NAND Flash;
in the step, the NAND Flash comprises a plurality of blocks (blocks), each Block comprises a plurality of pages, when the time sequence test is carried out on the NAND Flash, ATE is required to write data stored in a DBM (data buffer memory) into a memory in a form of a test vector by a Pattern System, a read command is sent to output the data after the data is written, and meanwhile, the clock setting memory sends an instruction to enable a signal generator to generate a sampling pulse to collect the output data; and acquiring all stored data in the NAND Flash to prepare for comparison of subsequent input data and output data.
S2, reading each Page of the NAND Flash to obtain a plurality of read data, moving the position of the sampling pulse, and sampling the read data to obtain a plurality of collected data; preferably, the sampling frequency of the sampling pulse is 400MHz, and the duty ratio of the sampling pulse is: 0.5; and the sampling pulse position is shifted by the time interval 0.01 ns.
In the step, a plurality of clock setting memories generate sampling pulses of corresponding areas, the sampling pulses are triggered by adopting rising edges, and all read data can be accurately collected every time.
S3, comparing the stored data with the collected data, and storing the comparison result of each byte in the Page into an Error Catch memory (ECR, Error Catch RAM);
in the step, the stored data is compared with the acquired data, and if the stored data is the same as the acquired data, the comparison result is 0; if not, the comparison result is 1.
S4, dividing all comparison results stored in the error capture memory into a plurality of areas, and acquiring the effective window time t of data corresponding to each areaDVWAnd data valid region time tstrobe；
Specifically, the step of dividing all comparison results stored in the error capturing memory into a plurality of areas includes:
s41, storing the comparison result in the corresponding position in the error capturing memory according to the corresponding row address and the column address, wherein the row address represents the shifting times of the sampling pulse, and the column address represents the byte address;
s42, dividing the error capturing memory into N areas according to a plurality of column addresses. Preferably, the value range of the number N of the regions in the error trapping memory is: 1 to 64.
In this step, the error trapping memory is divided into N regions according to a plurality of column addresses, that is, according to the difference of byte addresses, and in the subsequent acquisition of timing parameters, each small region is tested instead,the method means that each test only tests the comparison result of partial byte data in one Page, so that the phenomenon of parasitic capacitance interference caused by too short pulse interval and too late discharge of parasitic capacitance is avoided; therefore, the valid window time t of the data corresponding to each region can be accurately testedDVWAnd data valid region time tstrobe。
Further, obtaining the effective window time t of data corresponding to each regionDVWComprises the following steps:
s431, scanning the comparison result in each area in the error capturing memory according to the rows, and recording the number a of the comparison result in each area as 0;
s432, obtaining the test time T corresponding to each comparison result being 0;
s433, calculating the effective window time T of the data corresponding to each region according to the test time T and the number a corresponding to the comparison result of 0 in each regionDVWThe calculation formula is as follows:
tDVW＝aT；
wherein, tDVWThe unit of (A) is: ns, T is in units of: ns.
Further, the data valid region time t corresponding to each region is obtainedstrobeComprises the following steps:
s441, scanning the comparison result in each area in the error capturing memory according to rows, and sequentially judging whether the comparison result stored in each row of each area is 0;
s442, if all the first comparison results stored in a row in the area are 0, the scanning time corresponding to the row is the data valid area time t corresponding to the areastrobe。
S5, according to the data valid window time t corresponding to each regionDVWAnd data valid region time tstrobeAnd judging whether the NAND Flash has a fault.
Specifically, the step of judging whether the NAND Flash fails includes:
s51, calculating the effective data area time t corresponding to the first areastrobeData valid region time t corresponding to the second regionstrobeObtaining the absolute value of the difference to obtain a calculation result; judging the relation between the calculation result and the difference value requirement; wherein, preferably, the range of values required by the difference is: greater than 0ns and less than or equal to 0.17 ns.
S52, if the calculation result is larger than the difference requirement, the effective area time t of the data corresponding to the first area is determinedstrobeWriting the data into a clock setting memory (TSET RAM), and adding 1 to the number of the clock setting memory; if the calculation result is less than or equal to the difference requirement, continuing to calculate, and keeping the number of the used clock setting memories unchanged; the initial value of the number of the used clock setting memories is 1;
in this step, the data valid region time t corresponding to the region is determinedstrobeThe write clock is arranged in the memory, and can generate sampling pulses for accurately reading the area; if the calculation result is larger than the difference requirement, the second area and the first area do not meet the Magnum-V sampling difference requirement, and the data valid area time t corresponding to the first area needs to be setstrobeThe interference generated by the time sequence offset of the chip in the DDR3 mode can be overcome only by writing the data into the clock setting memory, and the read data of the NAND Flash can be correctly acquired.
S53, sequentially calculating the YnRegion and the Ythn+2Calculating the result of the region; judging the relation between the calculation result and the difference value requirement; wherein N is 1, 2, 3 … … (N-2), and N is the number of divided regions in the error trapping memory;
s54, if the calculated result is larger than the difference requirement, the Y-th step is carried outnData valid region time t corresponding to regionstrobeWriting the data into a clock setting memory, adding 1 to the number of the clock setting memory, and judging the relation between the number of the clock setting memory and the number of faults; if the calculation result is less than or equal to the difference requirement, continuing the previous operation until the end;
s55, if the number of the used clock setting memories is larger than the requirement of the number of faults, judging that the NAND Flash has the faults; and if the current value is less than or equal to the preset value, judging that the NAND Flash does not have a fault. Preferably, the required value range of the number of faults is as follows: 1 to 16.
In this step, if Y isnRegion and the Ythn+2The calculation result of the region is greater than the difference requirement, and the Yth image is acquired accuratelynThe time sequence parameter corresponding to the region needs to be the YthnData valid region time t corresponding to regionstrobeWriting into the clock setting memory, i.e. adding 1 to the number of the clock setting memory, if less than, indicating the YthnRegion and the Ythn+2The areas can share one clock setting memory, so that a proper number of clock setting memories can be selected independently according to the time sequence characteristics of the chip, and on one hand, the sampling pulses of the corresponding areas are generated by the plurality of clock setting memories, so that the using number of the clock setting memories can be reduced while the correct test is ensured; on the other hand, whether the NAND Flash has faults or not can be judged according to the number of the used clock setting memories after the clock setting memories are reduced, and specifically, if the total number of the used clock setting memories is larger than the requirement of the number of the faults after all the areas are judged, the NAND Flash faults are indicated; if the voltage is less than the preset value, the NAND Flash does not have a fault.
The following provides an embodiment for comparing the time sequence test of the NAND Flash with the storage capacity of 32GB by adopting a traditional time sequence test method and the NAND Flash time sequence test method related to the invention:
as shown in FIG. 4, the effective time t of 18432 bytes of a single tested NAND Flash in DDR3 modeACAnd an invalid time tInvalidStatistical plots (discrete points in the plot are caused by variations in the characteristics of individual memory cells within the chip), the upper curve representing the dead time tInvalidThe lower curve represents the effective time tACThe statistical result of (2); it can be seen that the effective time tACAnd an invalid time tInvalidGradually reducing along with the increase of the number of output bytes, sampling the traditional time sequence test method, and calculating to obtain t of the whole Page dataDVWThe value is then approximately 0; but in practice t is per byte in this PageDVWThe value is about 0.9ns, and the time sequence parameter measured by the traditional time sequence test method is notAnd the accuracy is high, so that the subsequent test cannot be normally carried out.
In the NAND Flash timing sequence testing method according to the present invention, as shown in fig. 3, the column address in the error capture memory represents the byte address, and the row address represents the shift frequency of the sampling pulse; dividing the error capturing memory into 64 areas according to the column address; during testing, a method of setting a clock setting memory by regions is adopted, namely, a clock setting memory is set for each region to generate sampling pulses capable of accurately reading the region, the sampling pulse position is moved, and read data are collected; and storing the comparison result of the stored data and the acquired data of each byte in the Page in a corresponding position in the error capturing memory according to a corresponding row address and a corresponding column address.
Obtaining 64 data valid window time t according to line scanning test for each areaDVWAnd data valid region time tstrobeThe test results are shown in FIG. 5, where the snowflake signature represents the data valid window time tDVWThe dot mark represents the effective area time t of the datastrobe(ii) a Select 64 tDVWThe minimum value of 0.85ns is used as the measured value of the chip data output effective window, and the accurate time sequence parameter can be obtained by the NAND Flash time sequence testing method.
By the method of the above steps S51 to S55, the time t is valid for 64 data valid regions in FIG. 5strobeThe process was performed and the setting result of the clock setting memory is shown in table 1.
TABLE 1 clock setting memory setup results
As can be seen from table 1, 5 clock setting memories are obtained according to the time sequence characteristics of the NAND Flash, that is, the 5 clock setting memories are used in the test process, so that the requirement of reducing the number of the clock setting memories is met, that is, the tested NAND Flash does not have a fault.
To further verify the reliability of the methodRespectively adopting a traditional time sequence testing method and the time sequence testing method related by the invention to test 256 NAND Flash chips without time sequence faults at room temperature; the test results are shown in FIG. 6, in which the snowflake marks (upper curves) represent t measured by the time sequence test method according to the present inventionDVWThe cross mark (lower curve) represents t measured by the conventional time sequence test methodDVWThe origin mark represents the number of counts of the clock setting memory, and it can be seen that t is measured by the conventional time sequence testing methodDVWThe value of (A) is distributed between 0.2 and 0.4ns, and the actual tDVWThe value difference is large, so that subsequent testing is inaccurate or cannot be carried out, and the finally output testing result is a time sequence fault; t measured by the time sequence testing method of the inventionDVWTest results of (1) are between 0.8 and 0.9ns, closer to the actual t of each byteDVW. Meanwhile, under the time sequence testing method, the using number of the clock setting memories of 256 chips is less than 16 of the fault number requirement, namely the requirement of reducing the using number of the clock setting memories is met, the testing result is that 256 NAND flashes have no fault, and the obtained time sequence testing result is consistent with the actual situation.
In summary, compared with the existing testing method, the NAND Flash timing sequence testing method of the present invention expands the comparison result of only recording the input and output of the whole Page into the comparison result of recording the input and output of all bytes in the whole Page, and correspondingly stores the comparison result of each byte in the error capturing memory divided into a plurality of areas, and obtains the corresponding data valid window time t by testing each areaDVWAnd data valid region time tstrobeAnd according to the effective window time t of the data corresponding to each regionDVWAnd data valid region time tstrobeWhether the NAND Flash fails or not can be judged, and the problem that the test cannot be carried out due to the parasitic capacitance interference phenomenon of the test equipment is avoided; meanwhile, the application of the multi-clock setting memory enables the ATE to overcome the interference generated by the time sequence offset of the chip in the DDR3 mode and correctly collect the output data of the chip, and provides the follow-up functional test withThe method is used for a reliable test environment, the NAND Flash under the DDR3 mode can still be subjected to time sequence test without modifying equipment hardware, the frequency limit of test equipment is overcome, and the test cost is reduced.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A NAND Flash time sequence testing method is characterized by comprising the following steps:
acquiring all storage data in each Page of the NAND Flash;
reading each Page of the NAND Flash to obtain a plurality of read data; moving the position of the sampling pulse, and acquiring the read data to obtain a plurality of acquired data;
comparing the stored data with the acquired data, and storing the comparison result of each byte in the Page into an error capturing memory;
dividing all the comparison results stored in the error capturing memory into a plurality of areas, and acquiring the effective window time t of data corresponding to each areaDVWAnd data valid region time tstrobe；
According to the effective window time t of the data corresponding to each regionDVWAnd data valid region time tstrobeAnd judging whether the NAND Flash fails or not.
2. The NAND Flash timing sequence test method of claim 1, wherein the step of dividing all the comparison results stored in the error trapping memory into the plurality of areas comprises:
storing the comparison result in corresponding positions in the error capturing memory according to corresponding row addresses and column addresses, wherein the row addresses represent the shifting times of the sampling pulses, and the column addresses represent byte addresses;
dividing the error trapping memory into N regions according to a plurality of the column addresses; the value range of the number N of the areas in the error capturing memory is as follows: 1 to 64.
3. The NAND Flash timing sequence test method of claim 2, wherein the data valid window time t corresponding to each region is obtainedDVWComprises the following steps:
scanning the comparison result in each area in the error capturing memory according to rows, and recording the number a of the comparison result in each area being 0;
obtaining the test time T corresponding to each comparison result being 0;
calculating the data valid window time T corresponding to each region according to the test time T and the number a corresponding to the comparison result of 0 in each regionDVWThe calculation formula is as follows:
tDVW＝aT；
wherein, tDVWThe unit of (A) is: ns, T is in units of: ns.
4. The NAND Flash timing sequence test method of claim 2, wherein the data valid area time t corresponding to each area is obtainedstrobeComprises the following steps:
scanning the comparison results in each region in the error capturing memory according to rows, and sequentially judging whether the comparison results stored in each row of each region are all 0;
if all the comparison results stored in one row in the area are 0 for the first time, the scanning time corresponding to the row is the data effective area time t corresponding to the areastrobe。
5. The NAND Flash timing sequence test method according to claim 2, wherein the step of judging whether the NAND Flash fails includes:
calculating the time t of the effective data area corresponding to the first areastrobeThe data valid region time t corresponding to the second regionstrobeObtaining the absolute value of the difference to obtain a calculation result; judging the relation between the calculation result and the difference value requirement;
if the calculation result is larger than the difference requirement, the data effective area time t corresponding to the first area is determinedstrobeWriting the data into a clock setting memory, and adding 1 to the number of the clock setting memory; if the calculation result is less than or equal to the difference requirement, continuing to calculate, and keeping the number of the used clock setting memories unchanged; the initial value of the number of the clock setting memories is 1;
sequentially calculate the YthnRegion and the Ythn+2The calculation result of the region; judging the relation between the calculation result and the difference value requirement; wherein N is 1, 2, 3 … … (N-2), and N > 0;
if the calculation result is greater than the difference requirement, the Y-th value is setnThe data valid region time t corresponding to the regionstrobeWriting the data into the clock setting memory, adding 1 to the number of the clock setting memory, and judging the relation between the number of the clock setting memory and the fault number requirement; if the calculation result is less than or equal to the difference requirement, continuing the previous operation until the end;
if the number of the used clock setting memories is larger than the requirement of the number of the faults, judging that the NAND Flash has the faults; and if the number of the NAND Flash is less than or equal to the preset value, judging that the NAND Flash does not have a fault.
6. The NAND Flash timing sequence test method of claim 1, wherein the sampling frequency of the sampling pulse is 400MHz, and the duty cycle of the sampling pulse is: 0.5.
7. the NAND Flash timing test method of claim 1, wherein the position of the sampling pulse is shifted by a time interval of 0.01 ns.
8. The NAND Flash timing sequence test method of claim 5, wherein the difference value requires a value range of: greater than 0ns and less than or equal to 0.17 ns.
9. The NAND Flash timing sequence test method of claim 5, wherein the required value range of the number of faults is: 1 to 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910983809.3A CN110797076B (en) | 2019-10-16 | 2019-10-16 | NAND Flash time sequence testing method |
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| CN115145775A (en) * | 2022-07-20 | 2022-10-04 | 长鑫存储技术有限公司 | Time sequence testing method and device, computer equipment and storage medium |
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