CN110718613A - Light emitting diode chip and manufacturing method thereof - Google Patents
Light emitting diode chip and manufacturing method thereof Download PDFInfo
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- CN110718613A CN110718613A CN201910802514.1A CN201910802514A CN110718613A CN 110718613 A CN110718613 A CN 110718613A CN 201910802514 A CN201910802514 A CN 201910802514A CN 110718613 A CN110718613 A CN 110718613A
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- 238000003892 spreading Methods 0.000 claims description 12
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
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Abstract
The invention discloses a light-emitting diode chip and a manufacturing method thereof, and belongs to the technical field of semiconductors. The light-emitting diode chip comprises a silicon substrate, a bonding layer, a metal reflecting layer, a transparent conducting layer, a filling layer, a current blocking layer, a window layer, a P-type limiting layer, an active layer, an N-type limiting layer and an electrode; the silicon substrate, the bonding layer, the metal reflecting layer, the transparent conducting layer, the filling layer, the window layer, the P-type limiting layer, the active layer, the N-type limiting layer and the electrode are sequentially stacked, a plurality of through holes extending from the transparent conducting layer to the window layer are formed in the filling layer, and the current blocking layer is arranged in the through holes; the current blocking layer is made of magnesium difluoride, and the filling layer and the transparent conducting layer are made of one of indium tin oxide, tungsten oxide and tungsten-doped indium tin oxide. The invention can improve the front light-emitting efficiency of the red LED chip.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a manufacturing method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light.
The chip is a core component of the LED and comprises an epitaxial wafer and an N-type electrode and a P-type electrode which are respectively arranged on the epitaxial wafer. For a red LED chip, the epitaxial wafer comprises a GaAs substrate, and an N-type limiting layer, an active layer, a P-type limiting layer and a window layer which are sequentially grown on the GaAs substrate. The GaAs substrate absorbs light, and in order to avoid the light emitted by the active layer from being absorbed by the GaAs substrate, the silicon substrate can be bonded to the window layer to be used as a P-type electrode, then the GaAs substrate is removed from the N-type limiting layer, and an N-type electrode is arranged.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
light rays emitted by the active layer can be emitted to all directions, and only part of the light rays are emitted from the N-type limiting layer, so that the front light emitting efficiency of the red light LED chip is low.
Disclosure of Invention
The embodiment of the invention provides a light-emitting diode chip and a manufacturing method thereof, which can effectively improve the light-emitting efficiency of the front side of the light-emitting diode chip. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a light emitting diode chip, where the light emitting diode chip includes a silicon substrate, a bonding layer, a metal reflective layer, a transparent conductive layer, a filling layer, a current blocking layer, a window layer, a P-type confinement layer, an active layer, an N-type confinement layer, and an electrode; the silicon substrate, the bonding layer, the metal reflecting layer, the transparent conducting layer, the filling layer, the window layer, the P-type limiting layer, the active layer, the N-type limiting layer and the electrode are sequentially stacked, a plurality of through holes extending from the transparent conducting layer to the window layer are formed in the filling layer, and the current blocking layer is arranged in the through holes; the current blocking layer is made of magnesium difluoride, and the filling layer and the transparent conducting layer are made of one of indium tin oxide, tungsten oxide and tungsten-doped indium tin oxide.
Optionally, the thickness of the current blocking layer and the filling layer is 100nm to 140nm, and the thickness of the transparent conductive layer is 100nm to 300 nm.
Furthermore, the aperture of each through hole is 6-10 microns, and the distance between every two adjacent through holes is 10-20 microns.
Optionally, the material of the metal reflective layer is silver.
Further, the light emitting diode chip further comprises a titanium-tungsten alloy layer, and the titanium-tungsten alloy layer is arranged between the metal reflecting layer and the bonding layer.
Further, the content of the titanium component in the titanium-tungsten alloy layer is 10%.
Optionally, the light emitting diode chip further includes a current spreading layer, a transition layer, and a light emitting layer, where the current spreading layer, the transition layer, and the light emitting layer are sequentially stacked on the N-type confinement layer, and the electrode is disposed on a partial region of the light emitting layer; the current expansion layer, the transition layer and the light emitting layer are made of N-type doped aluminum gallium indium phosphide, the content of an aluminum component in the current expansion layer is less than that in the transition layer, and the content of the aluminum component in the transition layer is less than that in the light emitting layer.
Further, the content of the aluminum component in the current expansion layer is 20% -40%, the content of the aluminum component in the transition layer is 35% -60%, and the content of the aluminum component in the light emergent layer is 55% -70%.
Further, the projection of the electrode on the light emergent layer is circular; the light emitting diode chip also comprises an ohmic contact layer, the material of the ohmic contact layer is N-type doped gallium arsenide, and the ohmic contact layer is arranged between the electrode and the light emitting layer; the projection of the ohmic contact layer on the light emergent layer is annular, and the outer diameter of the annular is smaller than the diameter of the circle; or the projection of the ohmic contact layer on the light emergent layer is a plurality of arcs distributed at intervals, and the outer diameter of each arc is equal to the diameter of each circle.
In another aspect, an embodiment of the present invention provides a method for manufacturing a light emitting diode chip, where the method includes:
growing a corrosion stop layer, an N-type limiting layer, an active layer, a P-type limiting layer and a window layer on a gallium arsenide substrate in sequence;
forming a current blocking layer and a filling layer on the window layer, wherein a plurality of through holes extending to the window layer are formed in the filling layer, and the current blocking layer is arranged in the through holes;
sequentially laying a transparent conducting layer, a metal reflecting layer and a first bonding layer on the current blocking layer and the filling layer;
forming a second bonding layer on the silicon substrate;
bonding the second bonding layer and the first bonding layer together;
removing the gallium arsenide substrate and the corrosion stop layer;
and arranging an electrode on the N-type limiting layer.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
a current blocking layer, a filling layer, a transparent conducting layer and a metal reflecting layer are additionally arranged between the window layer and the bonding layer, the current blocking layer is made of magnesium difluoride, the filling layer and the transparent conducting layer are made of one of indium tin oxide, tungsten oxide and tungsten-doped indium tin oxide, and the refractive index difference between the current blocking layer and the transparent conducting layer is large (the refractive index of magnesium difluoride is 1.38, the refractive index of indium tin oxide is 1.62, the refractive index of tungsten oxide is 1.65, and the refractive index of tungsten-doped indium tin oxide is 1.62-1.65); and the transparent conducting layer is arranged on the current blocking layer, and the current blocking layer and the transparent conducting layer can form a single-period Bragg reflector. And the metal reflecting layer is arranged on the transparent conducting layer, so that an omnibearing reflector is formed between the window layer and the bonding layer, light rays emitted to the P-type limiting layer from the active layer can be reflected to the N-type limiting layer to be emitted, and the front light emitting efficiency of the red light LED chip is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a light emitting diode chip according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a current blocking layer and a filling layer provided in an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an ohmic contact layer according to an embodiment of the invention;
FIG. 4 is a schematic structural diagram of another ohmic contact layer provided in the embodiment of the invention;
fig. 5 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a light emitting diode chip, in particular a red light LED chip. Fig. 1 is a schematic structural diagram of a light emitting diode chip according to an embodiment of the present invention. Referring to fig. 1, the light emitting diode chip includes a silicon substrate 10, a bonding layer 20, a metal reflective layer 31, a transparent conductive layer 32, a filling layer 33, a current blocking layer 34, a window layer 41, a P-type confinement layer 42, an active layer 43, an N-type confinement layer 44, and an electrode 50. The silicon substrate 10, the bonding layer 20, the metal reflective layer 31, the transparent conductive layer 32, the filling layer 33, the window layer 41, the P-type confinement layer 42, the active layer 43, the N-type confinement layer 44, and the electrode 50 are sequentially stacked.
Fig. 2 is a schematic structural diagram of a current blocking layer and a filling layer provided in an embodiment of the present invention. Referring to fig. 2, a plurality of through holes extending from the transparent conductive layer 32 to the window layer 41 are provided in the filling layer 33, and the current blocking layer 34 is provided in the through holes. The material of the current blocking layer 34 is magnesium difluoride, and the material of the filling layer 33 and the transparent conductive layer 32 is one of indium tin oxide, tungsten oxide, and tungsten-doped indium tin oxide.
According to the embodiment of the invention, the current blocking layer, the filling layer, the transparent conducting layer and the metal reflecting layer are additionally arranged between the window layer and the bonding layer, the material of the current blocking layer is magnesium difluoride, the material of the filling layer and the transparent conducting layer is one of indium tin oxide, tungsten oxide and tungsten-doped indium tin oxide, and the refractive index difference between the current blocking layer and the transparent conducting layer is large (the refractive index of magnesium difluoride is 1.38, the refractive index of indium tin oxide is 1.62, the refractive index of tungsten oxide is 1.65, and the refractive index of tungsten-doped indium tin oxide is 1.62-1.65); and the transparent conducting layer is arranged on the current blocking layer, and the current blocking layer and the transparent conducting layer can form a single-period Bragg reflector. And the metal reflecting layer is arranged on the transparent conducting layer, so that an omnibearing reflector is formed between the window layer and the bonding layer, light rays emitted to the P-type limiting layer from the active layer can be reflected to the N-type limiting layer to be emitted, and the front light emitting efficiency of the red light LED chip is improved. In addition, the magnesium difluoride is an insulating material, the indium tin oxide, the tungsten oxide and the tungsten-doped indium tin oxide are conductive materials, and the current blocking layer is arranged in the through holes in the filling layer, so that the current injection window layer is not influenced, and the current can be uniformly injected into the window layer.
Alternatively, the thicknesses of the current blocking layer 34 and the filling layer 33 may be 100nm to 140nm, and the thickness of the transparent conductive layer 32 may be 100nm to 300nm, so that the thicknesses of the current blocking layer 34 and the transparent conductive layer 32 are matched to each other, which is beneficial for implementing bragg reflection.
Further, as shown in fig. 2, the aperture d of the through hole may be 6 μm to 10 μm, and the pitch s between two adjacent through holes may be 10 μm to 20 μm. The distance between two adjacent through holes is about twice of the aperture of the through hole, which is beneficial to the uniform injection of current into the window layer.
Alternatively, the material of the metal reflective layer 31 may be silver. The silver has high reflectivity, so that an omnibearing reflector can be formed, and the light-emitting efficiency of the front side of the chip can be improved.
Illustratively, the surface roughness of the metal reflective layer 31 is 0.5nm to 3nm, and the reflectance of light having a wavelength of 550nm to 650nm can be maintained at 95% or more.
Further, the light emitting diode chip may further include a titanium tungsten alloy layer 35, and the titanium tungsten alloy layer 35 is disposed between the metal reflective layer 31 and the bonding layer 20. The titanium-tungsten alloy has good diffusion barrier property and adhesion property, can prevent silver from diffusing into the bonding layer, is favorable for fixing the bonding layer, and improves the reliability of the chip.
Furthermore, the content of the titanium component in the titanium-tungsten alloy layer 35 can be 10%, and the reliability of the chip is good.
Optionally, the light emitting diode chip may further include a current spreading layer 45, a transition layer 46, and a light emitting layer 47, where the current spreading layer 45, the transition layer 46, and the light emitting layer 47 are sequentially stacked on the N-type confinement layer 44, and the electrode 50 is disposed on a partial region of the light emitting layer 47. The current spreading layer 45, the transition layer 46 and the light emitting layer 47 are made of N-type doped (such as silicon) AlGaInP, the content of aluminum component in the current spreading layer 45 is less than that in the transition layer 46, and the content of aluminum component in the transition layer 46 is less than that in the light emitting layer 47. The aluminum component content in the current spreading layer is the lowest, and the doping concentration of silicon can be increased to 4 x 1018The method is favorable for current expansion; the light-emitting layer has the highest content of aluminum components, so that coarsening can be conveniently carried out, and the light-emitting efficiency of the front side of the chip is improved; the content of the aluminum component in the transition layer is between the current expansion layer and the light emergent layer, so that the transition effect can be achieved, and the influence on the crystal quality of the chip caused by too large difference of the content of the aluminum component in the current expansion layer and the content of the aluminum component in the light emergent layer is avoided.
Further, the content of the aluminum component in the current expansion layer 45 can be 20% -40%, the content of the aluminum component in the transition layer 46 can be 35% -60%, and the content of the aluminum component in the light emitting layer 47 can be 55% -70%, so that the matching effect is good.
Alternatively, the projection of the electrode 50 on the light exit layer 47 may be circular.
Further, the light emitting diode chip may further include an ohmic contact layer 48, the material of the ohmic contact layer 48 is N-type doped gallium arsenide, and the ohmic contact layer 48 is disposed between the electrode 50 and the light exit layer 47, so that ohmic contact is realized between the electrode and the epitaxial material, which is beneficial for the electrode to inject current into the epitaxial material.
Fig. 3 is a schematic structural diagram of an ohmic contact layer according to an embodiment of the present invention. Referring to fig. 3, in one implementation of the present embodiment, the projection of the ohmic contact layer 48 on the light exit layer 47 may be annular, and the outer diameter of the annular shape is smaller than the diameter of the circular shape.
Fig. 4 is a schematic structural diagram of another ohmic contact layer according to an embodiment of the invention. Referring to fig. 4, in another implementation manner of the present embodiment, the projection of the ohmic contact layer 48 on the light exit layer 47 may be a plurality of arcs distributed at intervals, and the outer diameter of the arc is equal to the diameter of the circle.
According to the two implementation modes, on the basis of realizing ohmic contact between the electrode and the epitaxial material, the occupied area of the ohmic contact layer is reduced as much as possible, and light absorption of gallium arsenide is avoided.
Optionally, the light emitting diode chip may further include a protective layer 60, and the material of the protective layer 60 is Si3N4A protective layer 60 is provided on the side of the chip to protect the epitaxial material from corrosion by oxygen and water vapor of the air. In practical applications, the light-exiting layer 47 is provided with a groove extending to the window layer 41, so that the protective layer 60 is deposited on the sidewall of the groove.
In this embodiment, the size of the chip may be 5mil to 10 mil. The material of the N-type confinement layer 44 may be N-type doped alinium phosphide, the material of the light-emitting layer 43 may be algan, the material of the P-type confinement layer 42 may be P-type doped alinium phosphide, and the window layer 41 may be P-type doped gallium phosphide. The bonding layer 20 may include a titanium layer, a platinum layer, a gold layer, an indium layer, a gold layer, a platinum layer, and a titanium layer, which are sequentially stacked, and the electrode 50 may include a gold layer, a gold-germanium-nickel alloy layer, a gold layer, a titanium layer, a platinum layer, and a gold layer, which are sequentially stacked. In practical application, a silicon substrate can be used as an electrode, and a titanium layer and a gold layer can be sequentially deposited on the silicon substrate to be used as the electrode.
Illustratively, the thickness of the metal reflective layer 31 may be 200nm to 500nm, and the thickness of the titanium-tungsten alloy layer may be 100nm to 300 nm; the thickness of the titanium layer in the bonding layer can be 100nm, the thickness of the platinum layer can be 80nm, the thickness of the gold layer can be 400nm, the thickness of the indium layer can be 2-4 mu m, and the deposition of the indium layerThe rate is more than 180 nm/s; the thickness of the titanium layer in the electrode on the silicon substrate may be 100nm and the thickness of the gold layer may be 400 nm. The doping concentration of the N-type dopant in the ohmic contact layer may be 7 × 1018/cm3In the above, the doping concentration of the P-type doping in the window layer may be 8 × 1019/cm3The above.
The embodiment of the invention provides a manufacturing method of a light-emitting diode chip, which is suitable for manufacturing the light-emitting diode chip shown in figure 1. Fig. 5 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present invention. Referring to fig. 5, the manufacturing method includes:
step 201: and sequentially growing a corrosion stop layer, an N-type limiting layer, an active layer, a P-type limiting layer and a window layer on the gallium arsenide substrate.
Optionally, the step 201 may include:
an etching stop layer, an N-type limiting layer, an active layer, a P-type limiting layer and a window layer are sequentially grown on a gallium arsenide substrate by adopting a Metal-organic Chemical vapor deposition (MOCVD) technology.
Step 202: and forming a current blocking layer and a filling layer on the window layer, wherein a plurality of through holes extending to the window layer are formed in the filling layer, and the current blocking layer is arranged in the through holes.
Optionally, this step 202 may include:
laying magnesium difluoride on the window layer by adopting an electron beam evaporation technology;
patterning magnesium difluoride by adopting a photoetching technology and a dry etching technology to form a current blocking layer;
and forming a filling layer between the patterns of the current blocking layer by adopting a sputtering technology.
In practical application, when the materials used for the filling layer and the transparent conductive layer are the same, the filling layer and the transparent conductive layer can be deposited together; when the materials used for the filling layer and the transparent conductive layer are different, the filling layer can be firstly deposited on the current blocking layer and between the current blocking layer, then the filling layer on the current blocking layer is removed, and finally the transparent conductive layer is deposited on the current blocking layer and the filling layer.
Step 203: and a transparent conductive layer, a metal reflecting layer and a first bonding layer are sequentially paved on the current blocking layer and the filling layer.
Optionally, this step 203 may comprise:
and a transparent conducting layer, a metal reflecting layer and a first bonding layer are sequentially paved on the current blocking layer and the filling layer by adopting a sputtering technology.
By adopting the sputtering technology, the film has good compactness and strong current expansibility.
In practical application, after the metal reflecting layer is formed, nitrogen can be introduced at the temperature of 250-500 ℃ for annealing. In addition, during the formation, vacuum is firstly pumped, and then argon is introduced to maintain the pressure at 0.2 Pa-10 Pa.
Step 204: a second bonding layer is formed on the silicon substrate.
Optionally, this step 203 may comprise:
a second bonding layer is formed on the silicon substrate using a sputtering technique.
Step 205: bonding the second bonding layer and the first bonding layer together.
Optionally, this step 205 may include:
bonding is carried out at the temperature of 280-320 ℃, and the bonding is firmer.
Step 206: and removing the gallium arsenide substrate and the corrosion stop layer.
Optionally, this step 206 may include:
wet etching the GaAs substrate and the etch stop layer.
Step 207: an electrode is provided on the N-type confinement layer.
Optionally, this step 207 may include:
forming a negative photoresist with a set pattern on the N-type limiting layer by adopting a photoetching technology;
laying electrode materials between the negative photoresist and the negative photoresist by adopting an electron beam evaporation technology;
the negative photoresist is stripped off, leaving the electrode material to form the electrode.
And the negative photoresist is adopted, so that the electrode is narrow at the top and wide at the bottom, and the adhesion is better.
Optionally, before step 207, the manufacturing method further includes:
epitaxially growing a current expansion layer, a transition layer, a light emitting layer and an ohmic contact layer on the N-type limiting layer;
and patterning the ohmic contact layer by adopting a photoetching technology and an ICP technology.
Further, after the patterning, the ohmic contact layer is annealed at a temperature of 300 ℃ to facilitate ohmic contact with the electrode.
Optionally, after step 207, the manufacturing method further includes:
forming a groove extending to the window layer on the light emitting layer by adopting a plasma etching technology;
chemically corroding the light emitting layer, and roughening the light emitting layer;
forming protective layers on the front side and the side face of the chip by adopting a PECVD (plasma enhanced chemical vapor deposition) technology;
and removing the protective layer on the front side of the chip by adopting photoetching and dry etching technologies.
Optionally, the manufacturing method may further include:
and thinning the silicon substrate.
Illustratively, the thickness of the silicon substrate can be thinned to 130 μm to 150 μm.
Further, the manufacturing method can further comprise the following steps:
depositing a titanium layer and a gold layer on the thinned silicon substrate in sequence;
annealing is performed at a temperature of 200 ℃ to increase adhesion and form good electrical contact.
After the products obtained in the steps are subjected to laser cutting and separation, the LED chip can be obtained, the front luminance of the LED chip is improved by 15%, and the reliability is high.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A light emitting diode chip, characterized in that it comprises a silicon substrate (10), a bonding layer (20), a metal reflective layer (31), a transparent conductive layer (32), a filling layer (33), a current blocking layer (34), a window layer (41), a P-type confinement layer (42), an active layer (43), an N-type confinement layer (44) and an electrode (50); the silicon substrate (10), the bonding layer (20), the metal reflection layer (31), the transparent conductive layer (32), the filling layer (33), the window layer (41), the P-type confinement layer (42), the active layer (43), the N-type confinement layer (44) and the electrode (50) are sequentially stacked, a plurality of through holes extending from the transparent conductive layer (32) to the window layer (41) are formed in the filling layer (33), and the current blocking layer (34) is arranged in the through holes; the material of the current blocking layer (34) is magnesium difluoride, and the material of the filling layer (33) and the material of the transparent conducting layer (32) are one of indium tin oxide, tungsten oxide and tungsten-doped indium tin oxide.
2. The light-emitting diode chip as claimed in claim 1, characterized in that the thickness of the current blocking layer (34) and the filling layer (33) is between 100nm and 140nm, and the thickness of the transparent electrically conductive layer (32) is between 100nm and 300 nm.
3. The light emitting diode chip of claim 2, wherein the aperture of the through hole is 6 μm to 10 μm, and the distance between two adjacent through holes is 10 μm to 20 μm.
4. The light-emitting diode chip as claimed in any of claims 1 to 3, wherein the material of the metal reflective layer (31) is silver.
5. The light-emitting diode chip according to claim 4, wherein the light-emitting diode chip further comprises a titanium tungsten alloy layer (35), the titanium tungsten alloy layer (35) being disposed between the metal reflective layer (31) and the bonding layer (20).
6. The light-emitting diode chip as claimed in claim 5, characterized in that the titanium-tungsten alloy layer (35) has a titanium component content of 10%.
7. The light-emitting diode chip according to any one of claims 1 to 3, wherein the light-emitting diode chip further comprises a current spreading layer (45), a transition layer (46) and a light-emitting layer (47), the current spreading layer (45), the transition layer (46) and the light-emitting layer (47) are sequentially stacked on the N-type confinement layer (44), and the electrode (50) is disposed on a partial region of the light-emitting layer (47); the current spreading layer (45), the transition layer (46) and the light emitting layer (47) are made of N-type doped aluminum gallium indium phosphide, the content of an aluminum component in the current spreading layer (45) is smaller than that in the transition layer (46), and the content of the aluminum component in the transition layer (46) is smaller than that in the light emitting layer (47).
8. The light-emitting diode chip as claimed in claim 7, wherein the content of the aluminum component in the current spreading layer (45) is 20% to 40%, the content of the aluminum component in the transition layer (46) is 35% to 60%, and the content of the aluminum component in the light-emitting layer (47) is 55% to 70%.
9. The light-emitting diode chip as claimed in claim 7, characterized in that the projection of the electrode (50) on the light-emitting layer (47) is circular; the light-emitting diode chip further comprises an ohmic contact layer (48), the material of the ohmic contact layer (48) is N-type doped gallium arsenide, and the ohmic contact layer (48) is arranged between the electrode (50) and the light emitting layer (47); the projection of the ohmic contact layer (48) on the light emitting layer (47) is annular, and the outer diameter of the annular is smaller than the diameter of the circle; or the projection of the ohmic contact layer (48) on the light emitting layer (47) is a plurality of arcs distributed at intervals, and the outer diameter of each arc is equal to the diameter of the circle.
10. A manufacturing method of a light emitting diode chip is characterized by comprising the following steps:
growing a corrosion stop layer, an N-type limiting layer, an active layer, a P-type limiting layer and a window layer on a gallium arsenide substrate in sequence;
forming a current blocking layer and a filling layer on the window layer, wherein a plurality of through holes extending to the window layer are formed in the filling layer, and the current blocking layer is arranged in the through holes;
sequentially laying a transparent conducting layer, a metal reflecting layer and a first bonding layer on the current blocking layer and the filling layer;
forming a second bonding layer on the silicon substrate;
bonding the second bonding layer and the first bonding layer together;
removing the gallium arsenide substrate and the corrosion stop layer;
and arranging an electrode on the N-type limiting layer.
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Application publication date: 20200121 |