CN110718569A - 1T2R memory cell based on resistive random access memory and preparation method thereof - Google Patents
1T2R memory cell based on resistive random access memory and preparation method thereof Download PDFInfo
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Abstract
The invention relates to a 1T2R memory cell based on a resistive random access memory and a preparation method thereof. The 1T2R storage unit based on the resistive random access memory comprises a MOSFET transistor and two resistive random access memories, wherein the two resistive random access memories are located at the drain end of the MOSFET transistor and are connected with the MOSFET transistor in series. The drain end of the MOSFET transistor is connected with two bit lines, and the two bit lines are respectively connected with the two resistive random access memories; when one of the two bit lines is high, the other bit line is low. The invention fully utilizes the area redundancy of the resistive random access memory array brought by the introduction of the MOSFET, so that the storage capacity is doubled under the same storage precision, or the storage precision is doubled under the same storage capacity, and the invention has important significance for the high-density integration of the resistive random access memory in the future.
Description
Technical Field
The invention belongs to the technical field of semiconductor and CMOS (complementary metal oxide semiconductor) hybrid integrated circuits, and particularly relates to a Resistive Random Access Memory (RRAM) based memory cell structure and a preparation method thereof.
Background
In recent years, as moore's law gradually approaches the limit, conventional Memory cells such as Dynamic Random Access Memory (DRAM) and Flash Memory (Flash) gradually face the physical limit of size reduction, and it is difficult to increase the storage capacity while reducing the production cost. In order to solve the problem, a series of novel memories, such as a resistive random access memory, a ferroelectric memory, a magnetic memory, a phase change memory and the like, are developed. The resistive random access memory has been widely regarded and researched in the academic and industrial fields due to its superior performances such as high integration density, high lamination potential, low production cost, etc.
When the resistive random access memories are integrated in an array, problems of leakage current between adjacent resistive random access memories, over-setting of the resistive random access memories and the like can be faced. At present, the solutions for commercialized mass-production resistive random access memories all adopt a structure of 1T1R (1 MOSFET is connected in series with one resistive random access memory), and the structure can effectively solve the two problems mentioned above, but the effective memory cell area can be originally 4F2Increase to 12F2(F is the lithographic size of the memory cell), the memory density is reduced, and the cell of 1T1R has a large redundant space on the resistive random access memory layer, and the advantage of small area of the resistive random access memory is not effectively utilized.
Disclosure of Invention
In order to solve the problems, the invention provides a novel resistive random access memory-based memory unit and a preparation method thereof.
The technical scheme adopted by the invention is as follows:
A1T 2R storage unit based on a resistive random access memory comprises a MOSFET transistor and two resistive random access memories, wherein the two resistive random access memories are located at the drain end of the MOSFET transistor and are connected with the MOSFET transistor in series.
Furthermore, the drain terminal of the MOSFET transistor is connected with two bit lines, and the two bit lines are respectively connected with the two resistive random access memories; when one of the two bit lines is high, the other bit line is low.
A memory comprises a plurality of memory cells, wherein the memory cells are the 1T2R memory cells based on the resistive random access memory.
A preparation method of the 1T2R memory cell based on the resistive random access memory comprises the following steps:
1) preparing a MOSFET device, namely a bottom layer;
2) preparing a first dielectric layer on the bottom layer, photoetching and patterning, and preparing a first through hole and a second through hole by etching, wherein the etching stop layer is the surface of the bottom layer;
3) preparing a first protective layer on the surface of the structure obtained in the step 2), then preparing a first metal layer, and then grinding the surface to be flat, wherein the stop layer is the surface of the first dielectric layer;
4) preparing a second metal layer on the surface of the structure obtained in the step 3), preparing a third metal layer on the surface of the second metal layer by using processes such as evaporation, sputtering and the like, and oxidizing the third metal layer to obtain a second dielectric layer;
5) preparing a fourth metal layer on the surface of the second dielectric layer, and preparing a second protective layer on the surface of the fourth metal layer;
6) photoetching and patterning the structure obtained in the step 4), etching the second metal layer, the second dielectric layer, the fourth metal layer and the second protective layer, only leaving the materials with the same parts as the patterns of the first through hole and the second through hole, and stopping etching on the surface of the first dielectric layer;
7) preparing a third dielectric layer on the structure obtained in the step 6), and grinding the surface;
8) photoetching and patterning the surface of the structure obtained in the step 7), preparing a third through hole above the first through hole, preparing a fourth through hole above the second through hole, and preparing a fifth through hole;
9) photoetching and patterning the surface of the structure obtained in the step 8), preparing a sixth through hole and a seventh through hole above the third through hole and the fourth through hole, and preparing an eighth through hole above the fifth through hole;
10) preparing a third protective layer on the surface of the structure obtained in the step 9), preparing a fifth metal layer on the third protective layer, and grinding the surface.
Furthermore, the second dielectric layer is directly formed by means of reactive ion sputtering, chemical vapor deposition, atomic layer deposition and the like, without adopting a mode of preparing a third metal layer and then oxidizing to form the second dielectric layer.
Furthermore, the materials of the first protective layer and the third protective layer are materials capable of improving the adhesion between metal and semiconductor, and the thickness is 1-15 nm.
Furthermore, the second protective layer is made of a material which is compatible with a CMOS process and meets a certain etching ratio with the third dielectric layer, such as tungsten, tantalum nitride, titanium nitride and the like, and the thickness of the second protective layer is 50-500 nm.
Furthermore, the first dielectric layer is made of a material capable of effectively preventing the metal layer from diffusing, and the thickness of the first dielectric layer is 5-50 nm; the second dielectric layer is made of transition metal oxide with excellent resistance change characteristics, and the thickness of the second dielectric layer is 2-30 nm; the third dielectric layer is made of a good insulator material and has a thickness of 100-1000 nm.
Furthermore, the materials of the first metal layer and the fifth metal layer are materials with excellent conductive characteristics, and the thickness is based on completely filling the through hole; the third metal layer is made of transition metal with excellent resistance change characteristics after oxidation and a compound thereof, and the thickness of the third metal layer is 2-50 nm.
Furthermore, the materials of the second metal layer and the fourth metal layer are a pair of materials with different metal activities, such as Pt/Cu, Au/Al, Hf/TiN, Hf/TaN, TiN/TaN, etc.
Further, when the ratio of metal atoms to oxygen atoms in the material of the third dielectric layer is asymmetric between the upper surface and the lower surface, the materials of the second metal layer and the fourth metal layer are the same material.
Further, the depth of the first through hole, the second through hole and the eighth through hole is 50-500nm, and the area of the first through hole, the second through hole and the eighth through hole is 0.015um2-2um2(ii) a The depth of the sixth through hole and the seventh through hole is 50-500nm, and the area is 0.01um2-2 um; the depth of the third through hole is 10-50nm, and the area is 0.003um2-1.5um2(ii) a The depth of the fourth through hole and the fifth through hole is 50-700nm, and the area is 0.003um2-1.5um2。
The invention has the following beneficial effects:
the invention provides a novel storage unit structure based on a resistive random access memory and an innovative preparation process. The memory cell structure provided by the invention fully utilizes the area redundancy of the resistive random access memory array brought by introducing the MOSFET, and integrates the resistive random access memory with higher density on the basis of not increasing the area of the existing 1T1R structure, so that the memory capacity is doubled under the same memory precision, or the memory precision is doubled under the same memory capacity. Therefore, the method has important significance for high-density integration of the resistive random access memory in the future.
Drawings
Fig. 1 to 10 are schematic diagrams of preparation processes of a 1T2R memory cell structure based on a resistive random access memory in an embodiment. Wherein:
FIG. 1 is a schematic diagram of the preparation of a dielectric layer and vias 1, 2 on a bottom layer;
fig. 2 is a schematic diagram of the preparation of the protective layer 210 and the metal layer 310.
Fig. 3 is a schematic diagram of preparing the metal layers 320 and 330.
Fig. 4 is a schematic diagram of the preparation of dielectric layer 120, metal layer 340 and protective layer 220.
Fig. 5 is a schematic diagram of etching metal layer 320, dielectric layer 120, metal layer 340, and protective layer 220.
Fig. 6 is a schematic diagram of the preparation of dielectric layer 130.
Fig. 7 is a schematic diagram of preparing the through-hole 3, the through-hole 4, and the through-hole 5.
Fig. 8 is a schematic diagram of preparing the through-hole 6, the through-hole 7, and the through-hole 8.
Fig. 9 is a schematic diagram of preparing the protective layer 230 and the metal layer 350.
Fig. 10 is an illustration of fig. 1-9.
Fig. 11 is a circuit connection schematic diagram of a 1T2R memory cell structure based on a resistive random access memory in the embodiment.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention shall be described in further detail with reference to the following detailed description and accompanying drawings.
The invention provides a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two resistive random access memory series unit structures (1T2R) realized based on a traditional Complementary Metal Oxide Semiconductor (CMOS) process and a preparation method thereof, and the resistive random access memory with good and stable performance is prepared through a specially designed process flow. The memory structure of 1T2R is such that two bit lines (in a MOS transistor, a drain line is a bit line, and a gate line is a word line) and two resistance change memories (two bit lines are connected to the two resistance change memories, respectively) are connected to each MOSFET, as shown in fig. 11. Two bit lines of the same MOSFET are in an EVEN/ODD form, namely when one bit line is high, the other bit line must be low (which can be realized by an external circuit). Compared with the traditional 1T1R structure, the structure has the advantages that the integration density is doubled on the premise of keeping the unit area unchanged, or the storage precision is doubled on the premise of keeping the integration density unchanged.
The 1T2R memory cell structure based on the resistive random access memory adopts the following preparation method:
1. the MOSFET device, namely the bottom layer 100, is prepared by adopting an industry-mature process, and the preparation steps of the invention begin from the dielectric layer 110, and focus on the integration of a novel device of the resistive random access memory device and the traditional MOSFET device.
2. A dielectric layer 110 is prepared on the bottom layer by PVD (physical vapor deposition) or CVD (chemical vapor deposition), patterned by lithography, and via holes 1 and 2 are prepared by RIE (reactive ion etching), the etch stop layer being the surface of the bottom layer. As shown in fig. 1.
3. The protective layer 210 is prepared on the surface of the structure in the previous step by PVD, then the metal layer 310 is prepared by PVD or electroplating, and then the surface is polished by CMP (chemical mechanical polishing), and the stop layer is the surface of the dielectric layer 110. As shown in fig. 2.
4. The metal layer 320 is prepared on the surface of the structure by PVD in the previous step, and then the metal layer 330 is prepared on the surface by PVD. As shown in fig. 3.
5. At O2Or N2O or N2+O2Or H2O+O2And oxidizing the metal layer 330 in the same atmosphere to obtain the dielectric layer 120, preparing a metal layer 340 on the surface of the dielectric layer 120 by PVD, and preparing a protective layer 220 on the surface of the metal layer 340. As shown in fig. 4.
6. Photoetching and patterning are carried out on the structure in the last step, RIE is used for etching the metal layer 320, the dielectric layer 120, the metal layer 340 and the protective layer 220, only materials of the parts with the same patterns of the through hole 1 and the through hole 2 are left, and etching is stopped on the surface of the dielectric layer 110. As shown in fig. 5.
7. Dielectric layer 130 is prepared by PVD or CVD and the surface is planarized by CMP. As shown in fig. 6.
8. The surface of the structure is subjected to photoetching patterning in the last step, a through hole 3 is prepared above the through hole 1 by RIE, a through hole 4 is prepared above the through hole 2, and a through hole 5 is prepared. As shown in fig. 7.
9. The surface of the structure is subjected to photoetching patterning in the last step, a through hole 6 and a through hole 7 are prepared above the through hole 3 and the through hole 4 by RIE, and a through hole 8 is prepared above the through hole 5. As shown in fig. 8.
10. The protective layer 230 is prepared on the surface of the structure in the previous step by PVD, the metal layer 350 is prepared on the protective layer 230 by PVD or electroplating process, and the surface is polished by CMP. As shown in fig. 9.
In the preparation method, the preparation method of the second dielectric layer is to prepare the third metal layer first and then oxidize the third metal layer to form the second dielectric layer. The second dielectric layer can be directly formed by using the modes of reactive ion sputtering, chemical vapor deposition, atomic layer deposition and the like instead of the mode.
In the structure shown in fig. 9, the metal layer 320, the dielectric layer 120 and the metal layer 340 form a resistive random access memory, and the resistive random access memory has two resistive random access memories, which are located at the drain terminal of the bottom MOSFET transistor and connected in series with the bottom MOSFET transistor. The protective layers 210 and 230 function to improve adhesion between the metal material and the semiconductor material, and specifically, the protective layer 210 increases adhesion between the dielectric layer 110 and the metal layer 310, and the protective layer 230 increases adhesion between the dielectric layer 130 and the metal layer 350. The metal layer 310 is used for communicating the drain terminal of the bottom layer MOSFET with the bottom electrode of the resistive random access memory. The metal layer 350 at the three through holes is used for leading out the top electrode of the resistive random access memory.
Preferably, the bottom MOSFET transistor is first fabricated by industry-mature processes on a substrate, which is a silicon substrate or a glass substrate, such as Pyrex 7740, Borofloat 33, etc.
Preferably, the material of the protective layer 210, 230 is a material capable of improving adhesion between metal and semiconductor, such as Cr, Ti, Ni, etc., and has a thickness of 1-15 nm.
Preferably, the material of the protection layer 220 is a material that is compatible with a CMOS process and satisfies a certain etching ratio with the third dielectric layer, such as tungsten, tantalum nitride, titanium nitride, and the like, and has a thickness of 50-500 nm.
Preferably, the dielectric layer 110 is made of a material capable of effectively preventing the diffusion of the metal layer, such as Ta, Co, SiN, TaN, TiW, and the like, and has a thickness of 5-50 nm.
Preferably, the material of the dielectric layer 120 is a transition metal oxide with excellent resistance change characteristics, such as HfOx、TaOx、NiOx、SrOxEtc. with a thickness of 2-30 nm.
Preferably, the dielectric layer 130 is made of a good insulator material, such as SiLK, FOx, MSQ, NanoglassHOSP, etc., and has a thickness of 100-.
Preferably, the material of the metal layers 310 and 350 is a material with excellent conductive characteristics, such as AI, Cu, W, Pt, etc., and the thickness is controlled to completely fill the via hole.
Preferably, the material of the metal layers 320 and 340 is usually a pair of materials with different metal activities, and may be metal or a compound with strong conductivity, such as Pt/Cu, Au/Al, Hf/TiN, Hf/TaN, TiN/TaN, etc. When the ratio of the metal atoms to the oxygen atoms in the material of the dielectric layer 130 is asymmetric between the upper surface and the lower surface, the material of the metal layers 320 and 340 may be the same material, such as Pt, Au, TiN, etc. The thickness is 5-50 nm.
Preferably, the material of the metal layer 330 is a transition metal and its compound with excellent resistance change characteristics after oxidation, such as Hf, Ni, Sr, TaN, etc., and the thickness is 2-50 nm.
Preferably, the depth of the through holes 1, 2 and 8 is 50-500nm, and the area is 0.015um2-2um2. The depth of the through holes 6 and 7 is 50-500nm, and the area is 0.01um2-2 um. The depth of the through hole 3 is 10-50nm, and the area is 0.003um2-1.5um2. The depth of the through holes 4 and 5 is 50-700nm, and the area is 0.003um2-1.5um2。
The above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person skilled in the art can modify the technical solution of the present invention or substitute the same without departing from the principle and scope of the present invention, and the scope of the present invention should be determined by the claims.
Claims (10)
1. The 1T2R storage unit based on the resistive random access memory is characterized by comprising a MOSFET transistor and two resistive random access memories, wherein the two resistive random access memories are located at the drain end of the MOSFET transistor and are connected with the MOSFET transistor in series.
2. The 1T2R memory cell based on resistive random access memory according to claim 1, wherein the drain terminal of the MOSFET transistor is connected to two bit lines, and the two bit lines are respectively connected to the two resistive random access memories; when one of the two bit lines is high, the other bit line is low.
3. A memory comprising a plurality of memory cells, wherein the memory cells are the 1T2R memory cells based on the resistive random access memory as claimed in claim 1 or 2.
4. The preparation method of the 1T2R memory cell based on the resistive random access memory as claimed in claim 1, characterized by comprising the following steps:
1) preparing a MOSFET device, referred to as an underlayer (100);
2) preparing a first dielectric layer (110) on the bottom layer (100), photoetching and patterning, and preparing a first through hole (1) and a second through hole (2) by etching, wherein the etching stop layer is the surface of the bottom layer;
3) preparing a first protective layer (210) on the surface of the structure obtained in the step 2), then preparing a first metal layer (310), and then grinding the surface to be flat, wherein the stop layer is the surface of the first dielectric layer (110);
4) preparing a second metal layer (320) on the surface of the structure obtained in the step 3), then preparing a third metal layer (330) on the surface of the structure, and oxidizing the third metal layer (330) to obtain a second dielectric layer (120);
5) preparing a fourth metal layer (340) on the surface of the second dielectric layer (120), and preparing a second protective layer (220) on the surface of the fourth metal layer;
6) photoetching and patterning the structure obtained in the step 5), etching the second metal layer (320), the second dielectric layer (120), the fourth metal layer (330) and the second protective layer (220), only leaving materials of the parts same as the patterns of the first through hole (1) and the second through hole (2), and stopping etching on the surface of the first dielectric layer (110);
7) preparing a third dielectric layer (130) on the structure obtained in the step 6), and grinding the surface;
8) photoetching and patterning the surface of the structure obtained in the step 7), preparing a third through hole (3) above the first through hole (1), preparing a fourth through hole (4) above the second through hole (2), and preparing a fifth through hole (5);
9) photoetching and patterning the surface of the structure obtained in the step 8), preparing a sixth through hole (6) and a seventh through hole (7) above the third through hole (3) and the fourth through hole (4), and preparing an eighth through hole (8) above the fifth through hole (5);
10) preparing a third protective layer (230) on the surface of the structure obtained in the step 9), preparing a fifth metal layer (350) on the third protective layer (230), and grinding the surface.
5. The method of claim 4, wherein the second dielectric layer is directly formed by reactive ion sputtering, chemical vapor deposition, or atomic layer deposition, instead of forming the second dielectric layer by preparing the third metal layer and oxidizing the third metal layer.
6. The method according to claim 4, wherein the first protective layer (210) and the third protective layer (230) are made of a material capable of improving adhesion between a metal and a semiconductor and have a thickness of 1-15 nm; the second protective layer (220) is made of a material which is compatible with a CMOS process and meets a certain etching ratio with the third dielectric layer, and the thickness of the second protective layer is 50-500 nm.
7. The method of claim 4, wherein the first dielectric layer (110) is made of a material effective to prevent diffusion of the metal layer and has a thickness of 5-50 nm; the second dielectric layer (120) is made of transition metal oxide with excellent resistance change characteristics, and the thickness of the second dielectric layer is 2-30 nm; the third dielectric layer (130) is a good insulator material with a thickness of 100-1000 nm.
8. The method of claim 4, wherein the material of the first metal layer (310) and the fifth metal layer (350) is a material having excellent conductive characteristics, and the thickness is based on completely filling the via hole; the third metal layer (330) is made of transition metal and compounds thereof with excellent resistance change characteristics after oxidation, and the thickness is 2-50 nm.
9. The method of claim 4, wherein the material of the second metal layer (320) and the fourth metal layer (340) is a pair of materials with different metal activities, and is one of the following materials: Pt/Cu, Au/Al, Hf/TiN, Hf/TaN, TiN/TaN; when the ratio of metal atoms to oxygen atoms in the material of the third dielectric layer (130) is asymmetric on the upper surface and the lower surface, the materials of the second metal layer (320) and the fourth metal layer (340) are the same material.
10. Method according to claim 4, characterized in that the first through hole (1), the second through hole (2), the eighth through hole (8) have a depth of 50-500nm and an area of 0.015um2-2um2(ii) a The depth of the sixth through hole (6) and the seventh through hole (7) is 50-500nm, and the area is 0.01um2-2 um; the depth of the third through hole (3) is 10-50nm, and the area is 0.003um2-1.5um2(ii) a The depth of the fourth through hole (4) and the fifth through hole (5) is 50-700nm, and the area is 0.003um2-1.5um2。
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