CN110690211B - Electrostatic discharge protection structure and electrostatic discharge robust semiconductor device - Google Patents
Electrostatic discharge protection structure and electrostatic discharge robust semiconductor device Download PDFInfo
- Publication number
- CN110690211B CN110690211B CN201811390017.7A CN201811390017A CN110690211B CN 110690211 B CN110690211 B CN 110690211B CN 201811390017 A CN201811390017 A CN 201811390017A CN 110690211 B CN110690211 B CN 110690211B
- Authority
- CN
- China
- Prior art keywords
- region
- substrate
- deep well
- protection structure
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 230000003321 amplification Effects 0.000 claims abstract description 51
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 51
- 230000003071 parasitic effect Effects 0.000 claims abstract description 15
- 210000000746 body region Anatomy 0.000 claims description 30
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 239000000969 carrier Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000013022 venting Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 102100035767 Adrenocortical dysplasia protein homolog Human genes 0.000 description 2
- 101100433963 Homo sapiens ACD gene Proteins 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000035568 catharsis Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an electrostatic discharge protection structure and an electrostatic discharge robust semiconductor device. The deep well area is arranged on the substrate; the drain region is arranged on the deep well region and is used as an input end; the top doped region is arranged on the deep well region and is adjacent to the drain region; the oxide layer region is arranged on the top doped region and covers the top doped region and part of the drain region; the grid region is arranged on the oxidation layer region and covers a part of the deep well region and the oxidation layer region to be used as a control end; the base region is arranged on the substrate and is adjacent to the gate region to serve as a base end; the amplification region is arranged on the substrate and is positioned on one side of the base region relative to the gate region, and is far away from the gate region to serve as an output end. Through the arrangement, parasitic transistors are formed among the amplification region, the base region and the drain region so as to discharge electrostatic pulses.
Description
Technical Field
The present invention relates to the field of electrostatic discharge protection structures, and more particularly, to an electrostatic discharge protection structure for protecting a semiconductor device from electrostatic damage and an electrostatic discharge robust semiconductor device thereof.
Background
Electrostatic discharge (ESD) is a phenomenon of surface charge discharge, which causes damage to integrated circuits, semiconductor devices, and circuits formed by the integrated circuits and semiconductor devices. Generally, electrostatic discharge is usually caused artificially, for example, static electricity is accumulated in human body, instruments, storage equipment, etc. even in electronic components themselves during the manufacturing, production, assembly, testing, storage, transportation, etc. of electronic components or systems, and these objects are contacted with each other unknowingly, thereby forming a discharge path, and the electronic components or systems are damaged by the electrostatic discharge.
Therefore, in order to avoid the electrostatic discharge phenomenon, an electrostatic protection circuit or an element is usually added to the conventional circuit. The LDMOS (Laterally Diffused Metal Oxide Semiconductor) is a common esd protection device, however, the conventional LDMOS cannot withstand a high voltage of more than 2kV, and the gate of the conventional LDMOS is damaged after being used many times, resulting in a functional failure of the whole LDMOS.
The prior art of U.S. Pat. No. 7916439B2 discloses adding a bipolar transistor to a ldmos to reduce the damage to its gate after multiple uses, however, the added bipolar transistor results in longer device length of ldmos and increased size of integrated circuit, which makes it difficult to apply the additional bipolar transistor in integrated circuits requiring miniaturization.
In view of the foregoing, the inventor of the present invention has devised and designed an esd protection structure and an esd robust semiconductor device to overcome the shortcomings of the prior art and further enhance the industrial application.
Disclosure of Invention
In view of the above-mentioned problems, it is an object of the present invention to provide an esd protection structure and an esd robust semiconductor device, which solve the problems encountered in the prior art.
In view of the above, the present invention provides an esd protection structure, which includes a substrate, a deep well region, a drain region, a top doped region, an oxide layer region, a gate region, a base region and an amplification region. The deep well area is arranged on the substrate; the drain region is arranged on the deep well region and is used as an input end; the top doped region is arranged on the deep well region and is adjacent to the drain region, and the top doped region enables an electric field among the drain region, the substrate region and the amplification region to be uniform; the oxide layer region is arranged on the top doped region and covers the top doped region and part of the drain region; the grid region is arranged on the oxidation layer region and covers a part of the deep well region and the oxidation layer region to be used as a control end; the base region is arranged on the substrate and is adjacent to the gate region to serve as a base end; the amplification region is arranged on the substrate and is positioned on one side of the base region relative to the gate region, and is far away from the gate region to serve as an output end. The amplification region and the drain region are of a first conductivity type, the body region is of a second conductivity type, and parasitic transistors are generated among the amplification region, the body region and the drain region. When electrostatic pulse is input from the input end and flows through the gate region, the current path of the parasitic transistor is lengthened due to the fact that the amplification region is far away from the gate region, so that damage of the electrostatic pulse to the gate region is reduced, and the voltage born by the electrostatic discharge protection structure is indirectly improved from 1kV to more than 2 kV.
Preferably, the substrate further comprises a guiding region disposed on a side of the substrate opposite to the deep well region, and the amplification region and the body region are disposed on the guiding region, the guiding region and the body region being of the second conductivity type.
Preferably, the substrate further includes a drain region and a guiding region, the guiding region is disposed on a side of the substrate opposite to the deep well region, the drain region is disposed on the substrate and adjacent to the guiding region and away from the deep well region, the body region is disposed on the guiding region, and the amplification region is disposed on the drain region. The substrate region and the guide region are of the second conductivity type, the amplification region and the vent region are of the first conductivity type, and the depth of the guide region is greater than that of the vent region.
Preferably, a spacer is provided between the amplification region and the base region, and the spacer prevents conduction between the amplification region and the base region.
Preferably, the drain region includes a well and a carrier drift region, the carrier drift region is located on the well, and the well provides carriers.
In view of the above, the present invention provides an electrostatic discharge robust semiconductor device, which includes a protected device and an electrostatic discharge protection structure. The electrostatic discharge protection structure comprises a substrate, a deep well region, a drain region, a top doped region, an oxide layer region, a gate region, a base region and an amplification region. The deep well region is arranged on the substrate to block carriers of the substrate; the drain region is arranged on the deep well region to be used as an input end, and the input end is connected with the pin of the protected element; the top doped region is arranged on the deep well region and is adjacent to the drain region, and the top doped region enables an electric field among the drain region, the substrate region and the amplification region to be uniform; the oxide layer region is arranged on the deep well region and covers the top doped region and part of the drain region; the grid region is arranged on the oxidation layer region and covers a part of the deep well region and the oxidation layer region to be used as a control end; the base region is arranged on the substrate and is adjacent to the gate region to serve as a base end; the amplification region is arranged on the substrate and is positioned on one side of the base region relative to the gate region, and is far away from the gate region to serve as an output end. When the electrostatic pulse is input from the pin of the protected element and the output end is grounded, the electrostatic discharge protection structure is in annular configuration and the electrostatic pulse is greater than the threshold voltage of the electrostatic discharge protection structure, so that the electrostatic discharge protection structure is enabled to be conducted, and the electrostatic pulse is released at the output end to achieve the purpose of protecting the protected element from being damaged due to the electrostatic pulse.
Preferably, the esd protection structure further comprises a guiding region disposed on a side of the substrate opposite to the deep well region, and the amplifying region and the body region are disposed on the guiding region, the guiding region and the body region are of the second conductivity type, and the amplifying region is of the first conductivity type.
Preferably, the esd protection structure further comprises a guiding region and a venting region, the guiding region is disposed on a side of the substrate opposite to the deep well region, the venting region is disposed on the substrate and adjacent to the guiding region and away from the deep well region, the body region is disposed on the guiding region, and the amplification region is disposed on the venting region. The substrate region and the guide region are of the second conductivity type, the amplification region and the vent region are of the first conductivity type, and the depth of the guide region is greater than that of the vent region.
Preferably, a spacer is provided between the amplification region and the base region, the spacer preventing conduction between the amplification region and the base region.
Preferably, the drain region includes a well and a carrier drift region, the carrier drift region being located on the well, the carrier drift region and the well providing carriers.
In view of the above, the esd protection structure and the esd robust semiconductor device of the present invention extend the current path of the parasitic transistor through the arrangement of the amplification region, thereby reducing the damage of the electrostatic pulse to the gate region and indirectly increasing the voltage that the esd protection structure can bear.
In view of the above, the electrostatic discharge robust semiconductor device and the electrostatic discharge robust semiconductor device of the present invention utilize the ring configuration and the amplification region of the electrostatic discharge protection structure to enable the electrostatic pulse to enter the electrostatic discharge protection structure instead of the protected device, so as to achieve the purpose of protecting the protected device from being damaged by the electrostatic pulse.
Drawings
FIG. 1 is a top view of an ESD robust semiconductor device in accordance with the present invention;
FIG. 2 is a cross-sectional view of a first embodiment of an ESD protection structure in an ESD robust semiconductor device in accordance with the present invention;
FIG. 3 is a cross-sectional view of a protected device portion in the ESD robust semiconductor device in accordance with the present invention;
FIG. 4 is a cross-sectional view of a second embodiment of an ESD protection structure according to the present invention;
FIG. 5 is a cross-sectional view of a third embodiment of an ESD protection structure according to the present invention;
FIG. 6 is a cross-sectional view of a fourth embodiment of an ESD protection structure according to the present invention.
Description of reference numerals:
1: an electrostatic discharge protection structure; 2: a protected element;
10. 2_ 10: a substrate; 20. 2_ 20: a deep well region;
30. 2_ 30: a drain region; 31: a well portion;
32: a carrier drift portion; 40. 2_ 40: a top doped region;
50. 2_ 50: an oxidation layer area; 60. TRAN _ 60: a gate region;
70. TRAN _ 70: a base region; 80: an amplification region;
90: a guide area; 100: a parasitic transistor;
110. 2_ 80: a spacer; 120: a catharsis area;
2_ 31: a first well portion; 2_ 32: a first carrier drift region;
2_ 71: a second well portion; 2_ 72: a second carrier drift portion;
2_ D: a drain electrode; 2_ S: a source electrode;
B. 2_ B: a substrate end; b1: a base electrode;
CN: a control end; c1: a collector electrode;
e1: an emitter; IN: an input end;
OUT: and (4) an output end.
Detailed Description
The advantages, features, and technical solutions of the present invention will be more readily understood by describing in greater detail exemplary embodiments and the accompanying drawings, and the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein, but rather provided as an embodiment within the scope of the present invention as defined by the claims.
Please refer to fig. 1, which is a top view of the electrostatic discharge robust semiconductor device of the present invention. The ESD robust semiconductor device of the present invention includes an ESD protection structure 1 and a protected device 2. The esd current fed through the protected device 2 can be discharged through the esd protection structure 1, as described in detail below.
Please refer to fig. 2, which is a cross-sectional view of a first embodiment of an esd protection structure portion in an esd robust semiconductor device according to the present invention, taken along the line I-I' in fig. 1. The esd-protection structure 1 includes a substrate (P-sub)10, a deep well region 20(DNW), a drain region 30, a top doped region (PTOP)40, an oxide layer region 50, a gate region (POLY1)60, a body region 70(NPLUS), and an amplification region (PPLUS) 80. The deep well 20 is disposed on the substrate 10 to block carriers from the substrate 10. The drain region 30 is disposed on the deep well region 20 as an input terminal IN (M1) and the input terminal IN (M1) is connected to the protected device 2, and includes a well 31(NWELL) and a carrier drift region (NPLUS)32, wherein the carrier drift region 32 is disposed on the well 31, and the well 31 is a first conductive type well and provides carriers. The top doped region 40 is disposed on the deep well region 20 and adjacent to the drain region 30, and the top doped region 40 homogenizes the electric field among the drain region 30, the substrate region 70 and the amplification region 80. The oxide region 50 is disposed on the deep well region 20 and covers the top doped region 40 and a portion of the drain region 30. The gate region 60 is disposed on the oxide region 50 and covers a portion of the deep well region 20 and the oxide region 50 as a control terminal CN (M1). The base region 70 is disposed on the substrate 10 and adjacent to the gate region 60 as a base end B (M1). The amplification region 80 is disposed on the substrate 10 on a side of the base region 70 opposite the gate region 60 and away from the gate region 60 as an output terminal OUT (M1). Wherein the amplification region 80 and the drain region 30 are of a first conductivity type and the body region 70 is of a second conductivity type, a parasitic transistor 100 is formed between the amplification region 80, the body region 70 and the drain region 30. When the electrostatic pulse is input from the pin of the protected device 2 and the output terminal OUT is grounded, the electrostatic pulse is greater than the threshold voltage of the electrostatic discharge protection structure 1, so as to turn on the electrostatic discharge protection structure 1, and the electrostatic pulse is released at the output terminal OUT to achieve the purpose of protecting the protected device 2 from the electrostatic pulse.
In addition, the esd-protection structure 1 further includes a guiding region (PWELL)90, the guiding region 90 is disposed on a side of the substrate 10 opposite to the deep well region 20 and contacts the gate region 60, and the amplification region 80 and the body region 70 are disposed on the guiding region 90, the guiding region 90 and the body region 70 are of the second conductivity type, and the guiding region 90 is a well region for providing carriers to the body region 70.
Fig. 3 is a cross-sectional view of a protected device portion of the electrostatic discharge robust semiconductor device according to the present invention. In this embodiment, the protected device 2 may be a Junction Field Effect Transistor (JFET), which is not specifically limited by the invention. As shown in fig. 3, the protected device 2 includes a substrate (P-sub)2_10, a deep well region (DNW)2_20, a drain region 2_30, two top doped regions (PTOP)2_40, an oxide layer region 2_50, a source region (NPLUS)2_60, and a body region 2_ 70. The deep well region 2_20 is disposed on the substrate 2_10 to block carriers of the substrate 2_ 10. The drain region 2_30 is disposed on the deep well region 2_20 as a drain 2_ D (M1), and the drain 2_ D is connected to the input IN of the ESD protection structure 1. The drain region 2_30 further includes a first well (NWELL)2_31 and a first carrier drift region (NPLUS)2_32, the first carrier drift region 2_32 is located on the first well 2_31, and the first well 2_31 is a first conductive well and provides carriers. The two top doped regions 2_40 are disposed on the deep well region 2_20 and adjacent to the drain region 2_30, and the two top doped regions 2_40 homogenize the electric field between the drain region 2_30 and the source region 2_ 60. The oxide region 2_50 is disposed on the deep well region 2_20 and covers the two top doped regions 2_40 and a portion of the drain region 2_30, and the oxide region 2_50 contacts the two top doped regions 2_40, respectively. The source region 2_60 is disposed on the deep well region 2_20 as the source (M1)2_ S. The body region 2_70 is disposed on the substrate 2_10 and adjacent to the deep well region 2_20 as a body terminal 2_ B (M1), and includes a second well Portion (PWELL)2_71 and a second carrier drift portion (PPLUS)2_72, and the second well portion 2_71 is a second conductive type well region and provides carriers. The deep well region 2_20, the drain region 2_30 and the source region 2_60 are of a first conductivity type, the two top doped regions 2_40 and the body region 2_70 are of a second conductivity type, the oxide region 2_50 is made of silicon dioxide, and a spacer 2_80 is provided between the source region 2_60 and the second carrier drift region 2_72 to prevent the source region 2_60 and the body region 2_70 from being turned on. The foregoing is a general configuration of junction field effect transistors, and the types of transistors can be changed according to actual requirements without limiting the scope of the invention. As mentioned above, when the electrostatic pulse is inputted from the drain 2_ D of the protected device 2 and the output terminal OUT is grounded, since the electrostatic pulse is greater than the threshold voltage of the esd protection structure 1, the esd protection structure 1 is further activated to be turned on, and the electrostatic pulse is released at the output terminal OUT to achieve the purpose of protecting the protected device 2 from the electrostatic pulse.
It should be noted that the gate of the protected device 2 and the gate of the esd protection structure 1 are shared, that is, the gate region 60 of the esd protection structure 1 is shared with the protected device 2, and the control terminal CN simultaneously controls the conduction of the esd protection structure 1 and the protected device 2, so the gate of the protected device 2 is omitted.
It should be noted that the esd protection structure 1 may be configured in a ring shape, and most of the electrostatic pulses are introduced to achieve the purpose of reliably protecting the protected device 2 from the electrostatic pulses, and further, the gate region 60 is effectively isolated between the drain region 30, the amplification region 80 and the body region 70, so that the electrostatic pulses are smoothly guided to the amplification region 80 for output. In addition, the current path of the parasitic transistor 100 is lengthened due to the distance between the amplification region 80 and the gate region 60, so as to reduce the damage of the electrostatic pulse to the gate region 60, and increase the voltage that the electrostatic discharge protection structure 1 can withstand from 1kV to about 2kV or more with the same device size.
In addition, the configuration of the esd protection structure 1 can be set as follows: in this embodiment, the first conductivity type is n-type, the second conductivity type is p-type, and the first conductivity type can be changed into p-type and the second conductivity type can be changed into n-type according to actual requirements without limiting the scope of the present invention; the n-type and p-type are achieved by doping the semiconductor material with impurities, the semiconductor material is silicon and the impurities are group III elements or group V elements, and the doping with impurities can be achieved by ion implantation or molecular beam epitaxy.
In other words, the substrate 10 is a second conductive type substrate, and includes a silicon substrate and a second conductive type epitaxial layer on the silicon substrate, and the thickness of the second conductive type epitaxial layer is adjusted according to the actual configuration; the carriers are electrons or holes according to the difference between the first conductivity type and the second conductivity type, in this embodiment, the carriers of the first conductivity type are electrons, and the carriers of the second conductivity type are holes; the well region is defined by exposure and development, and then doped with impurities to complete the formation of the first conductive type well region or the second conductive type well region. The foregoing configuration settings are adopted in the following and other embodiments, and the configuration settings need not be repeated.
It is worth mentioning the arrangement of the top doped region 40 and the oxide layer region 50. The top doped region 40 is of the second conductivity type to provide holes for balancing electrons of the drain region 30, so as to avoid the phenomenon of local concentration of the electric field of the drain region 30, and by optimizing the concentration and length of the top doped region 40 and the drain region 30, the charge balance of the drain region 30 and the top doped region 40 and the reduction of the on-resistance of the esd protection structure 1 are achieved. The oxide layer region 50 is disposed between the top doped region 40 and the gate region 60 and may be comprised of silicon dioxide, and the oxide layer region 50 contacts a portion of the gate region 60 to prevent the electrostatic pulse from directly breaking down the gate region 60 due to the contact of the oxide layer region 50 and the gate region 60 while improving current flow between the drain region 30 and the guide region 90.
Please refer to fig. 4, which is a configuration diagram of an esd protection structure according to a second embodiment of the present invention. In the present embodiment, the configuration of the elements with the same reference numerals is similar to that described above, and the description of the similarity is omitted here. As shown in fig. 4, the difference between the second embodiment and the first embodiment is that the esd protection structure 1 of the second embodiment has a spacer 110 between the amplification region 80 and the body region 70, and the spacer 110 is made of silicon dioxide to prevent conduction between the amplification region 80 and the body region 70, so that current flows more smoothly among the drain region 30, the gate region 60, the amplification region 80 and the body region 70.
Please refer to fig. 5, which is a configuration diagram of an esd protection structure according to a third embodiment of the present invention. In the present embodiment, the configuration of the elements with the same reference numerals is similar to that described above, and the description of the similarity is omitted here. As shown in FIG. 5, the ESD protection structure 1 of the third embodiment further includes a drain region 120, the drain region 120 is disposed on the substrate 10 adjacent to the guiding region 90 and away from the deep well region 20, and the amplifying region 80 is disposed on the drain region 120. Wherein the body region 70 and the guiding region 90 are of the second conductivity type, the amplifying region 80 and the venting region 120 are of the first conductivity type, and the guiding region 90 and the venting region 120 are well regions for providing holes and electrons to the body region 70 and the amplifying region 80.
The venting area 120 is configured to increase the voltage that the esd protection structure 1 can withstand, as further described below:
the gain value β of the parasitic transistor 100 is related as follows:
the parasitic transistor 100 includes an emitter E1, a base B1, and a collector C1, NEConcentration of emitter E1 of parasitic transistor 100, NBBy adjusting the concentration of the emitter E1 to be greater than the concentration of the base B1, the concentration of the base B1 of the parasitic transistor 100 can increase the value of the gain β, and thus the voltage that the esd protection structure 1 can withstand. The vent region 120 is disposed adjacent to and around the amplification region 80 and has the same conductivity type as the amplification region 80Equal to the concentration N of the emitter E1EThereby achieving the purpose of increasing the voltage that the electrostatic discharge protection structure 1 can bear.
Please refer to fig. 6, which is a configuration diagram of an esd protection structure according to a fourth embodiment of the present invention. In the present embodiment, the configuration of the elements with the same reference numerals is similar to that described above, and the description of the similarity is omitted here. As shown in fig. 6, the difference between the fourth embodiment and the third embodiment is that the guiding region 90 of the fourth embodiment is composed of a plurality of well regions, and the arrangement of the plurality of well regions reduces the volume of the guiding region 90, thereby reducing the concentration of the guiding region 90, reducing the concentration of the base B1 of the parasitic transistor 100, increasing the gain β of the parasitic transistor 100, and achieving the purpose of increasing the withstand voltage of the esd protection structure 1.
In summary, the esd protection structure of the present invention, through the arrangement of the amplification region 80, the current path of the parasitic transistor 100 is lengthened, the length of the esd protection structure 1 is not affected, and the voltage that the esd protection structure 1 can withstand is increased to 2 kV. The electrostatic discharge robust semiconductor device of the present invention uses the ring configuration of the electrostatic discharge protection structure 1 and the amplification region 80 to make the electrostatic pulse enter the electrostatic discharge protection structure 1 instead of the protected device 2, thereby achieving the purpose of protecting the protected device 2. In summary, the esd protection structure of the present invention and the esd robust semiconductor device of the present invention have the advantages as described above, and can withstand a voltage of 2kV and reduce damage to the gate region 60.
The foregoing is by way of example only, and not limiting. Any equivalent modifications or variations without departing from the spirit and scope of the present invention should be included in the claims of the present invention.
Claims (8)
1. An ESD protection structure, comprising:
a substrate;
a deep well region disposed on the substrate;
a drain region arranged on the deep well region as an input end;
a top doped region disposed on the deep well region and adjacent to the drain region;
an oxide layer region arranged on the top doped region and covering the top doped region and a part of the drain region;
the gate region is arranged on the oxide region and covers a part of the deep well region and the oxide region to be used as a control terminal;
the base region is arranged on the substrate and is adjacent to the gate region to serve as a base terminal; and
the amplification region is arranged on the substrate, is positioned on one side of the base region relative to the gate region and is far away from the gate region to serve as an output end;
wherein the amplification region and the drain region are of a first conductivity type, the body region is of a second conductivity type, and a parasitic transistor is generated between the amplification region, the body region and the drain region;
the electrostatic discharge protection structure further comprises a guiding region, the guiding region is arranged on one side, opposite to the deep well region, of the substrate, and the amplification region and the substrate region are arranged on the guiding region.
2. The ESD protection structure of claim 1, further comprising a drain region and a guiding region, wherein the guiding region is disposed on a side of the substrate opposite to the deep well region, the drain region is disposed on the substrate adjacent to the guiding region and away from the deep well region, the body region is disposed on the guiding region, and the amplification region is disposed on the drain region.
3. The esd-protection structure of claim 1, wherein a spacer is disposed between the amplification region and the substrate region, the spacer preventing conduction between the amplification region and the substrate region.
4. The ESD protection structure of claim 1, wherein the drain region comprises a well and a carrier drift region, the carrier drift region being located on the well.
5. An electrostatic discharge robust semiconductor device, comprising:
a protected element; and
an ESD protection structure, comprising:
a substrate;
a deep well region disposed on the substrate;
a drain region disposed on the deep well region as an input terminal, wherein the input terminal is connected to a pin of the protected device;
a top doped region disposed on the deep well region and adjacent to the drain region;
an oxide layer region arranged on the top doped region and covering the top doped region and a part of the drain region;
the gate region is arranged on the oxide region and covers a part of the deep well region and the oxide region to be used as a control terminal;
the base region is arranged on the substrate and is adjacent to the gate region to serve as a base terminal; and
the amplification region is arranged on the substrate, is positioned on one side of the base region relative to the gate region and is far away from the gate region to serve as an output end;
when an electrostatic pulse is input from the pin of the protected element and the output end is grounded, the electrostatic pulse is larger than a threshold voltage of the electrostatic discharge protection structure to cause the electrostatic discharge protection structure to be conducted, and the electrostatic pulse is then released at the output end;
the electrostatic discharge protection structure further comprises a guiding region, the guiding region is arranged on one side, opposite to the deep well region, of the substrate, and the amplification region and the substrate region are arranged on the guiding region.
6. The ESD robust semiconductor device of claim 5, wherein the ESD protection structure further comprises a drain region and a guiding region, the guiding region is disposed on the substrate at a side opposite to the deep well region, the drain region is disposed on the substrate adjacent to the guiding region and away from the deep well region, the body region is disposed on the guiding region, and the amplification region is disposed on the drain region.
7. The electrostatic discharge robust semiconductor device of claim 5, wherein a spacer is provided between the amplification region and the body region, the spacer preventing conduction between the amplification region and the body region.
8. The ESD robust semiconductor device of claim 5, wherein the drain region comprises a well and a carrier drift region, the carrier drift region being located over the well.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107123354 | 2018-07-05 | ||
| TW107123354A TWI706534B (en) | 2018-07-05 | 2018-07-05 | Esd protection structure and esd robust semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110690211A CN110690211A (en) | 2020-01-14 |
| CN110690211B true CN110690211B (en) | 2021-10-26 |
Family
ID=69107146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811390017.7A Active CN110690211B (en) | 2018-07-05 | 2018-11-21 | Electrostatic discharge protection structure and electrostatic discharge robust semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110690211B (en) |
| TW (1) | TWI706534B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI827466B (en) * | 2023-02-14 | 2023-12-21 | 新唐科技股份有限公司 | Esd protection device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120175673A1 (en) * | 2011-01-12 | 2012-07-12 | Mueng-Ryul Lee | Semiconductor device and fabricating method thereof |
| CN104037171A (en) * | 2013-03-04 | 2014-09-10 | 旺宏电子股份有限公司 | Semiconductor element, and manufacturing method and operation method thereof |
| US20160372578A1 (en) * | 2008-10-29 | 2016-12-22 | Tower Semiconductor Ltd. | Double-resurf ldmos with drift and psurf implants self-aligned to a stacked gate "bump" structure |
-
2018
- 2018-07-05 TW TW107123354A patent/TWI706534B/en active
- 2018-11-21 CN CN201811390017.7A patent/CN110690211B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160372578A1 (en) * | 2008-10-29 | 2016-12-22 | Tower Semiconductor Ltd. | Double-resurf ldmos with drift and psurf implants self-aligned to a stacked gate "bump" structure |
| US20120175673A1 (en) * | 2011-01-12 | 2012-07-12 | Mueng-Ryul Lee | Semiconductor device and fabricating method thereof |
| CN104037171A (en) * | 2013-03-04 | 2014-09-10 | 旺宏电子股份有限公司 | Semiconductor element, and manufacturing method and operation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202006921A (en) | 2020-02-01 |
| CN110690211A (en) | 2020-01-14 |
| TWI706534B (en) | 2020-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9570630B2 (en) | Schottky diode structure | |
| US7244975B2 (en) | High-voltage device structure | |
| US9373710B2 (en) | Insulated gate bipolar transistor | |
| KR20070103311A (en) | Semiconductor device | |
| US20130113036A1 (en) | Transistor Assembly as an ESD Protection Measure | |
| KR102255545B1 (en) | A semiconductor device and a method of manufacturing a semiconductor device | |
| US10978870B2 (en) | Electrostatic discharge protection device | |
| US11139288B2 (en) | Silicon-controlled-rectifier electrostatic protection structure and fabrication method thereof | |
| CN110690211B (en) | Electrostatic discharge protection structure and electrostatic discharge robust semiconductor device | |
| US11373996B2 (en) | Silicon-controlled-rectifier electrostatic protection structure and fabrication method thereof | |
| TWI652768B (en) | Layout structure of esd protection device with high esd tolerance | |
| CN107452786B (en) | Transistor structure with field plate to reduce its area | |
| US10438943B2 (en) | Field-effect transistor and semiconductor device | |
| KR20190121015A (en) | SCR device for protecting ESD | |
| US20110298104A1 (en) | Semiconductor Body with a Protective Structure and Method for Manufacturing the Same | |
| US7508038B1 (en) | ESD protection transistor | |
| JP4197660B2 (en) | MOS transistor and semiconductor integrated circuit device having the same | |
| CN116207090A (en) | Electrostatic discharge protection structure | |
| US6559515B1 (en) | Insulating wall between power components | |
| TWI678790B (en) | Electrostatic discharge protection device | |
| JP7281807B2 (en) | Semiconductor device and its manufacturing method | |
| US10943978B2 (en) | High voltage device and manufacturing method thereof | |
| US9748339B1 (en) | Semiconductor device and method for fabricating the same | |
| JP2022084984A (en) | Semiconductor device | |
| US10249713B2 (en) | Semiconductor device including an ESD protection element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |