CN110690189B - EHSOP5L lead frame of high-power driving circuit, packaging piece and production method thereof - Google Patents
EHSOP5L lead frame of high-power driving circuit, packaging piece and production method thereof Download PDFInfo
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- CN110690189B CN110690189B CN201911018161.2A CN201911018161A CN110690189B CN 110690189 B CN110690189 B CN 110690189B CN 201911018161 A CN201911018161 A CN 201911018161A CN 110690189 B CN110690189 B CN 110690189B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000009713 electroplating Methods 0.000 claims abstract description 7
- 238000004080 punching Methods 0.000 claims abstract description 7
- 239000003292 glue Substances 0.000 claims abstract description 4
- 239000004033 plastic Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 31
- 230000008569 process Effects 0.000 claims description 25
- 239000000047 product Substances 0.000 claims description 19
- 239000002313 adhesive film Substances 0.000 claims description 17
- 230000017525 heat dissipation Effects 0.000 claims description 15
- 238000005520 cutting process Methods 0.000 claims description 14
- 238000011068 loading method Methods 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 12
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- 238000012360 testing method Methods 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000011417 postcuring Methods 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
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- 238000010438 heat treatment Methods 0.000 claims description 3
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- 238000005476 soldering Methods 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
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- 238000003475 lamination Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a eHSOP L lead frame of a high-power driving circuit, a packaging piece and a production method thereof, wherein the lead frame is provided with a multi-row matrix type double-connecting rod single-base lead frame, five inner pins with rectangular heads and rectangular tails are arranged at the upper ends of base islands and connected with a lead frame body, two radiating fins with the same width are arranged at the lower ends of the base islands, a rectangular second stress release groove is arranged between the two radiating fins, one end of each radiating fin is connected with the base island, pi-shaped glue locking holes are formed at the connecting positions of the radiating fins and the base islands, two double-connecting rods are respectively arranged at two sides of the base islands, and the double-connecting rods are connected with the lead frame body; the lead frame has the advantages of small thickness, low price, environment-friendly material in production, copper alloy electroplating lead frame for the low-cost IC packaging piece in the punching production process, environmental protection and physical health of a user, miniaturization, high reliability, shorter packaging period, low cost and the like.
Description
Technical Field
The invention belongs to the field of IC chip integrated circuit packaging, and particularly relates to a eHSOP L lead frame of a high-power driving circuit, a packaging piece and a production method thereof.
Background
Integrated circuits (INTEGRATED CIRCUIT abbreviated as ICs) have been a new technology introduced into china for recent 30 years. The integrated circuit IC chip with the functions of storage, operation and the like is encapsulated in a plastic material, so that the integrated circuit IC chip becomes a carrier capable of storing, transferring, transmitting and processing data. In order to adapt to the development direction of lighter, thinner and smaller integrated circuits, the packaging technology conforms to the advantages of low failure rate, high density, miniaturization, space saving, lower cost, good heat dissipation and the like, and can shorten the time of product marketing and reduce investment risk. The high-power small-colloid packaging technology has the characteristics of small size, high heat dissipation and the like in foreign countries, and is in line with the development trend of integrated circuit products. The industry market speed increase is maintained at 15% -20% every year in the last 10 years, and the method has the advantages of large information storage amount, good security, quick storage and the like, is widely applied to various fields such as telecom, household appliances, commerce and trade, traffic, urban public utility management and the like, and achieves primary social benefit and economic benefit. However, the high-power driving circuit package with high reliability, high voltage and high insulativity adopts an SOP or DIP package form at present, has the advantages of more pins, large volume and more material consumption, and has a larger gap with similar products at home and abroad.
EHSOP (Small Outline PACKAGE WITH exposed THERMAL PAD AND HEAT SINK) is a novel SMT technology (surface mounting technology), and on the basis of the existing SOP technology, the development of eHSOP technology can rapidly improve the level of the domestic integrated circuit packaging technology. eHSOP the packaged product has many advantages such as miniaturization, high reliability, shorter packaging period, low cost and the like. The product adopting eHSOP packaging technology can be widely applied to various fields such as LED lamps, power adapter handheld mobile terminals, consumer electronic products, personal computers, peripheral, network, telecommunication equipment, medical equipment, office equipment, automobile electronics, industrial control equipment and the like, and has wider market prospect.
Disclosure of Invention
The object of the present invention is to provide a eHSOP L lead frame for a high-power driving circuit, which solves the above problems in the prior art.
Another object of the present invention is to provide a package formed of eHSOP L lead frame for a high-power driving circuit.
Another object of the present invention is to provide a method for manufacturing eHSOP L package of high-power driving circuit.
In order to achieve the above purpose, the invention adopts the following technical scheme: a eHSOP L lead frame of a high-power driving circuit comprises a lead frame body, wherein a plurality of lead frame unit groups which are arrayed are arranged on the lead frame body, each lead frame unit group is formed by a first lead frame part and a second lead frame part, the first lead frame part and the second lead frame part are respectively formed by two lead frame units, outer pins of two adjacent rows of frame units are arranged in a staggered manner, a process groove is formed between the first lead frame part and the second lead frame part, a first stress release groove is formed between the two adjacent lead frame unit groups, a base island is arranged on each lead frame unit, five inner pins which are rectangular in head portion and connected with the lead frame body are sequentially arranged at the upper ends of the base island, the inner pins are a first inner pin, a second inner pin, a third inner pin, a fourth inner pin and a fifth inner pin, the lower ends of the base island are provided with two heat dissipation fins with the same width, a rectangular second stress release groove is formed between the two heat dissipation fins, one end of each heat dissipation island is connected with the base island, two heat dissipation pins are connected with the base island, two heat dissipation rods are connected with the two heat dissipation rods, and two heat dissipation rods are connected with the base rods, and two heat dissipation rods are connected with the heat dissipation rods.
Further, the tops of the first lead frame part and the second lead frame part are respectively provided with a round frame anti-reflection hole and an oval frame anti-reflection hole.
Further, the lead frame has a length 249.60mm + -0.10 mm, a width 79.50 mm + -0.05 mm, and a thickness of 0.19 mm-0.21mm, and comprises 120 lead frame units arranged in 6 rows and 20 columns.
The invention provides a eHSOP L packaging piece production method of a high-power driving circuit, which comprises the following steps:
a. Wafer thinning
Thinning by a thinning machine, wherein the final thickness of the wafer is as follows: the thickness of the first chip is 100-120 mu m, and the thickness of the second chip is 200-300 mu m; the rough grinding speed is less than or equal to 35 mu m/min; the precision speed is less than or equal to 10 mu m/min, stress is eliminated, the film is cleaned, and a thinning adhesive film is stuck on the back surface;
b. scribing
Scribing by using a double-scribing-blade scribing machine, wherein the first cutter firstly scribes 30% of the thickness setting and takes a groove, the second cutter scribes 70% of the thickness setting, the scribing feeding speed is controlled to be less than or equal to 10mm/s, and the cleaning and drying are timely carried out;
c. Upper core
A lead frame according to any one of claims 1-3, wherein after automatic feeding, the chip is packaged in a lamination manner through a twice chip feeding process, and the method specifically comprises the following steps:
Core loading for the first time: the first chip is adhered to the lead frame by the core loading machine, and is adhered to the chip mounting area of the base island by using the environment-friendly high-silver conductive adhesive through a 2mm multiplied by 2mm chip suction nozzle and a dispensing head;
And (3) primary core loading baking: the whole lead frame stuck with the first chip is sent to a transfer box and is transferred to an oven, and the oven is baked by adopting a layering-preventing sectional baking process;
And (5) core loading for the second time: using equipment with a core-on-film function, fixing a wafer of a second chip with a DAF film attached to the back surface before dicing, automatically feeding by the equipment, then feeding a semi-finished lead frame with a first chip attached to a die bonding table, heating a substrate to 120 ℃, adsorbing the second chip with the DAF film, and placing the second chip on the front surface of the first chip;
And (5) secondary core loading baking: after all lead frames of the second chips are pasted, the lead frames are sent to a transfer box and are sent to an oven, and baking is carried out in the oven by adopting a layering-preventing sectional baking process;
d. Pressure welding
Bonding a metal wire or copper wire by pressure welding to realize a low-radian control technology, adopting a combination of flat arc and forward and reverse striking, and a high-grade wire arc shape of a sharp corner and a high-grade wire arc shape of a flat corner, controlling the arc height to be less than or equal to 150 mu m, and bonding a first chip and a second chip with an inner pin, a first chip and an inner pin, and an upper chip and a base island by using a welding wire;
e. plastic package and post-curing
An environment-friendly plastic package material is selected, and an ultrathin warp-preventing and delamination-reducing process is adopted to reduce the wire punching rate, reduce the back-packaging or the back-packaging, and reduce the curing time by 10 to 30S than normal; and (3) aging the semi-finished product bar of the lead frame of the IC packaging piece at 175 ℃ for 5 hours in an oven during post-curing, so that the warping degree of the plastic packaging body meets the requirements of printing, stamping and forming packaging processes, and the overflow of the radiating fin is ensured not to exceed 10% of the area of the radiating fin.
F. Electroplating
The automatic plating wire is adopted to carry out a tin plating process on the packaging piece and the copper alloy plating lead which leaks outside, so that the surface of the connecting pin is plated with soldering tin, and the thickness of the plating layer is 11.43+/-3.81 mu m;
g. Printing
The fixture type fixing, double laser heads, continuous feeding, positioning and printing modes are adopted to mark the surface of the plastic package;
h. Cutting ribs, forming and separating
Cutting off the double connecting rods connected to the lead frame by adopting a special rib cutting die, wherein the gap between the rib cutting tool and the plastic package body is more than 0.075mm, and meanwhile, plastic package residues on the surface of the die are cleaned, so that the rubber body is prevented from being padded;
i. Testing and packaging
The special tester and the sorting machine are adopted to test the appearance and the functional parameters, so that the products provided by customers can be used on the machine, and the use requirements of the packaging piece are met; and packaging and warehousing to obtain eHSOP L packaging parts of the high-power driving circuit.
Further, in the step a, the rough grinding thickness range is from 550 μm to 800 μm of the original wafer to 120 μm of the adhesive film, to 120 μm of the final thickness to 120 μm of the adhesive film to 50 μm of the final thickness, and the precision thickness range is from 120 μm of the final thickness to 120 μm of the adhesive film to 50 μm of the final thickness to 150 μm of the wafer to 120 μm of the adhesive film, and the chip warpage preventing process is adopted.
The invention discloses a eHSOP L package of a high-power driving circuit produced by adopting the production method, which comprises a first chip, a second chip and a lead frame unit, wherein the first chip is adhered to a chip mounting area of a base island by using high-silver conductive adhesive, the second chip is adhered to the surface of the first chip by using DAF film stacking, bonding pads on the surfaces of the first chip and the second chip are connected with corresponding inner pins and a carrier base island by lead bonding wires, the first chip, the second chip and the base island are all in plastic package, the plastic package is arranged with exposed parts of two radiating fins, five independent tinned outer pins with the spacing of 1.70mm are respectively arranged on the lower row of the plastic package, and the protruding parts of the five independent tinned outer pins are respectively 0.5mm to 1.5 mm.
Further, the first chip is connected with the second chip through a first bonding wire, and the second chip is connected with the fourth inner pin through a third bonding wire; the first chip is connected with the first inner pin through a second bonding wire, and the first chip is connected with the base island through a fourth bonding wire X4.
Further, a first pin mark is arranged on the plastic package body.
Further, the thickness of the package is 1.60 mm ±0.05 mm.
The beneficial effects of the invention are as follows:
1. The lead frame of the invention has small thickness and low price, is a multi-row matrix lead frame, has the material thickness of 0.19-0.21 mm, is thinner than the common copper-clad PCB by 0.023-0.06 mm, has higher production efficiency than the copper-clad PCB, has higher packaging yield, adopts environment-friendly materials in production, adopts the copper alloy electroplating lead frame for the low-cost IC packaging piece in the punching type production process, and is beneficial to environmental protection and health of users; has the advantages of miniaturization, high reliability, shorter packaging period, low cost and the like. .
2. The pi-shaped adhesive locking holes are formed at the joint of the base island and the double radiating fins, so that part of the base island and pins which are encapsulated up and down are firmly combined with the plastic package material, the reliability of the product is improved, the length of bonding wires is reduced, the current and signal transmission distance is shortened, and the electrical performance is improved.
3. The exposed base island is directly connected with the double radiating fins, so that the radiating performance of the product is greatly improved, and the product has high reliability and high radiating performance; and the outer pins of two adjacent rows of frame units on the lead frame are arranged in a staggered manner in a crossing manner, so that the frame benefit rate is greatly improved.
4. The invention is provided with a round frame anti-reflection hole and an oval frame anti-reflection hole at the top of the first lead frame part and the second lead frame part respectively, which can prevent the frame from being reversed.
5. A rectangular second stress release groove is arranged between the two radiating fins and is used for releasing stress during forming and separating of the rib cutting product and preventing the package from cracking.
Drawings
FIG. 1 is a schematic diagram of a eHSOP L lead frame of a high-power driving circuit according to the present invention;
Fig. 2 is a schematic structural view of a lead frame unit set according to the present invention;
FIG. 3 is a schematic diagram of a bonding wire for chip package according to the present invention;
FIG. 4 is an out schematic view of a leadframe unit according to the present invention;
FIG. 5 is a schematic view of a package structure according to the present invention;
FIG. 6 is a schematic cross-sectional view of a package of the present invention;
FIG. 7 is a graph of upper core bake temperature;
FIG. 8 is a graph of core stack bake temperature.
In the figure: 1. a lead frame body; 2. a lead frame unit group; 3. a first lead frame portion; 4. a second lead frame portion; 5. A lead frame unit; 6. A base island; 7. a process tank; 8. a first stress relief groove; 9. a second stress relief groove; 10. a first chip; 11. a second chip; 12. a plastic package body; 13. a die bond adhesive; 14. a round frame anti-reverse hole; 15. an anti-reverse hole of the oval frame; 16. a heat sink; 17. a first foot print; 18. a first inner pin; 19. a second inner pin; 20. a third inner pin; 21. a fourth inner pin; 22. a fifth inner pin; b. A double connecting rod; C. a locking hole; 23. a first outer pin; 24. a second outer pin; 25. a third outer pin; 26. a fourth outer pin; 27. A fifth outer pin; x1, a first bonding wire; x2, a second bonding wire; x3, third bond wire; and X4, a fourth bonding wire.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 1 and 2, a eHSOP L lead frame of a high-power driving circuit, which has a length of 249.60mm±0.10 mm, a width of 79.50 mm ±0.05mm and a thickness of 0.19 mm-0.21mm, comprises a total of 120 lead frame units 5 arranged in 6 rows and 20 columns, and specifically comprises a lead frame body 1, wherein a plurality of lead frame unit groups 2 arranged in an array are arranged on the lead frame body 1, each lead frame unit group 2 transversely consists of a first lead frame part 3 and a second lead frame part 4, the first lead frame part 3 and the second lead frame part 4 respectively consist of two lead frame units 5, the outer pins of two adjacent rows of the lead frame units 5 are arranged in a manner of being staggered in a crossing manner, the frame benefit rate is greatly improved, a process groove 7 is arranged between the first lead frame part 3 and the second lead frame part 4, a first stress release groove 8 is arranged between two adjacent lead frame unit groups 2, a base island 6 is arranged on the lead frame unit 5, five inner pins with rectangular T-shaped head parts and connected with the lead frame body 1 are arranged at the upper end of the base island 6, a first inner pin 18, a second inner pin 19, a third inner pin 20, a fourth inner pin 21 and a fifth inner pin 22 are sequentially arranged at the lower end of the base island 6, two radiating fins 16 with the same width are arranged at the lower end of the base island 6, a rectangular second stress release groove 9 is arranged between the two radiating fins 16, one end of each radiating fin 16 is connected with the base island 6, pi-shaped glue locking holes C are arranged at the connecting parts of the radiating fins 16 and the base island 6, two double connecting rods B are respectively arranged at two sides of the base island 6, and the double connecting rods B are connected with the lead frame body 1; the top of the first lead frame part 3 and the second lead frame part 4 are respectively provided with a circular frame anti-reflection hole 14 and an oval frame anti-reflection hole 15 to prevent the frame from being reversely put.
The invention provides a eHSOP L package production method of a high-power driving circuit, which comprises the following specific steps:
a. Wafer thinning
The equipment for thinning is a VG502 MKII 8B full-automatic thinning machine (Germany), the first chip 10 is a high-power driving circuit MOS chip, the final thickness of a wafer where the first chip 10 is positioned is 120 mu m, the rough grinding thickness range is from 550 mu m to 800 mu m of the original wafer thickness to 120 mu m of the adhesive film thickness, and the rough grinding speed is 35 mu m/min from the final thickness of 120 mu m to 120 mu m of the adhesive film thickness to 120 mu m+50 mu m; the precision thickness range is from the final thickness of 120 μm+the thickness of 120 μm+50 μm to the final thickness of 150 μm+the thickness of 120 μm of the film of the wafer, the precision speed is 10 μm/min, and the chip warpage prevention process is adopted. The final thickness of the wafer on which the second chip 11 is located is 50 μm; the thickness range of the rough grinding is from 550-800 mu m of the original wafer thickness to 120 mu m of the adhesive film thickness, and the final thickness is 50 mu m to 120 mu m of the adhesive film thickness to 30 mu m, the rough grinding speed is 30-35 mu m/min, the starting speed is high, and the speed is gradually reduced; the precision thickness range is from the final thickness of 50 μm plus the thickness of 120 μm plus 30 μm to the final thickness of 50 μm plus the thickness of 120 μm of the wafer, the precision speed is 10 μm/min, and a chip warpage prevention process is adopted;
b. scribing
The DISCO DFD6361, DFD6340, DFD6560 or double-blade dicing machine is adopted, the dicing feed speed is controlled to be less than or equal to 10mm/s, and the dicing blade is selected to be of a proper model according to different products and the width of a dicing channel of a wafer, and is cleaned and dried in time. A double-head dicing saw is adopted, double-blade dicing is adopted, the first blade is used for firstly dicing 30% of the thickness setting and grooving, and the second blade is used for dicing 70% of the thickness setting, so that cracking and back collapse are prevented;
c. Upper core
The core feeding machine adopts a general core feeding machine, the adhesive selects the conductive adhesive with low viscosity (viscosity is more than 9000 CP) and low stress and low water absorption, the upper core adopts the eHSOP L lead frame of the high-power driving circuit, and the back surface of the lead frame is adhered with the anti-overflow adhesive film. The chip of the first chip 10 is relatively large, a chip suction nozzle with the thickness of 2mm multiplied by 2mm and a dispensing head are selected, the size is close to a base island because the thickness of the first chip 10 is thinner, the problems of climbing, overflowing, BLT, hollowness, bridging and the like of the chip side adhesive are caused when the chip is arranged, the dispensing quality of the adhesive is ensured by adopting measures of optimizing a dispensing tool, related technological parameters and the like aiming at the problems, the whole lead frame stuck with the first chip is sent to a transfer box and is sent to an oven, and the oven is baked by adopting an anti-layering sectional baking process, wherein a baking curve is shown in fig. 7; because the second chip 11 is thinner and smaller, a DAF film is stacked on the first chip 10, after the two layers of chips are cored, a baking oven with good air exhaust quantity and uniform internal temperature is selected after the two layers of chips are cored, the baking oven adopts low-temperature-high-temperature-low-temperature (30 minutes at 0-70 ℃, 90 minutes at 70-150 ℃ and 30 minutes at 150-70 ℃) for one-time delamination-preventing baking, and a baking curve is shown in figure 8;
d. Pressure welding
The pressure welding adopts integrated circuit welding spot generating software, and because the thickness of the packaging piece is thin, the pressure welding adopts a chopper which is suitable for the welding spot requirement, and the gold wire bonding low-radian control technology. And adopting the combination of flat arc, reverse striking and forward striking to form the advanced wire arc shape of the sharp corner and the advanced wire arc shape of the flat corner. Firstly, bonding wires are formed from the second chip 11 to the first chip 10 to form a second bonding wire X1, and the arc height is controlled within 100 mu m; next, a third bonding wire X3 is formed by bonding wires from the second chip 11 to the fourth inner lead 21; next, a first bonding wire X2 is formed by bonding wires from the first chip 10 to the first inner leads 18, a fourth bonding wire X4 is formed by bonding wires from the first chip 10 to the base island 6, the arc height is controlled to be within 150 μm, and the arc heights of the first bonding wire X2, the third bonding wire X3 and the fourth bonding wire X4 are controlled to be within 150 μm. The widths of semi-finished products of the lead frames of the multi-row matrix copper alloy electroplating eHSOP L are larger, and the widths of the special multi-row windowing clamps used by the copper wire bonding station are also larger; because the clamp pressing plate and the heating block are tightly matched with the copper wire bonding machine worktable, the loosening phenomenon cannot occur after the installation; therefore, the special clamp pressing structure matched with the frame is redesigned, so that the frame pins are tightly matched with the clamp, and the frame pin is tightly matched with the clamp, as shown in fig. 3.
E. Plastic package
The environment-friendly plastic package material with high reliability is used, wherein the viscosity is more than 8500CP, the stress is low, the water absorption is less than 0.3 percent; using a fully automated encapsulation mold, to be vacuum adsorbed, application layering analysis software V1.4 (2011 SR 17091), multi-section injection molding software V1.0 (20111 SR0131 152), and void hundred percent measurement software (2011 SR 012173) were used.
The process adopts ultrathin warp-preventing and delamination-reducing and eliminating processes, and controls different injection molding speeds to reduce the wire punching rate, control the wire punching rate to be less than 8%, reduce the turn-up or turn-up, and increase the curing time by 10S-30S compared with the normal process so as to achieve the purpose of reducing the warp degree.
In the post-curing process, the upper clamp plate and the lower base are both flat, and the upper clamp plate of the IC clamp is larger than a multi-row matrix copper alloy electroplated eHSOP L lead frame semi-finished product after plastic packaging, and the clamp material is a chromed thick steel plate. The semi-finished product of the lead frame which is subjected to multi-row matrix copper alloy electroplating eHSOP L after plastic packaging is aged for 5 hours in a baking oven at 175 ℃, gradually becomes soft, and is flattened under the gravity of a pressing plate on an IC clamp; the semi-finished product of the multi-row matrix copper alloy electroplated eHSOP L lead frame after plastic packaging is taken out from the oven at the temperature below 70 ℃, and is completely cooled under the gravity of the pressing plate on the clamp, the warping degree of the plastic packaging body 12 can meet the requirements of printing, stamping and cutting processes, and secondary warping caused by rapid temperature drop is prevented;
f. Electroplating
Plating a tin plating process on a multi-row matrix copper alloy electroplated eHSOP L lead frame semi-finished product by adopting an automatic plating line, so that the surfaces of five independent outer pins of the semi-finished product are plated with a layer of soldering tin, and the thickness of a product plating layer is controlled to be 11.43+/-3.81 mu m;
g. Printing
Marking the surface of the packaging piece by adopting a full-automatic printer, and printing marks on the surface of a plated multi-row matrix copper alloy plated eHSOP L lead frame semi-finished product by adopting a clamp type fixing, double laser heads and continuous feeding positioning printing mode;
h. Cutting ribs, punching and separating
And a special full-automatic rib cutting system and a rib cutting die are adopted to cut double connecting rods B connected to a multi-row matrix copper alloy electroplated eHSOP L lead frame semi-finished product, the gap between a rib cutting tool and the plastic package body 12 is larger than 0.075mm, the plastic package body 12 is prevented from being punched, meanwhile, plastic package residues on the surface of the die are cleaned in time, and the rubber body is reduced from being padded.
The die-cut separation type tray feeding or pipe feeding method is adopted in the die-cut production process, in order to avoid the damage of the die-cut blades to the plastic package body 12 during die-cut separation, the distance from the die-cut blades to the plastic package body 12 is controlled to be 0.15mm on the premise of meeting the product quality requirement, the die is used for fixing and compacting the plastic package body 12 up and down, suspension is avoided, residual glue fragments in the die are cleaned in time in production, and the product deviation caused by residual foreign matters is prevented, so that the plastic package body 12 is broken due to the extrusion of redundant matters.
I. Testing and packaging
And (3) testing appearance and functional parameters of the punched and separated semi-finished product of the matrix copper alloy electroplated eHSOP L lead frame by adopting a special testing machine and a sorting machine, ensuring that products provided by customers can be used on the machine, meeting the use requirements of packaging parts, packaging and warehousing according to the customer requirements, and preparing the eHSOP L packaging parts of the high-power driving circuit.
The specific process of packaging is as follows: receiving products, braiding the braided products according to the number of packages, foaming cotton strips and protecting strips according to the standard requirements, checking warehouse entry orders and labels by operators, checking and tracing small labels and labeling reel labels by operators, setting vacuum packaging parameters, loading into packaging boxes, labeling according to the standard requirements, checking whether related accessories are complete or not, and packaging and warehouse entry.
As shown in fig. 3, fig. 4, fig. 5 and fig. 6, the eHSOP L package of the high-power driving circuit produced by the above production method of the present invention has a thickness of 1.60 mm ±0.05 mm, and comprises a first chip 10, a second chip 11 and a lead frame unit 5 according to claim 1, wherein the first chip 10 is adhered to a chip mounting area of a base island 6 by using high silver conductive adhesive, the second chip 11 is adhered to a surface of the first chip 10 by using DAF film stack, pads on the surfaces of the first chip 10 and the second chip 11 are connected with corresponding inner pins and base islands 6 by wire bonding wires, the first chip 10, the second chip 11 and the base islands 6 are all molded in a plastic package body 12, an outer part of two heat sinks 16 is arranged on the plastic package body 12, a lower row is provided with a fifth outer pin with a fifth outer stand-alone outer pin of 1.24 mm and a fifth outer pin of 5mm and a fifth outer pin of 1.24 mm and a fifth outer pin of 5mm, respectively, and a first inner pin 18 and a second inner pin 19 and a third inner pin 20 are arranged on the lower row; the first chip 10 is connected with the second chip 11 through a first bonding wire X1, and the second chip 11 is connected with the fourth inner pin 21 through a third bonding wire X3; the first chip 10 is connected with the first inner lead 18 through a second bonding wire X2, and the first chip 10 is connected with the base island 6 through a fourth bonding wire X4; the plastic package body 12 is provided with a first pin mark 17.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. The eHSOP L lead frame of the high-power driving circuit comprises a lead frame body, wherein a plurality of lead frame unit groups which are arranged in an array mode are arranged on the lead frame body, and the lead frame is characterized in that: each transverse lead frame unit group (2) consists of a first lead frame part (3) and a second lead frame part (4), the first lead frame part (3) and the second lead frame part (4) are respectively composed of two lead frame units (5), outer pins of two adjacent lead frame units (5) are arranged in a staggered mode, a process groove (7) is arranged between the first lead frame part (3) and the second lead frame part (4), a first stress release groove (8) is arranged between the two adjacent lead frame unit groups (2), a base island (6) is arranged on the lead frame units (5), five inner pins with T-shaped heads and rectangular tails and connected with the lead frame body (1) are arranged at the upper ends of the base island (6), the inner pins are sequentially a first inner pin (18), a second inner pin (19), a third inner pin (20), a fourth inner pin (21) and a fifth inner pin (22), two heat dissipation fins (16) with the same width are arranged at the lower ends of the base island (6), two heat dissipation fins (16) are arranged between the two heat dissipation fins (16) and are connected with one end of each base island (16) in a pi-shaped manner, a connection hole (9) is arranged between the two heat dissipation fins (16), two sides of the base island (6) are respectively provided with two double connecting rods (B), and the double connecting rods (B) are connected with the lead frame body (1); the tops of the first lead frame part (3) and the second lead frame part (4) are respectively provided with a round frame anti-reflection hole (14) and an oval frame anti-reflection hole (15); the lead frame has a length of 249.60mm plus or minus 0.10 mm, a width of 79.50 mm plus or minus 0.05mm and a thickness of 0.19mm-0.21mm, and comprises 120 lead frame units (5) which are arranged in 6 rows and 20 columns.
2. A method of manufacturing eHSOP L packages for high power driver circuits, comprising the steps of:
a. Wafer thinning
Thinning by a thinning machine, wherein the final thickness of the wafer is as follows: the thickness of the first chip is 100-120 mu m, and the thickness of the second chip is 200-300 mu m; the rough grinding speed is less than or equal to 35 mu m/min; the precision speed is less than or equal to 10 mu m/min, stress is eliminated, the film is cleaned, and a thinning adhesive film is stuck on the back surface;
b. scribing
Scribing by using a double-scribing-blade scribing machine, wherein the first cutter firstly scribes 30% of the thickness setting and takes a groove, the second cutter scribes 70% of the thickness setting, the scribing feeding speed is controlled to be less than or equal to 10mm/s, and the cleaning and drying are timely carried out;
c. Upper core
After the eHSOP L lead frame of the high-power driving circuit according to claim 1 is used for automatic feeding, the chip is packaged in a lamination manner through a process of twice feeding, and the method specifically comprises the following steps:
Core loading for the first time: the first chip (10) is adhered to the lead frame by the core loading machine, and the first chip (10) is adhered to the chip mounting area of the base island (6) by using the environment-friendly high-silver conductive adhesive through a chip suction nozzle and a dispensing head with the diameter of 2mm multiplied by 2 mm;
And (3) primary core loading baking: the whole lead frame stuck with the first chip (10) is sent to a transfer box and is transferred to an oven, and the oven is baked by adopting a layering-preventing sectional baking process;
And (5) core loading for the second time: using equipment with a glue film core-loading function, fixing a wafer of a second chip (11) with a DAF film attached to the back surface before dicing, automatically feeding the equipment, then feeding a semi-finished lead frame attached with a first chip (10) to a die bonding table, heating a substrate to 120 ℃, adsorbing the second chip (11) with the DAF film, and placing the second chip on the front surface of the first chip (10);
And (5) secondary core loading baking: after all lead frames of the second chips (11) are pasted, the lead frames are sent to a transfer box and are transferred to an oven, and baking is carried out in the oven by adopting a layering-preventing sectional baking process;
d. Pressure welding
Bonding a metal wire or copper wire by pressure welding to realize a low-radian control technology, adopting a combination of flat arc and forward and reverse striking, and a high-grade wire arc shape of a sharp corner and a high-grade wire arc shape of a flat corner, controlling the arc height to be less than or equal to 150 mu m, and bonding a first chip and a second chip with an inner pin, a first chip and an inner pin, and an upper chip and a base island by using a welding wire;
e. plastic package and post-curing
An environment-friendly plastic package material is selected, and an ultrathin warp-preventing and delamination-reducing process is adopted to reduce the wire punching rate, reduce the back-packaging or the back-packaging, and reduce the curing time by 10-30 s compared with the normal curing time; when in post-curing, the semi-finished product bar of the lead frame of the IC packaging part is aged for 5 hours in a baking oven at 175 ℃, so that the warp degree of the plastic packaging body meets the requirements of printing, stamping and forming packaging processes, and the overflow of the cooling fin is ensured not to exceed 10% of the area of the cooling fin;
f. Electroplating
The automatic plating wire is adopted to carry out a tin plating process on the packaging piece and the copper alloy plating lead which leaks outside, so that the surface of the connecting pin is plated with soldering tin, and the thickness of the plating layer is 11.43+/-3.81 mu m;
g. Printing
The fixture type fixing, double laser heads, continuous feeding, positioning and printing modes are adopted to mark the surface of the plastic package;
h. Cutting ribs, forming and separating
Cutting off the double connecting rods connected to the lead frame by adopting a special rib cutting die, wherein the gap between the rib cutting tool and the plastic package body is more than 0.075mm, and meanwhile, plastic package residues on the surface of the die are cleaned, so that the rubber body is prevented from being padded;
i. Testing and packaging
The special tester and the sorting machine are adopted to test the appearance and the functional parameters, so that the products provided by customers can be used on the machine, and the use requirements of the packaging piece are met; packaging and warehousing to prepare eHSOP L packaging parts of the high-power driving circuit;
The thickness range of rough grinding in the step a is from 550-800 mu m of the original wafer to 120 mu m of the adhesive film, to 120 mu m of the final thickness to 120 mu m of the adhesive film and 50 mu m of the adhesive film, and the thickness range of precision is from 120 mu m of the final thickness to 120 mu m of the adhesive film and 50 mu m of the adhesive film, to 150 mu m of the wafer and 120 mu m of the adhesive film, and the chip warping prevention process is adopted.
3. A eHSOP L package for high power driver circuits produced by the method of claim 2, wherein: the high-silver conductive adhesive is adhered to a chip mounting area of a base island (6) by the first chip (10), the second chip (11) is adhered to the surface of the first chip (10) by using a DAF film stack, bonding pads on the surface of the first chip (10) and the second chip (11) are connected with corresponding inner pins and the base island (6) through lead bonding wires, the first chip (10), the second chip (11) and the base island (6) are respectively and plastically packaged in a plastic package body (12), exposed parts of two radiating fins (16) are arranged on the plastic package body (12), five independent outer pins with the spacing of 1.70mm, namely a first outer pin (23), a third outer pin (24), a fifth outer pin (26) and a fifth outer pin (26) are arranged on the lower row, and the five independent outer pins with the spacing of 1.70mm are respectively and plastically packaged into a first outer pin (23), a third outer pin (24) and a fifth outer pin (26) and a fifth outer pin (0.0 mm) are arranged on the lower row; a first pin mark (17) is arranged on the plastic package body (12); the thickness of the package was 1.60 mm ±0.05 mm.
4. A eHSOP L package for a high-power driver circuit as defined in claim 3, wherein: the first chip (10) is connected with the second chip (11) through a first bonding wire (X1), and the second chip (11) is connected with the fourth inner pin (21) through a third bonding wire (X3); the first chip (10) is connected with the first inner pin (18) through a second bonding wire (X2), and the first chip (10) is connected with the base island (6) through a fourth bonding wire (X4).
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