CN110672995B - Power cable oscillatory wave partial discharge detection circuit and detection method thereof - Google Patents

Abstract

The present invention provides a power cable oscillation wave partial discharge detection circuit and a detection method thereof, comprising a pulse generating circuit, a pulse transformer, a plurality of IGBT trigger circuits, an IGBT, a voltage equalizing circuit, a detection circuit and a cable to be tested, wherein the output end of the pulse generating circuit is electrically connected to the primary side of the pulse transformer, the secondary side of the pulse transformer is electrically connected to the input end of each IGBT trigger circuit respectively, the output end of the IGBT trigger circuit is electrically connected to the gate of the IGBT, a voltage equalizing circuit is connected in parallel between the drain and source of each IGBT; the drain and source of adjacent IGBTs are connected in series; a detection circuit and a cable to be tested are connected in parallel between the drain of the head end IGBT and the source of the end IGBT connected in series. The pulse generating circuit of the present invention generates a pulse signal to drive the pulse transformer to transfer energy, the IGBT applies a test voltage to the cable to be tested; after the IGBT is turned off, the measuring circuit measures the discharge signal of the cable to be tested.

Description

A power cable oscillating wave partial discharge detection circuit and detection method thereof

Technical Field

The present invention relates to the field of electric power equipment, and in particular to a power cable oscillation wave partial discharge detection circuit and a detection method thereof.

Background Art

The power industry is a basic industry, and the failure of power cables will bring huge losses to power companies and power users. With the continuous transformation of my country's urban power grid, XLPE power cables have been widely used due to their corrosion resistance and high strength. However, after a period of operation, they are prone to operating failures. The main reasons are the dendritic aging and breakdown of the cable body insulation and the discharge caused by moisture in the accessories.

The local discharge source inside the insulation system of the power cable can be regarded as a point pulse signal source. The discharge will generate electromagnetic waves, which propagate along the cable and can be detected. The non-destructive testing of power cables usually adopts the DC excitation oscillating wave voltage withstand test (OWTS). The cable to be tested is charged through a series inductor to reach a preset voltage, and then the switch is quickly turned on to perform AC discharge, so that the cable to be tested and the inductor resonate in series, thereby stimulating the local discharge signal at the defect of the cable for detection, which can avoid the damage of the cable by traditional detection methods. However, the commonly used switches are not suitable for the high-speed action requirements of oscillating switches. IGBT (insulated gate bipolar transistor) has become the preferred device for high-voltage switches because of its advantages such as fast turn-on speed and low driving power. The IGBT itself has limited withstand voltage and needs to be used in series under high voltage conditions. If the trigger signals of each IGBT are inconsistent, the opening and closing time of each device will be asynchronous, resulting in unbalanced voltages on the IGBTs at each level in series, which is easy to damage the IGBT.

Summary of the invention

In view of this, the present invention proposes a power cable oscillation wave partial discharge detection circuit and a detection method thereof with balanced voltage of multi-stage IGBT series connection and consistent trigger signals.

The technical solution of the present invention is achieved in this way:

On the one hand, the present invention provides a power cable oscillation wave partial discharge detection circuit, comprising a pulse generating circuit (1), a pulse transformer (2), a plurality of IGBT trigger circuits (3), an IGBT, a voltage equalizing circuit (4), a detection circuit (5) and a cable to be tested (6), wherein the output end of the pulse generating circuit (1) is electrically connected to the primary side of the pulse transformer (2), the secondary side of the pulse transformer (2) is electrically connected to the input end of each IGBT trigger circuit (3), the output end of the IGBT trigger circuit (3) is electrically connected to the gate of the IGBT, the voltage equalizing circuit (4) is connected in parallel between the drain and source of each IGBT; the drain and source of adjacent IGBTs are connected in series; the detection circuit (5) and the cable to be tested (6) are connected in parallel between the drain of the head end IGBT and the source of the end IGBT connected in series;

The pulse generating circuit (1) outputs a pulse signal with an adjustable duty cycle, and the pulse signal is input into the IGBT trigger circuit (3) on the secondary side of the pulse transformer (2) after being stepped up by the pulse transformer (2);

The IGBT trigger circuit (3) receives the boosted pulse signal and inputs the pulse signal into the gate of the IGBT to maintain the on state of the IGBT or turn off the IGBT. Each IGBT in the on state performs direct current charging on the cable to be tested (6);

The voltage balancing circuit (4) reduces the gate voltage change rate of the IGBT to synchronize the drive signals of each IGBT;

After the IGBT of the detection circuit (5) is turned off, the cable to be tested (6) and the detection circuit (5) are in series resonance, and the detection circuit (5) detects a discharge signal of the cable to be tested (6).

On the basis of the above technical solution, preferably, the pulse generating circuit (1) includes a pulse high-voltage power supply, a first transistor Q1, a second transistor Q2 and a third transistor Q3, the pulse signal output by the pulse high-voltage power supply is input into the gate of the first transistor Q1, the collector of the first transistor Q1 is electrically connected to the base of the second transistor Q2, the collector of the second transistor Q2 is electrically connected to the gate of the third transistor Q3, and the emitter and collector of the third transistor Q3 are electrically connected to the primary side of the pulse transformer (2), respectively.

Further preferably, a D flip-flop, an AND gate and a PMW signal generating circuit are arranged between the second transistor Q2 and the third transistor Q3; the collector of the second transistor Q2 is electrically connected to the D port of the D flip-flop, the input end of the PMW signal generating circuit is electrically connected to the CP port of the D flip-flop and the first input end of the AND gate respectively, the output end of the D flip-flop is electrically connected to the second input end of the AND gate; the output end of the AND gate is electrically connected to the gate of the third transistor Q3.

Further preferably, the PMW signal generating circuit includes a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4 and a NAND gate; the inverting input terminal of the first operational amplifier U1 is electrically connected to the +2V excitation voltage, and the non-inverting input terminal of the first operational amplifier U1 is electrically connected to the +3.3V voltage; the output terminal of the first operational amplifier U1 is electrically connected to the non-inverting input terminal of the second operational amplifier U2, and the non-inverting input terminals of the third operational amplifier U3 and the fourth operational amplifier U4 are electrically connected to the +3.3V voltage. The inverting input terminal of the fourth operational amplifier U4 is electrically connected to the output terminal of the third operational amplifier U3 and the output terminal of the fourth operational amplifier U4 respectively; the output terminal of the fourth operational amplifier U4 is also electrically connected to the inverting input terminal of the third operational amplifier U3; the third operational amplifier U3 is electrically connected to the inverting input terminal of the second operational amplifier U2; the output terminal of the second operational amplifier U2 is electrically connected to the first input terminal of the NAND gate, the second input terminal of the NAND gate is grounded, and the output terminal of the NAND gate is electrically connected to the CP port of the D flip-flop and the first input terminal of the AND gate respectively.

On the basis of the above technical solution, preferably, the IGBT trigger circuit (3) includes a rectifier bridge and an RC parallel discharge unit, the first input terminal and the second input terminal of the rectifier bridge are electrically connected to the secondary side of the pulse transformer (2) respectively, and the RC parallel discharge unit is connected in parallel with the first output terminal and the second output terminal of the rectifier bridge; the source and drain of adjacent IGBTs are connected in series.

Further preferably, the RC parallel discharge unit includes a capacitor C5, a resistor R15 and a resistor R16, and the two ends of the capacitor C5 and the resistor R16 are respectively connected in parallel between the first output end and the second output end of the rectifier bridge; the two ends of the resistor R15 are connected in parallel between the connection point of the capacitor C5 and the resistor R16 and the first output end of the rectifier bridge.

Further preferably, the voltage equalizing circuit (4) comprises a voltage stabilizing diode D1, a resistor R17, a resistor R18 and a capacitor C6, wherein the resistor R17 is respectively connected between the source and drain of the IGBT, and the resistor R18 and the capacitor C6 are connected in series and in parallel with the two ends of the resistor R17; the voltage stabilizing diode D1 is connected in reverse parallel between the first output end and the second output end of the rectifier bridge, the gate of the IGBT is also connected in parallel with the cathode of the voltage stabilizing diode D1, and the source of the IGBT is connected in parallel with the anode of the voltage stabilizing diode D1.

On the basis of the above technical solution, preferably, the detection circuit (5) includes an inductor L1, a high-voltage voltage divider, a coupling capacitor C8 and a detection impedance R21, one end of the inductor L1 is electrically connected to the drain of the first-end IGBT connected in series, one end of the high-voltage voltage divider, one end of the resistor R21 and one end of the cable to be tested (6) are all electrically connected to the other end of the inductor L1, and the high-voltage voltage divider is electrically connected to the source of the terminal IGBT connected in series; the coupling capacitor C8 is connected in series with the other end of the resistor R21 and then grounded, and the other end of the cable to be tested (6) is grounded.

Further preferably, the high-voltage voltage divider includes a resistor R19, a resistor R20 and a capacitor C7, the resistor R19 and the resistor R20 are connected in series and connected to the drain of the first-end IGBT and the source of the end IGBT connected in series, and the capacitor C7 is connected in parallel to both ends of the resistor R20.

On the other hand, the present invention also provides a detection method for a power cable oscillating wave partial discharge detection circuit, comprising the following steps:

S1: disconnecting both ends of the cable to be tested (6) from the power grid, and arranging a power cable oscillation wave partial discharge detection circuit, a partial discharge locator and an industrial computer at the detection site;

S2: A pulse signal is sent out by a pulse high voltage power supply, and the pulse generating circuit (1) performs signal conditioning on the pulse signal, and inputs the signal into the second input terminal of the AND gate via the D port of the D flip-flop, and the PMW square wave signal output by the PMW signal generating circuit is input into the CP port of the D flip-flop and the first input terminal of the AND gate, thereby generating a new pulse signal having the same rising edge as the PMW square wave, and inputting the new pulse signal into the third transistor Q3, and the third transistor Q3 amplifies the new pulse signal, thereby forming a high-frequency square wave signal on the primary side of the pulse transformer (2);

S3: Pulse transformer (2) forms a high-frequency square wave signal on the primary side and transmits it to the secondary side;

S4: Each IGBT trigger circuit (3) on the secondary side of the pulse transformer (2) shapes the high-frequency square wave signal, and the RC parallel discharge unit stores energy; the shaped square wave signal triggers the gate of the IGBT, and when the square wave signal disappears, the RC parallel discharge unit discharges to maintain the continuous conduction of the IGBT and delays the shutdown; the voltage-stabilizing diode D1 in the voltage-equalizing circuit (4) limits the gate trigger voltage, so that each IGBT is triggered synchronously; the resistor R17 realizes the voltage-equalizing function, so that the voltage between the source and drain of the IGBT changes smoothly to realize dynamic voltage equalization; detection is carried out under no-load conditions to measure the background signal;

S5: Connecting the cable (6) to be tested, when each IGBT connected in series is turned on, the cable (6) to be tested is charged after being divided by the inductor L1 and the high-voltage divider, when charging is completed and the IGBT is turned off, the cable (6) to be tested is discharged outwardly, the coupling capacitor C8 couples the partial discharge of the cable (6) to the capacitor, and forms a detection loop with the resistor R21, and forms a pulse current in the loop, the pulse current is drawn from the measuring point between the capacitor C8 and the resistor R21, the measuring point is connected to the partial discharge locator and the industrial computer, and the measurement is performed;

S6: After obtaining the measurement results, the normal connection between the cable to be tested (6) and the power grid is restored.

The power cable oscillating wave partial discharge detection circuit and detection method provided by the present invention have the following beneficial effects compared with the prior art:

(1) The pulse generating circuit of the present invention generates a pulse signal to drive the pulse transformer to transfer energy, intermittently trigger and turn off the IGBT, so that the IGBT applies a test voltage to the cable under test; after the IGBT is turned off, the measuring circuit measures the discharge signal of the cable under test, thereby realizing the detection of partial discharge of the cable under test;

(2) The pulse generating circuit emits an adjustable pulse signal; with the assistance of the D flip-flop and the PMW signal generating circuit, the frequency of the pulse signal can be changed to better realize the oscillation process;

(3) The IGBT trigger circuit provides the gate trigger voltage of the IGBT on the one hand, and stores energy on the other hand to extend its turn-on time;

(4) The voltage balancing circuit can limit the gate voltage of the IGBT to prevent it from being turned on improperly. It can also balance the voltage between the source and drain of each level of the IGBT in series to prevent the IGBT from being damaged by overvoltage.

(5) The detection circuit detects the instantaneous pulse signal generated by partial discharge of the cable under test for further analysis.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a system structure block diagram of a power cable oscillating wave partial discharge detection circuit and a detection method thereof according to the present invention;

FIG2 is a wiring diagram of a pulse generating circuit of a power cable oscillating wave partial discharge detection circuit and a detection method thereof according to the present invention;

3 is a wiring diagram of a PMW signal generating circuit in a pulse generating circuit of a power cable oscillating wave partial discharge detection circuit and a detection method thereof according to the present invention;

4 is a wiring diagram of an IGBT trigger circuit, an IGBT and a voltage balancing circuit of a power cable oscillation wave partial discharge detection circuit and a detection method thereof according to the present invention;

FIG. 5 is a wiring diagram of a detection circuit of a power cable oscillating wave partial discharge detection circuit and a detection method thereof according to the present invention.

DETAILED DESCRIPTION

The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

As shown in FIG1 , the present invention provides a power cable oscillation wave partial discharge detection circuit, comprising a pulse generating circuit 1, a pulse transformer 2, a plurality of IGBT trigger circuits 3, an IGBT, a voltage equalizing circuit 4, a detection circuit 5 and a cable to be tested 6, wherein the output end of the pulse generating circuit 1 is electrically connected to the primary side of the pulse transformer 2, the secondary side of the pulse transformer 2 is electrically connected to the input end of each IGBT trigger circuit 3 respectively, the output end of the IGBT trigger circuit 3 is electrically connected to the gate of the IGBT, the voltage equalizing circuit 4 is connected in parallel between the drain and source of each IGBT; the drain and source of adjacent IGBTs are connected in series; the detection circuit 5 and the cable to be tested 6 are connected in parallel between the drain of the head end IGBT and the source of the end IGBT connected in series;

The pulse generating circuit 1 outputs a pulse signal with an adjustable duty cycle, and the pulse signal is boosted by the pulse transformer 2 and input into the IGBT trigger circuit 3 on the secondary side of the pulse transformer 2;

The IGBT trigger circuit 3 receives the boosted pulse signal and inputs the pulse signal into the gate of the IGBT to maintain the on state of the IGBT or turn off the IGBT. Each IGBT in the on state performs DC charging on the cable 6 to be tested.

The voltage balancing circuit 4 reduces the gate voltage change rate of the IGBT to synchronize the drive signals of each IGBT;

After the IGBT of the detection circuit 5 is turned off, the cable 6 to be tested and the detection circuit 5 are in series resonance, and the detection circuit 5 detects the discharge signal of the cable 6 to be tested.

The pulse generating circuit 1 of the present invention serves as a signal excitation source to emit a pulse signal, the power of which is amplified by the pulse transformer 2 and output to each IGBT trigger circuit 3, so that the IGBT is continuously turned on and off. The pulse signal emitted by the pulse generating circuit 1 can be realized by a common pulse high-voltage power supply product on the market.

As shown in FIG2 , the pulse generating circuit 1 of the present invention includes a pulse high-voltage power supply, a first transistor Q1, a second transistor Q2 and a third transistor Q3. The pulse signal output by the pulse high-voltage power supply is input to the gate of the first transistor Q1. The collector of the first transistor Q1 is electrically connected to the base of the second transistor Q2. The collector of the second transistor Q2 is electrically connected to the gate of the third transistor Q3. The emitter and collector of the third transistor Q3 are electrically connected to the primary side of the pulse transformer 2, respectively. The first transistor Q1 and the second transistor Q2 can condition the pulse signal emitted by the pulse high-voltage power supply, and then amplify it through the third transistor Q3 and input it to the primary side of the pulse transformer 2, and the pulse transformer 2 performs a boost output.

As shown in FIG1 and FIG2, a D flip-flop, an AND gate and a PMW signal generating circuit are arranged between the second transistor Q2 and the third transistor Q3; the collector of the second transistor Q2 is electrically connected to the D port of the D flip-flop, the input end of the PMW signal generating circuit is electrically connected to the CP port of the D flip-flop and the first input end of the AND gate respectively, the output end of the D flip-flop is electrically connected to the second input end of the AND gate; the output end of the AND gate is electrically connected to the gate of the third transistor Q3. The PMW signal generating circuit sends out a high-frequency square wave signal, which is input into the D flip-flop and the AND gate respectively, so that the pulse signal output by the pulse high-voltage power supply is further mixed with the high-frequency square wave signal, and the PMW signal generating circuit can adjust the duty cycle of the high-frequency square wave signal, and can further change the frequency of the pulse signal.

Specifically, the output end of the pulse high-voltage power supply is electrically connected to one end of the resistor R1, and the other end of the resistor R1 is electrically connected to one end of the resistor R2, one end of the resistor R3 and the base of the first transistor Q1 respectively; the emitter of the first transistor Q1 is connected in parallel with the other end of the resistor R3 and then grounded; the other end of the resistor R2 is connected in parallel with the collector of the first transistor Q1 and then electrically connected to one end of the resistor R4; the other end of the resistor R4 is electrically connected to the base of the second transistor Q2; the emitter of the second transistor Q2 is electrically connected to the +12V power supply, and the collector of the second transistor Q2 is electrically connected to one end of the resistor R5. The end is electrically connected to the D port of the D flip-flop; the other end of the resistor R5 is grounded; the output end of the D flip-flop is electrically connected to the second input end of the AND gate; the input end of the PMW signal generating circuit is electrically connected to the CP port of the D flip-flop and the first input end of the AND gate respectively; the output end of the AND gate is electrically connected to one end of the resistor R6, and the other end of the resistor R6 is electrically connected to the base of the third transistor Q3; the collector and emitter of the third transistor Q3 are connected in parallel with the two ends of the capacitor C1 and the primary side of the pulse transformer 2; the collector of the third transistor Q3 is also electrically connected to the +12V power supply through the resistor R7.

As shown in FIG3 , the PMW signal generating circuit includes a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4 and a NAND gate; the inverting input terminal of the first operational amplifier U1 is electrically connected to the +2V excitation voltage, and the non-inverting input terminal of the first operational amplifier U1 is electrically connected to the +3.3V voltage; the output terminal of the first operational amplifier U1 is electrically connected to the non-inverting input terminal of the second operational amplifier U2, and the non-inverting input terminals of the third operational amplifier U3 and the fourth operational amplifier U4 are electrically connected to the +3.3V voltage. The inverting input terminal of the fourth operational amplifier U4 is electrically connected to the output terminal of the third operational amplifier U3 and the output terminal of the fourth operational amplifier U4 respectively; the output terminal of the fourth operational amplifier U4 is also electrically connected to the inverting input terminal of the third operational amplifier U3; the third operational amplifier U3 is electrically connected to the inverting input terminal of the second operational amplifier U2; the output terminal of the second operational amplifier U2 is electrically connected to the first input terminal of the NAND gate, the second input terminal of the NAND gate is grounded, and the output terminal of the NAND gate is electrically connected to the CP port of the D flip-flop and the first input terminal of the AND gate respectively.

Among them, the non-inverting input terminal of the first operational amplifier U1 is connected in parallel with a filter circuit composed of a resistor R9 and a capacitor C2 in parallel, and the non-inverting input terminal of the first operational amplifier U1 is also electrically connected to a +3.3V power supply through a capacitor R8; the inverting input terminal of the first operational amplifier U1 is electrically connected to one end of a resistor R10, one end of a capacitor C3 and one end of a resistor R11 respectively; the other end of the resistor R10 is electrically connected to a +2V power supply; the other end of the capacitor C3 is electrically connected to the output terminal of the first operational amplifier U1; the other end of the resistor R11 is electrically connected to the output terminal of the second operational amplifier U2; the output terminal of the first operational amplifier U1 is electrically connected to the non-inverting input terminal of the second operational amplifier U2; the first operational amplifier U1 and its peripheral components together constitute an error amplifier, the +2V power supply is used as an excitation signal input to the first operational amplifier U1, and the +3.3V power supply is used as a reference voltage input to the first operational amplifier U1. The non-inverting input terminal of the third operational amplifier U3 is electrically connected to the +3.3V power supply; the inverting input terminal of the third operational amplifier U3 is electrically connected to one end of the resistor R12 and one end of the capacitor C4, respectively, and the other end of the resistor R12 is electrically connected to the output terminal of the fourth operational amplifier U4 and one end of the resistor R13, respectively; the non-inverting input terminal of the fourth operational amplifier U4 is electrically connected to the +3.3V power supply; the inverting input terminal of the fourth operational amplifier U4 is electrically connected to the other end of the resistor R13, and a resistor R14 is also connected in parallel between the output terminal of the third operational amplifier U3 and the inverting input terminal of the fourth operational amplifier U4. The output terminal of the third operational amplifier U3 is electrically connected to the inverting input terminal of the second operational amplifier U2. The output terminal of the second operational amplifier U2 is electrically connected to the first input terminal of the NAND gate, and the second input terminal of the NAND gate is grounded. The third operational amplifier U3 and the fourth operational amplifier U4 form a triangle wave generator, and the second operational amplifier U2 outputs a square wave signal with an adjustable duty cycle, and the duty cycle is adjusted by the input control of the inverting input terminal of the first operational amplifier U1. In the present invention, the first operational amplifier U1 and the third operational amplifier U3 use OPA2365, which is a single-power operational amplifier and uses a +5V single power supply. The first operational amplifier U1 and the third operational amplifier U3 can be integrated into a chip, which can reduce the size of the chip. The second operational amplifier U2 and the third operational amplifier U3 can use TLV3502 comparator, which is also powered by a +5V single power supply. The second operational amplifier U2 and the third operational amplifier U3 can be integrated in the same TLV3502 to further reduce the size of the chip.

As shown in FIG4 , the IGBT trigger circuit 3 includes a rectifier bridge and an RC parallel discharge unit. The first input terminal and the second input terminal of the rectifier bridge are electrically connected to the secondary side of the pulse transformer 2 respectively. The RC parallel discharge unit is connected in parallel with the first output terminal and the second output terminal of the rectifier bridge. The source and drain of adjacent IGBTs are connected in series. The rectifier bridge can process the boosted pulse signal to obtain a pulsating DC voltage, which is sent to the subsequent RC parallel discharge unit and IGBT. The components of each IGBT trigger circuit 3 are preferably the same model products from the same manufacturer and the same batch, and their performance is relatively close.

The RC parallel discharge unit includes a capacitor C5, a resistor R15 and a resistor R16, and the two ends of the capacitor C5 and the resistor R16 are respectively connected in parallel between the first output end and the second output end of the rectifier bridge; the two ends of the resistor R15 are connected in parallel between the connection point between the capacitor C5 and the resistor R16 and the first output end of the rectifier bridge. The RC parallel discharge unit can continue to discharge after the pulse transformer 2 is powered off to maintain the conduction of the IGBT. Because a certain amount of energy is required to turn on the IGBT gate, but the energy required to maintain the conduction of the IGBT is relatively small, the RC parallel discharge unit can form a discharge circuit to achieve continuous conduction of the IGBT until the discharge process ends.

As shown in FIG4 , the voltage balancing circuit 4 includes a voltage stabilizing diode D1, a resistor R17, a resistor R18 and a capacitor C6. The resistor R17 is respectively connected between the source and drain of the IGBT, and the resistor R18 and the capacitor C6 are connected in series and in parallel with the two ends of the resistor R17. The voltage stabilizing diode D1 is connected in reverse parallel between the first output end and the second output end of the rectifier bridge, the gate of the IGBT is also connected in parallel with the cathode of the voltage stabilizing diode D1, and the source of the IGBT is connected in parallel with the anode of the voltage stabilizing diode D1. The voltage balancing circuit 4 can buffer the change of the circuit voltage to achieve the effect of voltage balancing change.

As shown in Figure 5, the detection circuit 5 includes an inductor L1, a high-voltage voltage divider, a coupling capacitor C8 and a detection impedance R21. One end of the inductor L1 is electrically connected to the drain of the first-end IGBT connected in series, one end of the high-voltage voltage divider, one end of the resistor R21 and one end of the cable to be tested 6 are all electrically connected to the other end of the inductor L1, and the high-voltage voltage divider is electrically connected to the source of the terminal IGBT connected in series; the coupling capacitor C8 is connected in series with the other end of the resistor R21 and then grounded, and the other end of the cable to be tested 6 is grounded.

The high voltage divider includes a resistor R19, a resistor R20 and a capacitor C7. The resistor R19 and the resistor R20 are connected in series and connected to the drain of the first-end IGBT and the source of the terminal IGBT connected in series. The capacitor C7 is connected in parallel to both ends of the resistor R20.

The present invention provides a detection method for a power cable oscillating wave partial discharge detection circuit, comprising the following steps:

S1: disconnect both ends of the cable 6 to be tested from the power grid, and arrange a power cable oscillation wave partial discharge detection circuit, a partial discharge locator and an industrial computer at the testing site;

S2: A pulse signal is sent out by a pulse high voltage power supply, and the pulse generating circuit 1 performs signal conditioning on the pulse signal, and inputs the signal into the second input terminal of the AND gate through the D port of the D flip-flop, and the PMW square wave signal output by the PMW signal generating circuit is input into the CP port of the D flip-flop and the first input terminal of the AND gate, and a new pulse signal identical to the rising edge of the PMW square wave is generated and input into the third transistor Q3, and the third transistor Q3 amplifies the new pulse signal and forms a high-frequency square wave signal on the primary side of the pulse transformer 2;

S3: Pulse transformer 2 forms a high-frequency square wave signal on the primary side and transmits it to the secondary side;

S4: Each IGBT trigger circuit 3 on the secondary side of the pulse transformer 2 shapes the high-frequency square wave signal, and the RC parallel discharge unit stores energy; the shaped square wave signal triggers the gate of the IGBT, and when the square wave signal disappears, the RC parallel discharge unit discharges to maintain the continuous conduction of the IGBT and delays the shutdown; the voltage-stabilizing diode D1 in the voltage-equalizing circuit 4 limits the gate trigger voltage, so that each IGBT is triggered synchronously; the resistor R17 realizes the voltage-equalizing function, so that the voltage between the source and drain of the IGBT changes smoothly to realize dynamic voltage-equalizing; detection is performed under no-load conditions to measure the background signal;

S5: Connect the cable 6 to be tested. When the IGBTs in series are turned on, they charge the cable 6 to be tested after being divided by the inductor L1 and the high-voltage divider. When the charging is completed and the IGBT is turned off, the cable 6 to be tested discharges outwards. The coupling capacitor C8 couples the partial discharge of the cable 6 to the capacitor, and forms a detection loop with the resistor R21, and forms a pulse current in the loop. The pulse current is drawn from the measuring point between the capacitor C8 and the resistor R21. The measuring point is connected to the partial discharge locator and the industrial computer for measurement.

S6: After obtaining the measurement results, the normal connection between the cable 6 to be tested and the power grid is restored.

In the above detection method, the partial discharge locator can be a 560-type partial discharge locator from Swiss HAEFELY Company. The industrial computer can be a PC. The partial discharge locator uses an offline method based on the time domain reflection method commonly used in the field. When partial discharge occurs, the partial discharge pulse signal will propagate along the cable 6 to be tested from two opposite directions. There will be a time difference between the two pulses reaching the test end of the partial discharge locator. Since the cable material and length are basically determined, the location of the partial discharge can be calculated by the time difference, thereby determining the location of the partial discharge part.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims (5)

1. The utility model provides a power cable oscillatory wave partial discharge detection circuit which characterized in that: the device comprises a pulse generating circuit (1), a pulse transformer (2), a plurality of IGBT trigger circuits (3), IGBTs, a voltage equalizing circuit (4), a detection circuit (5) and a cable (6) to be tested, wherein the output end of the pulse generating circuit (1) is electrically connected with the primary side of the pulse transformer (2), the secondary side of the pulse transformer (2) is respectively electrically connected with the input end of each IGBT trigger circuit (3), the output end of each IGBT trigger circuit (3) is electrically connected with the gate electrode of each IGBT, and the voltage equalizing circuit (4) is connected in parallel between the drain electrode and the source electrode of each IGBT; the drain electrode and the source electrode of the adjacent IGBT are connected in series; a detection circuit (5) and a cable (6) to be detected are connected in parallel between the drain electrode of the head-end IGBT and the source electrode of the tail-end IGBT which are connected in series;

The pulse generating circuit (1) outputs a pulse signal with an adjustable duty ratio, and the pulse signal is boosted by the pulse transformer (2) and then is input into the IGBT trigger circuit (3) on the secondary side of the pulse transformer (2);

The IGBT trigger circuit (3) receives the boosted pulse signal, inputs the pulse signal into the gate electrode of the IGBT, maintains the on-state of the IGBT or turns off the IGBT, and each IGBT in the on-state carries out direct current charging on the cable (6) to be tested;

the voltage equalizing circuit (4) reduces the gate voltage change rate of the IGBTs and synchronizes the driving signals of the IGBTs;

After the IGBT is turned off, the detection circuit (5) and the cable (6) to be detected and the detection circuit (5) are in series resonance, and the detection circuit (5) detects a discharge signal applied to the cable (6) to be detected;

The pulse generating circuit (1) comprises a pulse high-voltage power supply, a first triode Q1, a second triode Q2 and a third triode Q3, a pulse signal output by the pulse high-voltage power supply is input into the gate electrode of the first triode Q1, the collector electrode of the first triode Q1 is electrically connected with the base electrode of the second triode Q2, the collector electrode of the second triode Q2 is electrically connected with the gate electrode of the third triode Q3, and the emitter electrode and the collector electrode of the third triode Q3 are respectively electrically connected with the primary side of the pulse transformer (2);

A D trigger, an AND gate and a PMW signal generating circuit are arranged between the second triode Q2 and the third triode Q3; the collector of the second triode Q2 is electrically connected with the D port of the D trigger, the input end of the PMW signal generating circuit is respectively electrically connected with the CP port of the D trigger and the first input end of the AND gate, and the output end of the D trigger is electrically connected with the second input end of the AND gate; the output end of the AND gate is electrically connected with the gate electrode of the third triode Q3;

The PMW signal generating circuit comprises a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4 and a NAND gate; the inverting input end of the first operational amplifier U1 is electrically connected with +2V excitation voltage, and the non-inverting input end of the first operational amplifier U1 is electrically connected with +3.3V voltage; the output end of the first operational amplifier U1 is electrically connected with the non-inverting input end of the second operational amplifier U2, the non-inverting input ends of the third operational amplifier U3 and the fourth operational amplifier U4 are electrically connected with +3.3V voltage, and the inverting input end of the fourth operational amplifier U4 is electrically connected with the output end of the third operational amplifier U3 and the output end of the fourth operational amplifier U4 respectively; the output end of the fourth operational amplifier U4 is also electrically connected with the inverting input end of the third operational amplifier U3; the third operational amplifier U3 is electrically connected with the inverting input end of the second operational amplifier U2; the output end of the second operational amplifier U2 is electrically connected with the first input end of the NAND gate, the second input end of the NAND gate is grounded, and the output end of the NAND gate is electrically connected with the CP port of the D trigger and the first input end of the AND gate respectively;

The detection circuit (5) comprises an inductor L1, a high-voltage divider, a coupling capacitor C8 and a detection impedance R21, one end of the inductor L1 is electrically connected with the drain electrode of the head-end IGBT which is mutually connected in series, one end of the high-voltage divider, one end of the resistor R21 and one end of the cable (6) to be detected are electrically connected with the other end of the inductor L1, and the high-voltage divider is electrically connected with the source electrode of the tail-end IGBT which is mutually connected in series; the coupling capacitor C8 is connected with the other end of the resistor R21 in series and then grounded, and the other end of the cable (6) to be tested is grounded;

The high-voltage divider comprises a resistor R19, a resistor R20 and a capacitor C7, wherein the resistor R19 and the resistor R20 are connected in series and then connected to the drain electrode of the head IGBT and the source electrode of the tail IGBT which are connected in series, and the capacitor C7 is connected to the two ends of the resistor R20 in parallel.

2. A power cable oscillatory wave partial discharge detection circuit as claimed in claim 1, wherein: the IGBT trigger circuit (3) comprises a rectifier bridge and an RC parallel discharge unit, wherein a first input end and a second input end of the rectifier bridge are respectively and electrically connected with the secondary side of the pulse transformer (2), and the RC parallel discharge unit is connected with a first output end and a second output end of the rectifier bridge in parallel; the sources and drains of adjacent IGBTs are connected in series with each other.

3. A power cable oscillatory wave partial discharge detection circuit as claimed in claim 2, wherein: the RC parallel discharging unit comprises a capacitor C5, a resistor R15 and a resistor R16, wherein two ends of the capacitor C5 and the resistor R16 are respectively connected in parallel between a first output end and a second output end of the rectifier bridge; the two ends of the resistor R15 are connected in parallel between the capacitor C5 and the connection point of the resistor R16 and the first output end of the rectifier bridge.

4. A power cable oscillatory wave partial discharge detection circuit as claimed in claim 2, wherein: the voltage equalizing circuit (4) comprises a voltage stabilizing diode D1, a resistor R17, a resistor R18 and a capacitor C6, wherein the resistor R17 is connected between the source electrode and the drain electrode of the IGBT respectively, and the resistor R18 and the capacitor C6 are connected in series and then connected with two ends of the resistor R17 in parallel; the voltage stabilizing diode D1 is reversely connected between the first output end and the second output end of the rectifier bridge in parallel, the gate electrode of the IGBT is also connected with the cathode of the voltage stabilizing diode D1 in parallel, and the source electrode of the IGBT is connected with the anode of the voltage stabilizing diode D1 in parallel.

5. The detection method of the power cable oscillatory wave partial discharge detection circuit as claimed in claim 4, wherein: the method comprises the following steps:

S1: separating two ends of a cable (6) to be tested from a power grid, and arranging a power cable oscillating wave partial discharge detection circuit, a partial discharge positioning instrument and an industrial personal computer on a detection site;

S2: pulse signals are sent out by a pulse high-voltage power supply, the pulse signals are subjected to signal conditioning by a pulse generating circuit (1), the pulse signals are input into a second input end of an AND gate through a D port of a D trigger, a PMW square wave signal output by the PMW signal generating circuit is input into a CP port of the D trigger and a first input end of the AND gate, a new pulse signal which is the same as the rising edge of the PMW square wave is generated, the new pulse signal is input into a third triode Q3, and after the new pulse signal is amplified by the third triode Q3, a high-frequency square wave signal is formed at the primary side of a pulse transformer (2);

S3: the pulse transformer (2) forms a high-frequency square wave signal on the primary side and transmits the high-frequency square wave signal to the secondary side;

S4: each IGBT trigger circuit (3) on the secondary side of the pulse transformer (2) shapes the high-frequency square wave signal, and the RC parallel discharge unit stores energy; triggering the gate electrode of the IGBT by the shaped square wave signal, and after the square wave signal disappears, discharging by the RC parallel discharging unit to maintain continuous conduction and delay turn-off of the IGBT; a voltage stabilizing diode D1 in the voltage equalizing circuit (4) limits gate trigger voltage so that each IGBT is triggered synchronously; the resistor R17 realizes a voltage equalizing function, so that the voltage between the source electrode and the drain electrode of the IGBT changes steadily to realize dynamic voltage equalizing; detecting under the no-load condition, and measuring a background signal;

S5: the method comprises the steps of connecting a cable (6) to be tested, charging the cable (6) to be tested after the voltage is divided by an inductor L1 and a high-voltage divider when each IGBT connected in series is conducted, discharging the cable (6) to be tested outwards when the charging is finished and the IGBT is turned off, coupling a partial discharge of the cable (6) to be tested to the capacitor C8 by a coupling capacitor C8, forming a detection loop with a resistor R21, forming a pulse current in the loop, leading out the pulse current from a measuring point between the capacitor C8 and the resistor R21, and connecting the measuring point with a partial discharge positioning instrument and an industrial personal computer for measuring;

s6: and after the measurement result is obtained, recovering the normal connection between the cable (6) to be measured and the power grid.