CN110676152A - Semiconductor process, manufacturing method of semiconductor device and semiconductor device - Google Patents
Semiconductor process, manufacturing method of semiconductor device and semiconductor device Download PDFInfo
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- CN110676152A CN110676152A CN201910775850.1A CN201910775850A CN110676152A CN 110676152 A CN110676152 A CN 110676152A CN 201910775850 A CN201910775850 A CN 201910775850A CN 110676152 A CN110676152 A CN 110676152A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 142
- 238000000034 method Methods 0.000 title claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 239000012530 fluid Substances 0.000 claims abstract description 4
- 238000001723 curing Methods 0.000 claims description 19
- 238000001029 thermal curing Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02697—Forming conducting materials on a substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Abstract
The application provides a semiconductor process, a manufacturing method of a semiconductor device and the semiconductor device. The semiconductor process comprises the following steps: forming a semiconductor substrate having a recess; arranging a predetermined material in the groove until the thickness of the predetermined material is greater than or equal to a predetermined thickness, wherein the predetermined material is a fluid material; controlling the semiconductor substrate to rotate, wherein the rotating shaft of the semiconductor substrate is parallel to the thickness direction of the semiconductor substrate; and curing the predetermined material to form the filling structure. The semiconductor process solves the problem that the groove with a larger depth-to-width ratio is difficult to fill seamlessly in the prior art, ensures that the performance of the formed filling structure is better, and further ensures that the performance of a semiconductor device formed by the semiconductor process is better. In addition, the process is easy to control, has low cost and can be widely applied to the manufacturing process of various semiconductor devices.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a semiconductor process, a method for manufacturing a semiconductor device, and a semiconductor device.
Background
In the prior art, in the semiconductor field, there are generally two ways for filling a groove with a large aspect ratio: the first is to deposit the predetermined material directly in the recess until the predetermined material fills the recess; the second method is to deposit a thinner preparation layer in the groove, then etch the part of the preparation layer near the groove opening to enlarge the groove opening, and finally deposit the predetermined material in the rest of the groove until the groove is filled.
The grooves filled by the two methods are provided with gaps, the gaps are larger for the first method, and the gaps are smaller for the second method.
Therefore, it is difficult to achieve seamless filling of grooves with large aspect ratios in the prior art.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present application mainly aims to provide a semiconductor process, a method for manufacturing a semiconductor device, and a semiconductor device, so as to solve the problem that the semiconductor process in the prior art is difficult to realize seamless filling of a groove with a large aspect ratio.
In order to achieve the above object, according to one aspect of the present application, there is provided a semiconductor process comprising: forming a semiconductor substrate having a recess; arranging a predetermined material in the groove until the thickness of the predetermined material is greater than or equal to a predetermined thickness, wherein the predetermined material is a fluid material; controlling the semiconductor substrate to rotate, wherein a rotating shaft of the semiconductor substrate is parallel to the thickness direction of the semiconductor substrate; and curing the predetermined material to form the filling structure.
Further, the predetermined thickness is greater than or equal to a depth of the groove.
Further, disposing a predetermined material in the groove comprises: dropping the predetermined material into the groove.
Further, the rotation axis of the semiconductor substrate is an axis passing through the semiconductor substrate.
Furthermore, the viscosity of the preset material is between 0.2 and 10000cP, and the rotation speed of the semiconductor substrate is between 100 and 8000 PRM.
Further, the predetermined material is cured by ultraviolet curing and/or thermal curing.
Further, the aspect ratio of the groove is greater than or equal to 6.
In order to achieve the above object, according to an aspect of the present application, there is provided a method of manufacturing a semiconductor device, the method including any one of the semiconductor processes.
Further, the semiconductor device is a 3D NAND memory.
According to still another aspect of the present application, there is provided a semiconductor device comprising a semiconductor structure fabricated by any one of the semiconductor processes described above.
By applying the technical scheme of the application, in the semiconductor process, the fluid-shaped preset material is arranged in the groove, the semiconductor substrate is rotated, and the preset material is solidified subsequently to form the filling structure. In the process, the semiconductor substrate rotates when, after or before the fluid-shaped preset material is arranged, so that the preset material in the groove is uniformly distributed without gaps, the gap in the filling structure is finally formed, the problem that the groove with a large depth-to-width ratio is difficult to fill seamlessly in the prior art is solved, the formed filling structure is ensured to have good performance, and the semiconductor device formed by the semiconductor process is ensured to have good performance. In addition, the process is easy to control, has low cost and can be widely applied to the manufacturing process of various semiconductor devices.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a schematic structural diagram of a semiconductor substrate in one embodiment of the present application;
FIG. 2 shows a schematic view of the arrangement of a predetermined material in the recess of FIG. 1;
FIG. 3 is a schematic view showing a structure after a predetermined material covers the surface of the semiconductor substrate on both sides of the recess; and
fig. 4 shows a schematic diagram of a semiconductor structure formed by the semiconductor process of the present application.
Wherein the figures include the following reference numerals:
10. a semiconductor substrate; 11. a groove; 20. a predetermined material; 21. and (5) filling the structure.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, in the semiconductor process in the prior art, it is difficult to achieve seamless filling of a groove with a large aspect ratio, and in order to solve the above technical problems, the present application provides a semiconductor process, a method for manufacturing a semiconductor device, a semiconductor structure and a semiconductor device.
In an exemplary embodiment of the present application, there is provided a semiconductor process, including: forming a semiconductor substrate 10 having a recess 11, as shown in fig. 1; arranging a predetermined material 20 in the groove 11, wherein the schematic process structure is shown in fig. 2, until the thickness of the predetermined material 20 is greater than or equal to a predetermined thickness, and the predetermined material 20 is a fluid material; controlling the semiconductor substrate 10 to rotate, wherein the rotation axis of the semiconductor substrate 10 is parallel to the thickness direction of the semiconductor substrate 10, and the structure shown in fig. 3 is formed; the predetermined material 20 is cured to form a filled structure 21, as shown in fig. 4.
In the semiconductor process, the filling structure is formed by disposing the fluid-shaped predetermined material in the groove, rotating the semiconductor substrate, and then curing the predetermined material. In the process, the semiconductor substrate is controlled to rotate while, after or before the fluid-shaped preset material is arranged, so that the preset material in the groove is uniformly distributed, no gap exists, the gap does not exist in the filling structure finally, the problem that the groove with a large depth-to-width ratio is difficult to fill seamlessly in the prior art is solved, the formed filling structure is ensured to have good performance, and the semiconductor device formed by the semiconductor process is ensured to have good performance. In addition, the process is easy to control, has low cost and can be widely applied to the manufacturing process of various semiconductor devices.
It should be noted that the groove in this application may be a structure formed through any process, may be formed by directly etching a predetermined structure, or may be a groove formed by etching a preliminary groove for the predetermined structure, and then filling the preliminary groove with another material, and forming the remaining preliminary groove. The semiconductor process is applicable to any groove formed in the manufacturing process of a semiconductor device, for example, the groove can be formed in the manufacturing process of a 3D NAND memory, and can also be formed in the manufacturing process of other devices, such as grooves in an MRAM memory.
It should be noted that the step of rotating the semiconductor substrate and the step of disposing the predetermined material in the groove in the present application may be performed simultaneously, or may be performed first and then, or may be performed in other suitable manners. The case of synchronous progress is: the semiconductor substrate is controlled to rotate, i.e., set while rotating, while the predetermined material is set in the groove. A first-then-last case includes two specific cases, one case being: firstly, arranging a preset material in the groove, and then controlling the semiconductor substrate to rotate; the other situation is as follows: the semiconductor substrate is controlled to rotate, and then the predetermined material is disposed in the groove, and of course, the semiconductor substrate is maintained in a rotating state during the disposing of the predetermined material. Other suitable manners, such as performing two steps simultaneously first and then performing the two steps one after the other, are not described in detail, and those skilled in the art can adjust the order of the two steps according to actual situations.
The predetermined material in this application may be any fluid-like material of the predetermined filling materials in the prior art, for example, if the recess needs to be filled with a metal material, the corresponding predetermined material should comprise a metal material, and if the recess needs to be filled with a dielectric material, silicon dioxide, the corresponding predetermined material should comprise silicon dioxide. The skilled person can select suitable predetermined materials depending on the actual situation. Of course, the predetermined material and the material formed by the final curing may not be identical, since the subsequent curing process may be performed, and the predetermined material may be changed during the curing process, and the change may be only a physical change or may include a chemical change.
The predetermined thickness in the present application may be any suitable thickness, and the skilled person may select the corresponding predetermined thickness according to the actual situation. In a specific embodiment, the predetermined thickness is greater than or equal to the depth of the groove, and the predetermined material at least fills the groove. The predetermined material 20 shown in fig. 3 not only fills the grooves, but also is disposed over the grooves so that more of the predetermined material 20 can further ensure that no gaps exist in the resulting filled structure.
In a particular embodiment, disposing the predetermined material 20 in the recess comprises: the predetermined material 20 is dropped into the groove, and specifically, the predetermined material 20 may be dropped into the groove by using an instrument like a dropper, as shown in fig. 2. The embodiment is simple and flexible in operation, and the position of the predetermined material dropping into the groove can be flexibly adjusted according to actual conditions.
Of course, the manner of disposing the predetermined material in the groove in the present application is not limited to the above-mentioned dropping manner, and may be any other suitable manner, for example, injecting the predetermined material into the groove by using an injection instrument like a needle tube, or for example, inputting the predetermined material into the groove by using a small-sized input tube. Different sizes, different aspect ratios and different predetermined materials of the specific grooves may lead to different ways of disposing the predetermined material, and a person skilled in the art can select a suitable method to dispose the predetermined material in the grooves according to actual situations.
In addition, it should be noted that the manner of controlling the rotation of the semiconductor substrate in the present application may be any feasible method, for example, the semiconductor substrate may be placed on a rotatable carrier, and during the process of forming the filling structure, the carrier is controlled to rotate, and the carrier drives the semiconductor substrate thereon to rotate.
In order to further ensure that the rotation process can make the predetermined material in the groove uniformly distributed, in a specific embodiment of the present application, the rotation axis of the semiconductor substrate is an axis passing through the semiconductor substrate. In a more specific embodiment, the rotation axis is a central axis of the semiconductor substrate, which further ensures a uniform distribution of the predetermined material in the recess.
In order to further ensure that no gap exists in the formed filling structure, in a specific embodiment of the present application, the viscosity of the predetermined material is between 0.2 and 10000cP, and the rotation speed of the semiconductor substrate is between 100 and 8000 PRM. The viscosity is matched with the rotating speed, so that the predetermined material can be further uniformly distributed in the groove without gaps, and the formed filling structure is further ensured not to have gaps.
In a specific practical application process, the curing in the above process may be any feasible curing manner, and a person skilled in the art may select a suitable curing manner according to practical situations, and may specifically select a curing manner according to a predetermined material. In a specific embodiment of the present application, the predetermined material is cured by an ultraviolet curing method and/or a thermal curing method. The embodiment specifically includes three cases, the first case is that only the ultraviolet curing mode is adopted to cure the predetermined material; secondly, only the predetermined material is cured by a heat curing method; third, a combination of uv curing and thermal curing is used to cure the predetermined material. The ultraviolet curing mode and the thermal curing mode are relatively common curing modes, the operation is simple, and the curing effect is good.
It should be noted that the semiconductor process in the present application is applicable to any depth-to-width ratio (B/T) groove, specifically, a groove with a relatively large depth-to-width ratio, or a groove with a relatively small depth-to-width ratio, and of course, the above method is particularly applicable to a groove with a relatively large depth-to-width ratio.
In practical application, a common filling manner is adopted to fill a groove with a small aspect ratio, and an obtained filling structure basically has no gap, so that in order to improve the manufacturing efficiency of a semiconductor device and simplify the manufacturing process, the semiconductor process can be adopted only for the groove with the large aspect ratio, and in a specific embodiment of the application, the aspect ratio of the groove is greater than or equal to 6. That is, in this embodiment, the semiconductor process is more suitable for a groove having an aspect ratio of 6 or more.
In another exemplary embodiment of the present application, a method for manufacturing a semiconductor device is provided, the method for manufacturing including any one of the above semiconductor processes.
The manufacturing method of the semiconductor device comprises the semiconductor process, so that a filling structure in the device has no gap, and the good performance of the device is further ensured.
The semiconductor device of the present application may be any device in the art that includes a fill structure, and may be, for example, an MRAM. In a specific embodiment of the present application, the semiconductor device is a 3D NAND memory. Due to the fact that the depth-to-width ratio of the groove formed in the manufacturing process of the 3D NAND memory is large, the performance of a filling structure formed by filling the groove in the 3D NAND memory can be further guaranteed to be good by the aid of the semiconductor process, and the performance of the 3D NAND memory is further guaranteed to be good.
In yet another exemplary embodiment of the present application, a semiconductor device is provided, which is formed using any of the semiconductor processes described above. The semiconductor structure is actually a filled structure, i.e., the filled structure is formed using any of the semiconductor processes described above.
The filling structure in the semiconductor device is formed by adopting the semiconductor process, no gap exists, the performance is good, and the performance of the semiconductor device is good.
The semiconductor device of the present application may be any device in the art that includes a fill structure, for example, may be a nanowire device. In a specific embodiment of the present application, the semiconductor device is a 3D NAND memory. Due to the fact that the depth-to-width ratio of the groove formed in the manufacturing process of the 3D NAND memory is large, the performance of a filling structure formed by filling the groove in the 3D NAND memory can be further guaranteed to be good by the aid of the semiconductor process, and the performance of the 3D NAND memory is further guaranteed to be good.
In order to enable those skilled in the art to further understand the technical solutions and technical effects of the present application, the technical solutions of the present application will be described below with reference to specific embodiments.
Examples
In this embodiment, the semiconductor process for forming the filling structure in the groove includes:
step S1, forming a predetermined substrate;
step S2, etching the predetermined substrate to form the semiconductor substrate 10 having the groove 11 shown in fig. 1, wherein the depth-to-width ratio of the groove 11 is 10;
step S3, placing the semiconductor substrate on a rotatable carrier, then dropping the predetermined material 20 into the groove 11, as shown in fig. 2, and during the dropping process, controlling the carrier to rotate, so as to drive the semiconductor substrate 10 to rotate with its own central axis as a rotating axis, and the rotating axis is parallel to the thickness direction of the semiconductor substrate 10, until the predetermined material 20 covers the surfaces of the semiconductor substrate 10 at the two sides of the groove, as shown in fig. 3;
in step S4, the predetermined material is cured by thermal curing or ultraviolet curing to form the filling structure 21 shown in fig. 4.
The semiconductor process can ensure that the formed filling structure is compact and has no gap, thereby ensuring that the filling structure has good performance, and the semiconductor process is simple and flexible to operate and has high manufacturing efficiency.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) in the semiconductor process, a filling structure is formed by arranging a fluid-shaped preset material in the groove, rotating the semiconductor substrate until the preset material is filled in the groove, and then solidifying the preset material. In the process, the semiconductor substrate rotates while or after the fluid-shaped preset material is arranged, so that the preset material in the groove is uniformly distributed, no gap exists, the gap does not exist in the filling structure finally formed, the problem that the groove with a large depth-to-width ratio is difficult to fill seamlessly in the prior art is solved, the formed filling structure is ensured to have good performance, and the semiconductor device formed by the semiconductor process is ensured to have good performance. In addition, the process is easy to control, has low cost and can be widely applied to the manufacturing process of various semiconductor devices.
2) Due to the fact that the manufacturing method of the semiconductor device comprises the semiconductor process, gaps do not exist in the filling structure of the device, and the good performance of the device is further guaranteed.
3) The filling structure in the semiconductor device is formed by adopting the semiconductor process, no gap exists, the performance is good, and the performance of the semiconductor device is good.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A semiconductor process, comprising:
forming a semiconductor substrate having a recess;
arranging a predetermined material in the groove until the thickness of the predetermined material is greater than or equal to a predetermined thickness, wherein the predetermined material is a fluid material;
controlling the semiconductor substrate to rotate, wherein a rotating shaft of the semiconductor substrate is parallel to the thickness direction of the semiconductor substrate;
and curing the predetermined material to form the filling structure.
2. The semiconductor process of claim 1, wherein the predetermined thickness is greater than or equal to a depth of the recess.
3. The semiconductor process of claim 1, wherein disposing a predetermined material in the recess comprises:
dropping the predetermined material into the groove.
4. The semiconductor process of claim 1, wherein the axis of rotation is an axis through the semiconductor substrate.
5. The semiconductor process of claim 1, wherein the predetermined material has a viscosity of 0.2 to 10000cP, and the semiconductor substrate is rotated at a speed of 100 to 8000 PRM.
6. The semiconductor process according to claim 1, wherein the predetermined material is cured by means of uv curing and/or thermal curing.
7. The semiconductor process according to any of claims 1 to 6, wherein the aspect ratio of the recess is greater than or equal to 6.
8. A method of manufacturing a semiconductor device, characterized in that the method comprises the semiconductor process of any one of claims 1 to 7.
9. The method of manufacturing according to claim 8, wherein the semiconductor device is a 3D NAND memory.
10. A semiconductor device comprising a semiconductor structure, wherein the semiconductor structure is fabricated using the semiconductor process of any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910775850.1A CN110676152A (en) | 2019-08-21 | 2019-08-21 | Semiconductor process, manufacturing method of semiconductor device and semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910775850.1A CN110676152A (en) | 2019-08-21 | 2019-08-21 | Semiconductor process, manufacturing method of semiconductor device and semiconductor device |
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| CN110676152A true CN110676152A (en) | 2020-01-10 |
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| CN201910775850.1A Pending CN110676152A (en) | 2019-08-21 | 2019-08-21 | Semiconductor process, manufacturing method of semiconductor device and semiconductor device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007134420A (en) * | 2005-11-09 | 2007-05-31 | Ulvac Japan Ltd | Embedding method inside structure by hydrophobic porous silica material |
| CN104465498A (en) * | 2014-11-12 | 2015-03-25 | 华天科技（昆山）电子有限公司 | Method for evenly coating silicon through hole inner wall with insulation layer |
| CN108067401A (en) * | 2016-11-15 | 2018-05-25 | 株式会社斯库林集团 | Coating method |
-
2019
- 2019-08-21 CN CN201910775850.1A patent/CN110676152A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007134420A (en) * | 2005-11-09 | 2007-05-31 | Ulvac Japan Ltd | Embedding method inside structure by hydrophobic porous silica material |
| CN104465498A (en) * | 2014-11-12 | 2015-03-25 | 华天科技（昆山）电子有限公司 | Method for evenly coating silicon through hole inner wall with insulation layer |
| CN108067401A (en) * | 2016-11-15 | 2018-05-25 | 株式会社斯库林集团 | Coating method |
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