CN110651370B - Semiconductor device, display device, and sputtering target - Google Patents
Semiconductor device, display device, and sputtering target Download PDFInfo
- Publication number
- CN110651370B CN110651370B CN201780090747.2A CN201780090747A CN110651370B CN 110651370 B CN110651370 B CN 110651370B CN 201780090747 A CN201780090747 A CN 201780090747A CN 110651370 B CN110651370 B CN 110651370B
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- oxide
- layer
- copper
- atomic
- conductive metal
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- 238000005477 sputtering target Methods 0.000 title description 53
- 239000000758 substrate Substances 0.000 claims abstract description 165
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 124
- 229910052802 copper Inorganic materials 0.000 claims abstract description 124
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- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910000410 antimony oxide Inorganic materials 0.000 claims abstract description 40
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- 229910000420 cerium oxide Inorganic materials 0.000 claims abstract description 39
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims abstract description 38
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 25
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- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 claims description 15
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/08—Oxides
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
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- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Liquid Crystal (AREA)
- Electroluminescent Light Sources (AREA)
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Semiconductor Integrated Circuits (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
A semiconductor device includes a substrate, a conductive wiring provided on one surface of the substrate, and a thin film transistor electrically connected to the conductive wiring. The conductive wiring has 3 layers in which a copper layer or a copper alloy layer is sandwiched between a first conductive metal oxide layer and a second conductive metal oxide layer. The first conductive metal oxide layer and the second conductive metal oxide layer contain indium oxide. The thin film transistor has a channel layer composed of an oxide semiconductor. The oxide semiconductor is a composite oxide containing indium oxide, antimony oxide, and cerium oxide in an amount smaller than the respective amounts of the indium oxide and the antimony oxide. In the oxide semiconductor, the total amount of the elements excluding oxygen is set to 100 atomic% and the respective amounts of indium and antimony are 40 atomic% or more.
Description
Technical Field
The invention relates to a semiconductor device, a display device and a sputtering target.
Background
A thin film transistor using an oxide semiconductor as a channel layer has a leakage current smaller than that of a silicon semiconductor by approximately 2 bits, and is attracting attention as a power-saving device. In addition, such a thin film transistor has a high voltage resistance, and therefore, is also attracting attention for use in a power semiconductor element.
In addition, in a circuit configuration using a silicon semiconductor or a circuit configuration using an oxide semiconductor, a low-resistance conductive wiring is desired as a conductive wiring for electrically connecting circuit components in the above-described device. Since aluminum has a resistivity (specific resistance) of 2.7 μΩ cm and copper has a resistivity of 1.7 μΩ cm, an attempt has been made to replace aluminum wiring with copper wiring as a low-resistance conductive wiring. In recent years, copper wiring having better conductivity has been desired.
For example, patent document 1 provides a metal wiring having a copper layer sandwiched between oxide layers containing indium and zinc. The zinc oxide content is 10 wt% or more and less than 35 wt%. Paragraph [0050] of patent document 1 is expressed as zinc oxide (ZnO), indium oxide (InO), or the like. According to claim 1 of patent document 1, there is no specific description about indium of a metal element contained in an oxide, and definition of the metal element is not shown, so that an atomic ratio (atomic%) of the metal element is not clear. It is assumed that the atomic ratio in the oxide layer calculated as the lower limit value of the zinc oxide content of 10 wt% becomes about 15 atomic% in terms of indium oxide (InO). If the amount of zinc element exceeds 10 atomic% based on the total amount of indium element and zinc element, alkali resistance increases, and it is difficult to obtain ohmic contact. This tendency becomes more remarkable as the amount of zinc element is larger. When the amount of zinc exceeds 10 atomic%, the surface resistance of the composite oxide containing zinc oxide and indium oxide is reduced, which is an obstacle in the step of electrically mounting such metal wiring on a substrate or the like. Such a technical problem is not disclosed in patent document 1. In addition, patent document 1 does not disclose any problem of migration or diffusion of copper.
On the other hand, patent document 2 and patent document 3 disclose a method of adding zinc (Zn), calcium (Ca), magnesium (Mg), manganese (Mn), and the like as alloying elements to copper as a technique for improving adhesion of copper to a glass substrate or a silicon substrate. However, patent document 2 and patent document 3 have a problem that diffusion of copper element into a base (underlayer, glass substrate, or semiconductor layer) of a copper layer (copper alloy layer) cannot be completely suppressed because a configuration in which a copper alloy is directly in contact with a glass substrate or a semiconductor layer constituting a thin film transistor is adopted. Further, patent document 2 and patent document 3 do not disclose a 3-layer structure in which a copper alloy layer is sandwiched between conductive metal oxide layers.
In addition, when a conductive wiring is formed directly on a substrate using a copper alloy, for example, the conductive wiring is formed so as to have a line width (thin line) of 10 μm or less, the conductive wiring may be peeled off from the substrate in a manufacturing process thereof. For example, in a development step such as a washing step or a semiconductor patterning step performed after a wet etching step, a conductive wiring formed by the wet etching step may be partially peeled off (a defect or a disconnection of the conductive wiring) due to electrostatic breakdown. The finer the line width of the conductive wiring, the more pronounced the tendency of the conductive wiring to peel off. The technical problems in such a manufacturing process are not disclosed in patent document 1, patent document 2, and patent document 3.
Patent document 4 discloses an element such as In, ga, zn, sn, sb as an oxide semiconductor film. However, in the disclosure of paragraph [0030], the oxide semiconductor composition is not described In detail except for In-Zn system and Sn-In-Zn system, and for example, the action and effect when antimony oxide or cerium oxide is used are not described.
Prior art literature
Patent literature
Patent document 1: japanese patent laid-open publication No. 2014-78700
Patent document 2: japanese patent application laid-open No. 2011-91364
Patent document 3: japanese patent No. 5099504
Patent document 4: japanese patent laid-open No. 2007-73704
Disclosure of Invention
Technical problem to be solved by the invention
The aluminum wiring is a low-resistance wiring, and has practical reliability because aluminum is passivated. Therefore, aluminum wiring is often used as the conductive wiring used for the functional device. However, due to thermal processes, long-term storage, and the like in the manufacturing process of a functional device having an aluminum wiring having high purity and excellent conductivity, hillocks (hemispherical protrusions and the like) tend to be generated on the surface of the aluminum wiring, and reliability degradation such as insulation failure tends to occur. In order to solve the problem of hillock, an aluminum alloy to which a small amount of a metal such as Nd (neodymium) or Ta (tantalum) is added is generally used.
High purity aluminum has a resistivity of 2.7 μΩ cm, but increases in resistivity due to addition of Nd or Ta to aluminum are 3.7 μΩ cm/atom% and 8.6 μΩ cm/atom%, respectively. In other words, by adding 1 atomic% of Nd to aluminum, the resistivity of the aluminum alloy (al—nd based alloy) becomes computationally 6.4 μΩ cm, and the resistivity deteriorates compared to high purity aluminum. In general, the target resistivity of the aluminum alloy wiring is 6 μΩ cm or less.
Copper alloy wiring is more excellent than aluminum alloy wiring in terms of alkali resistance. From the viewpoint of such chemical resistance, copper alloy wiring is also required as a conductive wiring used for functional devices. Further, aluminum or aluminum alloy cannot obtain ohmic contact to a transparent electrode such as ITO. Therefore, copper or copper alloy is also expected to be used as a conductive wiring for use in a functional device from the viewpoint of ohmic contact.
Copper having a resistivity of 1.7 μΩ cm, which is higher than aluminum, is expected as a conductive wiring in place of aluminum alloy wiring. However, copper wiring has disadvantages in that copper is easily diffused to cause a decrease in reliability, and the surface of copper is not passivated, copper oxide is formed with time, and the amount of copper oxide increases. When the film thickness of the copper oxide formed on the copper surface increases, the surface resistance increases, and problems occur in the process of electrically mounting copper wiring on a substrate or the like. The formation of copper oxide in the copper wiring is not preferable because it not only increases the surface resistance of the copper wiring but also varies (varies) due to unevenness in contact resistance and threshold voltage (Vth) of the thin film transistor. In the electrical mounting of copper wiring, copper alloy wiring counter electrode, and the like, pretreatment such as chelate washing is necessary to remove copper oxide on the wiring surface.
In electronic devices, in order to suppress copper diffusion, which is a fundamental technical problem due to the characteristics of copper, a 3-layer structure or a 2-layer structure in which copper is sandwiched by high-melting-point metals such as titanium (Ti), molybdenum (Mo), and tungsten (W) is often used. However, these refractory metals are difficult to pattern (pattern formation) with copper (using a one-component etchant, 1 time). Patterning of Ti, mo, or the like is often performed using an etching solution different from that used in patterning copper, or patterning is performed by dry etching. For example, in a liquid crystal display device, a wiring having 2 layers of titanium/copper may be formed on an insulating layer such as silicon oxide.
Further, in the step of forming a circuit or the step of forming a matrix of thin film transistors constituting a display device, it is necessary to obtain electrical contact between a connection point (pad or the like) of a circuit element or a thin film transistor and a wiring located above the connection point through a via hole. In this case, a copper oxide layer is formed on the surface of the high-melting-point metal or the surface of copper, and therefore, a high contact resistance is often generated. In other words, with the existing copper wiring, it is difficult to obtain ohmic contact required for electrical mounting. Further, the copper thin film exposed to the air is likely to grow abnormally during the heat treatment, to be thinned on the surface of the thin film, and to deteriorate the resistivity.
In addition, a channel layer (oxide semiconductor layer) formed of a composite oxide containing indium oxide, gallium oxide, and zinc oxide, which is called IGZO, is often subjected to heat treatment at a temperature ranging from 400 to 700 ℃ in order to ensure reliability due to crystallization. In the production process of a liquid crystal display device or the like, in this heat treatment, mutual diffusion of titanium and copper often occurs, and the conductivity of copper wiring is greatly deteriorated. When the heat treatment is not performed, the channel layer formed of IGZO may have a variation in threshold voltage (Vth) due to a change with time, and is not practical. Regarding the variation in threshold voltage (Vth) due to the change with time, it is considered that the change in impurity level such as oxygen defect in the oxide semiconductor layer is an influence of hydrogen embedded in the oxide semiconductor layer. It is also expected that titanium or titanium nitride is liable to intercalate hydrogen, and that the transistor characteristics change due to hydrogen contained in the metal electrode or the metal wiring. Further, when the source electrode or the gate electrode is formed of titanium or copper, a metal such as titanium in contact with the channel layer may reduce an oxide semiconductor forming the channel layer (oxide semiconductor layer), and thus the transistor characteristics may be degraded. In a manufacturing process of a thin film transistor including a channel layer formed of IGZO or the like, a low-temperature process is required in which the conductivity of copper wiring is not deteriorated.
In addition, indium oxide or antimony oxide may cause oxygen deficiency during vacuum film formation such as sputtering, and it is difficult to obtain sufficient semiconductor characteristics. Further, a channel layer formed of an oxide semiconductor containing indium oxide or antimony oxide is susceptible to etching damage in a step of forming a source electrode or the like by a manufacturing process such as wet etching. An oxide semiconductor which is hardly affected by an etchant used in wet etching is required.
The present invention has been made in view of the above-described problems, and an object thereof is to provide a semiconductor device, a display device, and a sputtering target which have good reliability even when copper wiring is used and which can be easily manufactured.
Means for solving the technical problems
The semiconductor device according to the first aspect of the present invention includes a substrate, a conductive wiring provided on one surface of the substrate, and a thin film transistor electrically connected to the conductive wiring, wherein the conductive wiring includes 3 layers including a copper layer or a copper alloy layer sandwiched between a first conductive metal oxide layer and a second conductive metal oxide layer, the first conductive metal oxide layer and the second conductive metal oxide layer include indium oxide, the thin film transistor includes a channel layer including an oxide semiconductor, and the oxide semiconductor is a composite oxide including indium oxide, antimony oxide, and cerium oxide having amounts less than respective amounts of the indium oxide and the antimony oxide, and the amounts of indium and antimony are 40 atomic% or more, respectively, when the total of elements other than oxygen is 100 atomic%.
In the semiconductor device according to the first aspect of the present invention, it may be that: in the oxide semiconductor, when the total of indium, antimony and cerium, which are not counted as oxygen, is set to 100 atomic%, the respective amounts of indium and antimony are in the range of 45 atomic% or more and 49.8 atomic% or less, and the amount of cerium is in the range of 10 atomic% or less and 0.4 atomic% or more.
In the semiconductor device according to the first aspect of the present invention, the thin film transistor may have an insulating film which is in contact with the channel layer and contains at least cerium oxide.
In the semiconductor device according to the first aspect of the present invention, it may be that: the copper alloy layer contains a first element that is solid-dissolved in copper and a second element that has an electronegativity smaller than that of copper and the first element, wherein the first element and the second element are elements that have a specific resistance increase rate of 1 [ mu ] Ω cm/atom% or less when added to copper, and the specific resistance of the copper alloy layer is in the range of 1.9 [ mu ] Ω cm to 6 [ mu ] Ω cm.
In the semiconductor device according to the first aspect of the present invention, it may be that: in the copper alloy layer, the first element is zinc, the second element is calcium, and the copper alloy layer contains the first element in a range of 0.2 atomic% or more and 5.0 atomic% or less, and the second element in a range of 0.2 atomic% or more and 5.0 atomic% or less, with the total of copper, zinc, and calcium being 100 atomic%, and the copper being the remainder.
In the semiconductor device according to the first aspect of the present invention, it may be that: the first conductive metal oxide layer and the second conductive metal oxide layer are conductive metal oxides containing indium oxide as a main conductive metal oxide and containing 1 or more kinds selected from antimony oxide, zinc oxide and gallium oxide.
A display device according to a second aspect of the present invention includes the semiconductor device according to the first aspect.
In the display device according to the second aspect of the present invention, it may be: an antenna is provided which is formed by a conductive wiring having 3 layers in which a copper layer or a copper alloy layer is sandwiched between a first conductive metal oxide layer and a second conductive metal oxide layer, wherein the first conductive metal oxide layer and the second conductive metal oxide layer contain indium oxide.
A sputtering target according to a third aspect of the present invention is the sputtering target used for manufacturing the semiconductor device according to the first aspect, wherein indium oxide and antimony oxide are contained as main materials, and a composite oxide containing cerium oxide is contained as a stabilizer, and the composite oxide contains indium and antimony in an amount of 45 atomic% to 49.8 atomic% and cerium in an amount of 10 atomic% to 0.4 atomic% inclusive, where the total of indium, antimony and cerium, which are not counted as 100 atomic%.
A sputtering target according to a fourth aspect of the present invention is a sputtering target used for forming a copper alloy layer constituting a semiconductor device according to the first aspect, comprising a first element which is solid-dissolved in copper and a second element which has electronegativity smaller than that of copper and the first element, wherein the first element is zinc, and the second element is calcium, and wherein the content of the first element is in a range of 0.2 atomic% or more and 5.0 atomic% or less, and the content of the second element is in a range of 0.2 atomic% or more and 5.0 atomic% or less, and the remainder excluding the first element and the second element contains copper, when the total of copper, zinc, and calcium is 100 atomic%.
Effects of the invention
According to the above aspect of the present invention, a semiconductor device and a display device including a thin film transistor which can be formed using a conductive wiring having a high conductivity by a low-temperature process and which has stable characteristics can be provided.
Drawings
Fig. 1 is a sectional view partially showing a display device including a semiconductor device according to a first embodiment of the present invention.
Fig. 2 is a plan view partially showing a display device including a semiconductor device according to a first embodiment of the present invention.
Fig. 3 is a sectional view partially showing a semiconductor device according to a first embodiment of the present invention.
Fig. 4 is a sectional view partially showing a conductive wiring which is a constituent element of the semiconductor device of the first embodiment of the present invention.
Fig. 5 is a schematic configuration diagram showing a sputtering apparatus provided with a sputtering target used for manufacturing a semiconductor device according to the first embodiment of the present invention.
Fig. 6 is a block diagram showing a control unit (an image signal control unit, a system control unit, and a touch sensor control unit) and a display unit constituting a display device including a semiconductor device according to a second embodiment of the present invention.
Fig. 7 is a sectional view partially showing a display device including a semiconductor device according to a second embodiment of the present invention.
Fig. 8 is a cross-sectional view partially showing an array substrate (first substrate) constituting a display device according to a second embodiment of the present invention, and is a view illustrating a driving transistor and a light-emitting layer of an organic EL formed on the array substrate.
Fig. 9 is a view of a display device according to a second embodiment of the present invention, which is a plan view showing circuits such as a first conductive wiring, a second conductive wiring, a first antenna unit, a second antenna unit, and a control unit formed on a substrate (second substrate) of the display device.
Fig. 10 is a plan view showing circuits such as a third antenna unit, a fourth antenna unit, a source signal switching circuit, a gate signal switching circuit, and a driving transistor for driving an organic EL, which are formed on an array substrate (first substrate) constituting a display device according to a second embodiment of the present invention.
Fig. 11 is a partial plan view showing an enlarged view of a first antenna unit formed on a display device substrate constituting a display device including a semiconductor device according to a second embodiment of the present invention.
Fig. 12 is a view showing a first antenna element formed on a display device substrate constituting a display device including a semiconductor device according to a second embodiment of the present invention, and is a cross-sectional view taken along line A-A' shown in fig. 11.
Fig. 13 is a perspective view showing the overlapping of a first antenna unit formed on a display device substrate constituting a display device including a semiconductor device according to a second embodiment of the present invention and a third antenna unit formed on an array substrate.
Detailed Description
Embodiments of the present invention will be described below with reference to the drawings.
In the embodiments of the present invention, a semiconductor device including a thin film transistor using an oxide semiconductor as a channel layer, a semiconductor device including a copper alloy wiring having a 3-layer structure with low resistance (specific resistance) and low contact resistance, and a display device to which the semiconductor device is applied will be described. Further, a description will be given of a novel sputtering target used for manufacturing the semiconductor device.
In the following description, the same or substantially the same functions and constituent elements are denoted by the same reference numerals, and description thereof will be omitted or simplified or will be made only when necessary. In each of the drawings, the components are made to be of a size that can be recognized in the drawings, and therefore, the dimensions and ratios of the components are appropriately different from the actual cases. Elements which are difficult to be illustrated, for example, a structure of an insulating layer, a buffer layer, and a plurality of layers forming a channel layer of a semiconductor, the number of thin film transistors, a structure of a plurality of layers forming a conductive layer, an optical film such as an alignment film, a polarizing film, and a retardation film, which impart initial alignment to a liquid crystal layer, a cover glass for protection, a backlight, and the like are omitted as necessary.
As a substrate which can be applied to the semiconductor device according to the embodiment of the present invention, a semiconductor substrate such as silicon, silicon carbide, or silicon germanium, a glass substrate such as alkali-free glass, a ceramic substrate, a quartz substrate, a sapphire substrate, a plastic substrate such as polyimide, or polyamide, or the like can be applied. In the case of applying the thin film transistor to a substrate of a semiconductor device, an insulating film such as silicon oxide or silicon nitride oxide may be formed before forming the thin film transistor or the conductive metal oxide layer. When the semiconductor device is applied to a reflective display device, a thin film of silver alloy may be formed on a substrate. In the following description, the substrates may be referred to as a first substrate and a second substrate.
The ordinal words such as "first" or "second" used for the first substrate or the second substrate, and the first conductive wiring, the second conductive wiring, the third conductive wiring, and the like are included to avoid mixing of constituent elements, and are not limited in number. The first conductive wiring, the second conductive wiring, and the third conductive wiring are sometimes referred to as conductive wirings only in the following description.
In the following description, the first conductive metal oxide layer and the second conductive metal oxide layer may be simply referred to as conductive metal oxide layers. The display device according to the embodiment of the present invention may have a touch sensing function using a capacitance system. As described later, a conductive wiring such as the first conductive wiring or the third conductive wiring can be used as a detection wiring or a driving wiring for touch sensing. In the following description, conductive wirings, electrodes, and signals related to touch sensing are sometimes referred to as only touch wirings, touch driving wirings, touch detecting wirings, touch electrodes, and touch driving signals. The voltage applied to the touch sensing wiring for driving the touch sensing is referred to as a touch driving voltage, and the voltage applied between the common electrode and the pixel electrode for driving the liquid crystal layer as the display function layer is referred to as a liquid crystal driving voltage. The voltage for driving the organic EL layer is referred to as an organic EL driving voltage. The conductive wiring connected to the common electrode is sometimes referred to as a common wiring.
The "planar view" described below refers to a plane that a viewer (symbol OB described below) sees from a direction of viewing a display surface of the display device (a plane of a display device substrate). The shape of the display portion of the display device according to the embodiment of the present invention, the shape of the pixel opening of the predetermined pixel, and the number of pixels constituting the display device are not limited. However, in the embodiments described below, the display device will be described with respect to a plan view, in which the short side direction of the pixel opening is defined as the X direction, the long side direction (longitudinal direction) is defined as the Y direction, and the thickness direction of the substrate is defined as the Z direction. In the following embodiments, the display device may be configured by switching between the X direction and the Y direction defined above.
(first embodiment)
(Structure of display device DSP 1)
Fig. 1 is a sectional view partially showing a display device DSP1 including a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a plan view partially showing a display device including a semiconductor device according to a first embodiment of the present invention.
The display device DSP1 is a liquid crystal display device including a first substrate 1, a second substrate 2, and a liquid crystal layer 4 sandwiched between the first substrate 1 and the second substrate 2.
A first insulating layer 41, a second insulating layer 42, and a third insulating layer 43 are stacked on the first substrate 1. As described later, the thin film transistor 39 (the semiconductor device 3) is provided between the first insulating layer 41 and the second insulating layer 42. The pixel electrode 9 is formed on the third insulating layer 43, and the pixel electrode 9 is electrically connected to the thin film transistor 39 through a contact hole 45 (see fig. 3) provided in the third insulating layer 43. The pixel electrode 9 is, for example, a transparent conductive film called ITO or the like. In the case of an organic EL device or a reflective display device, the pixel electrode 9 may be a reflective electrode of light reflectivity such as silver alloy or aluminum. The pixel electrode 9 is provided at a position corresponding to a pixel opening 14 described later. The pixel electrode 9 and the thin film transistor 39 are formed in a matrix shape in a plan view (see fig. 10, for example).
A plurality of pixel openings 14 are defined in a surface of the second substrate 2 facing the first substrate 1. The red pixel R, the green pixel G, and the blue pixel B are provided in the pixel openings 14, respectively.
A black matrix BM is provided between adjacent pixels, that is, between the red pixel R and the green pixel G, and between the blue pixel B and the red pixel R in the example shown in fig. 1. As shown in fig. 2, the red pixel R, the green pixel G, and the blue pixel B are divided into grids by the black matrix BM to form a color filter. A cover coat OC as a transparent resin is laminated on the color filter. A transparent electrode 8 as ITO is formed on the overcoat layer OC.
A liquid crystal layer 4 is sandwiched between the first substrate 1 and the second substrate 2. The thin film transistor 39 is switched, and a voltage is applied between the transparent electrode 8 and the pixel electrode 9, and the liquid crystal layer 4 is driven by the applied voltage.
The display device DSP1 shown in fig. 1 is driven by a vertical electric field (voltage applied between the pixel electrode 9 and the transparent electrode 8), but may be a liquid crystal display device of a horizontal electric field type such as IPS or FFS.
(semiconductor device)
Fig. 3 is a sectional view partially showing a semiconductor device 3 according to a first embodiment of the present invention.
The semiconductor device 3 includes a first substrate 1, conductive wirings provided on the first substrate 1 (on one surface of the substrate), and a thin film transistor 39 electrically connected to the conductive wirings. Specifically, in the semiconductor device 3, a first insulating layer 41 made of silicon oxide nitride is formed on the first substrate 1, and a gate electrode 38 (conductive wiring) is formed on the first insulating layer 41. Further, a second insulating layer 42 as a gate insulating film is formed on the first insulating layer 41 so as to cover the gate electrode 38. A channel layer 35, a drain electrode 37 (conductive wiring), and a source electrode 36 (conductive wiring) which are oxide semiconductors are formed on the second insulating layer 42. Further, a third insulating layer 43 is formed on the second insulating layer 42 so as to cover the channel layer 35, the drain electrode 37, and the source electrode 36. The gate electrode 38, the second insulating layer 42, the channel layer 35, the drain electrode 37, and the source electrode 36 constitute a thin film transistor 39.
The source electrode 36 is electrically connected to a source wiring 31 (conductive wiring) extending in a direction (Y direction) perpendicular to the paper surface of fig. 3. The gate electrode 38 is electrically connected to a gate wiring (conductive wiring) located on the back side in the plane of fig. 3. The distance between the end of the drain electrode 37 and the end of the source electrode 36 facing each other is the channel length L. By setting the channel length L to be short, the switching operation by the thin film transistor 39 can be vigorously started. The drain electrode 37 constituting the thin film transistor 39 is electrically connected to the pixel electrode 9 formed on the third insulating layer 43 through the contact hole 45.
Fig. 4 is a sectional view partially showing a gate electrode 38 constituting a semiconductor device according to a first embodiment of the present invention.
On the first insulating layer 41, the gate electrode 38 has a 3-layer structure in which the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12. The wiring structure of the gate electrode 38 is shown in fig. 4, but the structure having such a conductive wiring constituted of 3 layers can also be applied to the gate wiring, the source wiring 31, the drain electrode 37, and the source electrode 36.
Further, the conductive wiring formed of 3 layers including the first conductive metal oxide layer 11, the copper alloy layer 13, and the second conductive metal oxide layer 12 can be applied to the wiring formed on the first substrate 1 or the second substrate 2 in addition to the wiring or the electrode forming the thin film transistor 39. For example, the conductive wiring may be used as a wiring constituting an electronic circuit (a driver circuit or the like) formed on a substrate, a surrounding wiring extending from the electronic circuit to the thin film transistor 39, a touch sensor wiring, an antenna wiring, a light shielding pattern, or the like.
The conductive wiring can be applied to a multilayer wiring using a via hole because ohmic contact which is indispensable for mounting is easily obtained. The film thickness of the conductive metal oxide layer can be selected from the range of 10nm to 100nm, for example. The film thickness of the copper alloy layer may be selected from the range of 50nm to 500nm, for example. The film formation of the conductive metal oxide layer or the copper alloy layer 13 is preferably vacuum film formation such as sputtering. For electrical mounting, plating may be further performed on a portion of the copper alloy layer 13 of the terminal portion.
(copper alloy layer)
The copper alloy layer is specifically described below.
The copper alloy layer 13 contains a first element dissolved in copper and a second element having a smaller electronegativity than copper and the first element. The first element and the second element are elements having a specific resistance increase rate of 1 mu omega cm/atom% or less when added to copper. The resistivity of the copper alloy layer 13 is in the range of 1.9 μΩ cm to 6 μΩ cm.
The element solid-dissolved with copper according to the embodiment of the present invention may be, for example, an element stably in a substitutional solid-solution state with copper in a temperature range of (minus) 40 ℃ to + (plus) 80 ℃ which is a range including a use range of electronic devices for vehicles.
In the above temperature range (the range of use of electronic devices) and the range of the amount of the element added to the copper alloy, the element that can be substituted to the position of the copper atom in the crystal structure of copper is determined as "element in the substitution solid solution state". The amount of the element(s) added to copper may be in the range of not more than 6. Mu. OMEGA.cm as long as the resistivity (meaning the specific resistance) of the copper alloy is equal. When the matrix masterbatch is copper, gold (Au), nickel (Ni), zinc (Zn), gallium (Ga), palladium (Pd), and manganese (Mn) can be exemplified as metals having a wide solid solution region for copper. Aluminum (Al), although not wide, has a solid solution region for copper.
Examples of the element added to the copper alloy (copper alloy element) having a small specific resistance include palladium (Pd), magnesium (Mg), beryllium (Be), gold (Au), calcium (Ca), cadmium (Cd), zinc (Zn), and silver (Ag). The increase in resistivity of these elements when added at 1 atomic% to pure copper is approximately 1 μΩ cm or less. Since the increase in resistivity of calcium (Ca), cadmium (Cd), zinc (Zn) and silver (Ag) is 0.4. Mu. Ω cm/atom% or less, it is preferable as an alloy element. In view of economy and environmental load, zinc and calcium are preferably used as the alloying elements. Zinc and calcium may be added to 5 atomic% respectively as alloying elements in copper.
Based on the above-mentioned range of the addition amount, the addition amount of calcium may be increased or decreased, and the addition amount of zinc and calcium may be increased or decreased. In terms of the effect of adding zinc and calcium to copper, a remarkable effect can be obtained at an addition amount of 0.2 atomic% or more, respectively.
The resistivity of the copper alloy to which zinc and calcium were added in an amount of 0.4 at% in total with respect to pure copper was about 1.9 μΩ cm. Therefore, the lower limit of the resistivity of the copper alloy layer 13 according to the embodiment of the present invention is 1.9 μΩ cm. When calcium (Ca), cadmium (Cd), zinc (Zn), and silver (Ag) are used as the alloying elements, the resistivity of the copper alloy increases significantly when the addition amount exceeds 5 atomic% relative to the total element number of copper and the alloying elements. Therefore, the addition amount is preferably at least less than 5 atomic%.
Calcium has the property of being difficult to dissolve in copper in solid solution. The resistivity of the present invention is a value obtained by sandwiching the copper alloy layer 13 with a conductive metal oxide. As will be described later, the copper alloy layer 13 not sandwiched by the conductive metal oxides is liable to deteriorate in resistivity by performing heat treatment or the like. For example, in the case of a 2-layer structure in which titanium and pure copper are laminated on a substrate such as glass (the outermost surface is pure copper), the initial copper wiring has a resistivity of about 2 μΩ cm, but when heat treatment is performed at 400 to 500 ℃ thereafter, the resistivity may deteriorate to a level of 4 μΩ cm to 5 μΩ cm. The reason why the resistivity is deteriorated is considered to be that copper and titanium diffuse into each other and copper is oxidized by performing a high-temperature heat treatment.
Electronegativity is the relative measure of the intensity at which an atom (element) attracts an electron. The smaller the value, the more likely it is for the element to become cationic. The electronegativity of copper is 1.9. The electronegativity of oxygen was 3.5. Examples of the element having low electronegativity include alkaline earth elements, titanium group elements, chromium group elements, and the like. The electronegativity of the alkali element is also small, but when alkali element or moisture is present in the vicinity of copper, diffusion of copper is promoted. Therefore, no alkali element such as sodium or potassium is used as the alloy element of copper.
The electronegativity of calcium is as low as 1.0. When calcium is used as an alloying element of copper, it is oxidized earlier than copper to become calcium oxide during heat treatment or the like, and diffusion of copper can be suppressed. In the conductive wiring according to the embodiment of the present invention, the calcium oxide may be selectively formed on the exposed surface of the copper alloy layer not covered with the conductive metal oxide layer or on the interface between the copper alloy layer and the conductive metal oxide layer. In particular, the formation of calcium oxide on the exposed surface of the copper alloy layer not covered with the conductive metal oxide layer contributes to suppression of copper diffusion and improvement of reliability. The conductivity of the conductive wiring or the copper alloy layer according to the embodiment of the present invention is improved by annealing such as heat treatment. The electronegativity is represented by a value of electronegativity of a polarization state. In the conductive wiring according to the embodiment of the present invention, the second element is preferably oxidized to form an oxide before the copper and the first element by a heat treatment step of the conductive wiring or the like. In addition, it is preferable to prevent hydrogen and oxygen from being mixed into copper or copper alloy.
In addition, the "first element" in the embodiment of the present invention may have a smaller electronegativity than copper. The "second element" may have a solid solution region in copper. When 2 or more elements having 2 properties of having less electronegativity than copper and having a solid solution region in copper are used, the element having less electronegativity among the 2 or more elements is taken as the "second element".
For example, the first element is zinc and the second element is calcium.
Specifically, the copper alloy layer 13 contains a first element in a range of 0.2 atomic% or more and 5.0 atomic% or less, a second element in a range of 0.2 atomic% or more and 5.0 atomic% or less, and copper as the remainder, with the total of copper, zinc, and calcium being 100 atomic%.
In this embodiment, for example, a copper alloy containing 2 atomic% of calcium, 0.5 atomic% of zinc, and the balance copper and unavoidable impurities is used for the copper alloy layer 13. The resistivity of the copper alloy layer 13 having such a composition condition can be exemplified by 2.7 μΩ cm.
The resistivity of the copper alloy layer 13 may have a variation of about ±30% depending on the film forming method or annealing conditions of the copper alloy layer 13. For example, in a structure in which the copper alloy layer 13 is directly formed on a glass substrate or the like, the copper alloy layer may be oxidized (CuO or copper oxide is formed) and the resistance may be deteriorated due to heat treatment during film formation and heat treatment after film formation. In addition, in a thin alloy which is a copper alloy to which an alloy element constituting the copper alloy layer is added at a relatively low concentration, copper oxide is formed, and crystal grains of the copper alloy become excessively large. Therefore, coarse grain boundaries (crystal grain boundaries) having voids may be formed, and the surface of the copper alloy layer may be roughened, thereby deteriorating the resistance value.
In the embodiment of the present invention, the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12. According to this structure, the resistivity can be improved by heat treatment (annealing). In other words, in the embodiment of the present invention, by covering the copper alloy layer 13 with the conductive metal oxide layer, surface oxidation of the copper alloy layer 13 can be suppressed. In addition, the crystal grains of the copper alloy layer are not extremely coarsened and the surface of the copper alloy layer 13 is not roughened due to the regulation (anchoring) by the conductive metal oxide layers formed on the front and rear surfaces of the copper alloy layer 13. Even in the copper alloy layer 13 in which the alloy elements constituting the copper alloy layer 13 are added at a relatively low concentration (for example, before and after 0.2 atomic%), crystal grains (crystal grains) are hardly enlarged, and carrier scattering (deterioration of resistivity) due to grain boundaries can be suppressed. By adding the first element and the second element to the copper alloy in a total of 0.4 at% or more, a dense copper alloy layer 13 can be obtained.
In particular, when the specific resistance increase rate of the alloy element added to copper is 1 μΩ cm/atom% or less, and the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12, a remarkable effect can be easily obtained.
By performing the heat treatment, calcium oxide is formed at the interface between the copper alloy layer 13 and the first conductive metal oxide layer 11, at the interface between the copper alloy layer 13 and the second conductive metal oxide layer 12, and on the exposed surface (side surface) of the copper alloy layer 13 that is not covered with the conductive metal oxide layer. Since calcium oxide is formed on the surface of the copper alloy layer 13 or at the interface with the oxide layer, copper diffusion can be suppressed, contributing to improvement of reliability.
In addition, the copper alloy layer 13 according to the embodiment of the present invention does not need to contain oxygen (O) intentionally. The copper alloy layer containing a large amount of oxygen may generate pores in the copper alloy layer in the presence of water or alkali, for example, and may reduce the reliability of the copper alloy layer.
Therefore, for example, 3 layers of the first conductive metal oxide layer 11, the copper alloy layer 13, and the second conductive metal oxide layer 12 are continuously formed at a substrate temperature of 180 ℃ or lower. The substrate temperature may be set to room temperature (25 ℃) or lower. Further, a low-temperature anneal at 180 ℃ to 340 ℃ is performed by a post-process after patterning the channel layer. The low-temperature annealing may be performed before the step of forming the conductive wiring such as the source wiring and the drain electrode. By low temperature annealing, electrical characteristics including resistivity can be improved.
As described above, the semiconductor device according to the embodiment of the present invention can be formed by a low-temperature process at 340 ℃. The semiconductor device according to the present embodiment is particularly effective for use in an organic EL (electro luminescence) display device or a liquid crystal display device using a resin substrate, glass having a thickness of 0.4mm or less, or the like as a substrate material.
As the copper alloy used for the copper alloy layer 13, the above-described materials can be used. In the copper alloy according to the first embodiment, the content of zinc is 0.5 atom%, the content of calcium is 2.0 atom%, and the balance is copper and unavoidable impurities. The film thickness of the copper alloy is not limited. In the first embodiment, the film thickness of the copper alloy layer 13 was 280nm. The resistivity of the copper alloy layer 13 was 2.7 μΩ cm after annealing (heat treatment) described later.
In the present embodiment, the copper alloy layer 13 sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12 can be suppressed to have a very small specific resistance in the range of about 1.9 μΩ cm to 6 μΩ cm.
(conductive Metal oxide layer)
The conductive metal oxide layer is a conductive metal oxide containing indium oxide as a main component, and contains 1 or more kinds of conductive metal oxides selected from antimony oxide, zinc oxide, and gallium oxide.
The amount of indium (In) contained In the conductive metal oxide layer is necessarily more than 80 atomic%. The amount of indium (In) is preferably more than 80 atomic%. The amount of indium (In) is more preferably more than 90 atomic%. When the amount of indium (In) is less than 80 atomic%, the specific resistance of the conductive metal oxide layer formed becomes large, which is not preferable. When the amount of zinc (Zn) exceeds 20 atom%, alkali resistance of the conductive metal oxide (mixed oxide) is lowered, which is not preferable. The conductive metal oxide layers are all atomic percentages (counts of the remaining elements excluding only oxygen elements) of the elements in the mixed oxide. Antimony oxide is not likely to form a solid solution region with copper, and can be added to the conductive metal oxide layer because it suppresses diffusion of copper in the laminated structure. Other elements such as titanium, zirconium, magnesium, aluminum, germanium, etc. may be added to the mixed oxide in small amounts.
In general, the adhesion of the copper layer or copper alloy layer to the transparent resin or glass substrate (applied to the first substrate and the second substrate) is low. Therefore, when the copper layer or the copper alloy layer is directly applied to the display device or the semiconductor device, it is difficult to realize a practical display device or semiconductor device. However, the composite oxide has sufficient adhesion to a black matrix, a transparent resin, a glass substrate, and the like, and also sufficient adhesion to a copper layer or a copper alloy layer. Therefore, when the copper layer or the copper alloy layer using the above-described composite oxide is applied to a display device or a semiconductor device, a practical display device or semiconductor device can be realized.
Copper, copper alloy, silver alloy, or oxides and nitrides thereof generally do not have sufficient adhesion to transparent substrates such as glass and resin, black matrices, and the like. Therefore, when the conductive metal oxide layer is not provided, there is a problem that the conductive wiring and glass or the like are transparentInterface of bright substrate, or conductive wiring and black matrix or SiO 2 And the possibility of peeling at the interface of the formed insulating layer. When copper or a copper alloy is used as the conductive wiring having a relatively thin wiring pattern, in the display device substrate in which the conductive metal oxide layer is not formed as the underlayer of the conductive wiring, not only a failure due to peeling may occur, but also a failure due to electrostatic breakdown may occur in the conductive wiring during the manufacturing process of the display device substrate. Such electrostatic breakdown is a phenomenon in which static electricity is accumulated in a wiring pattern due to a post-process of stacking a color filter on a substrate, a process of adhering a display device substrate (corresponding to the second substrate 2, for example) to an array substrate (corresponding to the first substrate 1, for example), a washing process, or the like, and pattern missing, disconnection, or the like occurs due to electrostatic breakdown.
Further, copper oxide having no conductivity may be formed on the surface of the copper layer or the copper alloy layer with time, and it may be difficult to perform electric control. On the other hand, a composite oxide layer such as indium oxide, zinc oxide, antimony oxide, gallium oxide, and tin oxide can realize stable ohmic contact, and when such a composite oxide is used, conduction transfer (transfer) or electrical mounting via a contact hole can be easily performed. In the description of the present embodiment, "contact hole" and "via hole" have the same meaning.
In the thin film transistor using the copper wiring in this embodiment, copper oxide having no conductivity is formed over time on the surface of the copper layer or the copper alloy layer as described above, and the connection resistance tends to be uneven in the contact hole. The variation in connection resistance directly causes variation in threshold voltage (Vth) in characteristics of the thin film transistor 39, and causes a problem in driving the organic EL layer or the liquid crystal layer. In an embodiment of the present invention, a conductive metal oxide layer is formed between a conductive wiring and a surface electrically connected to the conductive wiring. Thereby, ohmic contact becomes possible. With this structure, a thin film transistor with less variation in threshold voltage (Vth) can be provided.
As a material constituting the conductive metal oxide used in the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12, the above-described materials can be used. In the first embodiment, indium oxide, zinc oxide, and tin oxide are contained so that the amount of indium (In) is 90 atom%, zinc (Zn) is 8 atom%, and tin (Sn) is 2 atom% based on the proportion of the elements not counting oxygen (when the total of the elements not counting oxygen is 100%). The film thicknesses of the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12 are not specified. In the first embodiment, the film thickness of the first conductive metal oxide layer 11 is set to 30nm, and the film thickness of the second conductive metal oxide layer 12 is set to 50nm.
(sputtering apparatus)
Fig. 5 is a schematic configuration diagram of a sputtering apparatus provided with a sputtering target used for manufacturing a semiconductor device according to the first embodiment of the present invention.
As shown in fig. 5, the sputtering apparatus 200 includes a vacuum chamber 201, a holder 202, a vacuum pump 203, a sputtering gas supply 204, a power supply 205, a backing plate 206, and a sputtering target 207. A substrate 208 (first substrate 1, second substrate 2) to be a film formation target is placed on the support 202. A sputtering target 207 is bonded to the backing plate 206, and the sputtering target 207 is disposed so as to face the holder 202 (substrate 208) in the vacuum chamber 201.
As the vacuum chamber 201, the holder 202, the vacuum pump 203, the sputtering gas supply unit 204, and the power supply 205, known structures or materials are used.
In the sputtering apparatus 200, sputtering is performed in a state in which the substrate 208 is mounted on the holder 202. Specifically, by driving the vacuum pump 203, the inside of the vacuum chamber 201 is depressurized so as to be in a vacuum state necessary for sputtering, and the pressure of the vacuum chamber 201 is maintained at a predetermined level. In this state, the sputtering gas supply unit 204 supplies a sputtering gas such as argon gas into the vacuum chamber 201, and the power supply 205 supplies a voltage to the sputtering target 207, so that sputtering is performed by the sputtering target 207, and the metal constituting the sputtering target 207 is scattered from the sputtering target 207 and deposited on the substrate 208.
Next, a case where a copper alloy sputtering target is used as the sputtering target 207 will be described.
The copper alloy sputtering target is used for forming the copper alloy layer 13, and contains a first element dissolved in copper and a second element having electronegativity smaller than that of copper and the first element, wherein the first element is zinc and the second element is calcium. Here, when the total of copper, zinc, and calcium is set to 100 at%, the remainder excluding the first element and the second element contains copper in a range of 0.2 at% or more and 5.0 at% or less of the content of the first element and in a range of 0.2 at% or more and 5.0 at% or less of the content of the second element.
(copper alloy sputtering target)
The method for producing the copper alloy sputtering target is not particularly limited.
In the following description, "copper alloy" refers to copper alloy of a sputtering target, and "copper alloy film" or "copper alloy layer" refers to a copper alloy thin film formed on the substrate 208 by vacuum using the sputtering apparatus 200. "copper" means copper having a purity of 99.99% or more and unavoidable impurities of less than 0.01%.
In the method for producing the copper alloy sputtering target, oxygen-free copper (purity 99.99 mass%), zinc (purity 99.99 mass%), and calcium (purity 99.9 mass%) are used as the raw material of the sputtering target 207, for example. The amounts of oxygen-free copper, zinc and calcium were adjusted so as to be the above-mentioned contents. The raw materials of which the amounts were adjusted in this way were melted at high frequency in a high-purity graphite crucible, and then cast into cooled carbon molds. The ingot obtained by such casting is hot rolled, for example, to a thickness of about 5mm by working and grinding, as required.
Next, a low-melting point metal such as indium is used as a bonding metal, and an ingot is bonded to the copper backing plate 206, whereby a sputtering target 207 can be obtained.
The average grain diameter of crystal grains (crystal grains) of the copper alloy observed on the surface of the sputtering target 207 is preferably 10 μm to 80 μm. When a sputtering target having an average grain size of crystal grains exceeding 80 μm is used, abnormal discharge tends to occur during sputtering in vacuum film formation, and product defects tend to occur. The average grain size of the crystal grains may be 10 μm or less, but in this case, it is necessary to rapidly cool an ingot melted during the production of the sputtering target 207 or to increase the amount of zinc added. An increase in the amount of zinc added is not preferable because it increases the resistivity of the copper alloy film. Rapid cooling tends to produce deformation in the sputter target.
Therefore, the ambient gas for melting the raw materials (oxygen-free copper, zinc, and calcium) of the sputtering target 207 and the ambient gas for casting the melted raw materials into a carbon mold are preferably such that oxygen is removed as much as possible.
When the total amount of copper, zinc and calcium is 100 at%, if calcium exceeds 5 at%, the castability of the sputtering target 207 is deteriorated, and therefore the content of calcium is preferably 5 at% or less. On the other hand, when calcium is less than 0.2 at%, the protective effect of the surface of the copper alloy layer 13 between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12 and exposed to the end thereof is reduced. At this time, the reliability of the conductive wiring formed of the 3 layers sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12 of the copper alloy layer 13 cannot be sufficiently ensured.
When the total of copper, zinc and calcium is set to 100 atomic%, if zinc exceeds 5 atomic%, the conductivity of the copper alloy layer 13 is reduced, and therefore, it is preferably 5 atomic% or less. On the other hand, when zinc is less than 0.2 atomic%, copper diffusion cannot be suppressed in a structure in which the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12, and reliability cannot be sufficiently ensured.
In the sputtering apparatus 200 shown in fig. 5, one sputtering target 207 is disposed in one vacuum chamber 201. On the other hand, a configuration may be adopted in which a plurality of sputtering targets of different types are disposed in one vacuum chamber 201. The plurality of vacuum chambers may be connected by gate valves, and the types of films formed on the substrate may be different in each of the plurality of vacuum chambers. That is, at this time, a plurality of films of different types may be continuously formed on the substrate while maintaining the vacuum state.
By using the sputtering apparatus having such an apparatus configuration, the first conductive metal oxide layer, the copper alloy layer, and the second conductive metal oxide layer can be continuously formed on the substrate while maintaining the vacuum state. In this sputtering film formation, a copper alloy sputtering target having the above composition and a conductive metal oxide target having the above composition are used. The 3-layer films of the first conductive metal oxide layer, the copper alloy layer, and the second conductive metal oxide layer thus formed can be patterned together by a known photolithography method using an acidic etchant to form conductive wirings.
(channel layer)
Next, referring back to fig. 3, a channel layer of the thin film transistor 39 constituting the semiconductor device will be described.
In the first embodiment, the oxide semiconductor constituting the channel layer 35 is a composite oxide containing indium oxide, antimony oxide, and cerium oxide in an amount smaller than each of the indium oxide and the antimony oxide. In the oxide semiconductor, when the total of the elements excluding oxygen is set to 100 atomic%, the respective amounts of indium and antimony are 40 atomic% or more.
Specifically, in this embodiment mode, when the total of the elements excluding oxygen in the oxide semiconductor is set to 100 atomic%, the amounts of indium and antimony are each about 48 atomic% and the amount of cerium is about 4 atomic%.
Further, antimony oxide or cerium oxide is not the same as gallium oxide or indium oxide, and is available at low cost, and therefore has high industrial value.
In order to adjust the electrical characteristics or mobility of the oxide semiconductor, for example, the concentration of indium oxide or the concentration of cerium oxide may be changed in the thickness direction of the channel layer 35. Alternatively, the channel layer 35 may be formed using a plurality of layers having different concentrations of cerium oxide. Alternatively, in order to expand the wet etching processability of the source electrode or the like, the composition in the surface layer of the channel layer 35 may be made rich in cerium oxide, thereby improving the acid resistance of the channel layer 35. An etching stopper layer may be laminated on the channel layer 35, but a composite oxide thin film containing cerium oxide becomes a film having high acid resistance due to annealing at 180 ℃ or higher, so that active insertion of the etching stopper layer is not necessary. The acid resistance can also be obtained by increasing the concentration of cerium oxide in the composite oxide film.
In the semiconductor device shown in fig. 3, stabilization of the channel layer as an oxide semiconductor and reduction of resistance of the conductive wiring including the first conductive metal oxide layer 11, the copper alloy layer 13, and the 3 layers of the second conductive metal oxide layer 12 were performed by heat treatment at 260 ℃ for 1 hour.
In the contact hole 45 shown in fig. 3, the pixel electrode 9 which is ITO is in contact with the drain electrode 37 (conductive wiring) which is the upper layer of the second conductive metal oxide layer 12. The ITO and second conductive metal oxide layers forming the pixel electrode 9 are made of similar conductive metal oxides, and can be ohmic-contacted. In the configuration shown in fig. 3, it is difficult to make ohmic contact when the surface in contact with the pixel electrode 9 in the contact hole 45 is an oxidized copper surface or aluminum. The physical adhesion of ITO to aluminum is also insufficient. The novel structure employed in the semiconductor device according to the embodiment of the present invention can provide a wiring structure capable of making ohmic contact in this manner.
In the structure of the thin film transistor 39 shown in fig. 3, a semiconductor interface 30 in which the channel layer 35 is in contact with the source electrode 36 and a semiconductor interface 30 in which the channel layer 35 is in contact with the drain electrode 37 are formed. In particular, in the semiconductor interface 30, a conductive metal oxide having low contact resistance and high mobility is substantially formed on the electrode side (source electrode side, drain electrode side) of the channel layer 35. As a result, transistor characteristics can be improved. In fig. 3, the first conductive metal oxide layer 11 functions as a semiconductor layer having low resistance and high mobility. In a second embodiment described later, the second conductive metal oxide layer 12 functions as a semiconductor layer having low resistance and high mobility.
(oxide semiconductor)
The oxide semiconductor is a composite oxide containing indium oxide and antimony oxide as main materials. The oxide semiconductor may be formed with a composition of only indium oxide and antimony oxide, but oxygen deficiency is likely to occur in an oxide semiconductor having such a composition. In order to reduce oxygen deficiency of the oxide semiconductor, zirconium oxide, hafnium oxide, scandium oxide, yttrium oxide, lanthanum oxide, cerium oxide, neodymium oxide, samarium oxide, and gallium oxide are preferably further added to the oxide semiconductor as a stabilizer for an oxidation state. For reasons described later, cerium oxide is particularly preferred.
As an example of the oxide semiconductor according to the embodiment of the present invention, a case where cerium oxide is used as an oxidation stabilizer will be described.
The oxide semiconductor according to the embodiment of the present invention contains indium oxide and antimony oxide as main materials, and cerium oxide as an oxidation stabilizer. In the oxide semiconductor, when the total of the elements excluding oxygen is set to 100 atomic%, for example, the content of each of indium and antimony is in a range of 45 atomic% or more and 49.8 atomic% or less, and the content of cerium is in a range of 10 atomic% or less and 0.4 atomic% or more.
In the embodiment of the present invention, the "host material" refers to indium oxide and antimony oxide, and refers to a composite oxide in which the total of elements excluding oxygen in the oxide semiconductor is 100 atomic% and the content of indium and antimony is 40 atomic% or more, respectively.
On the other hand, when gallium is used as an oxidation stabilizer, for example, if the content of gallium is less than 0.4 atomic%, oxygen deficiency of the oxide semiconductor cannot be sufficiently compensated. When the content exceeds 10 atomic%, the composite oxide target as a starting material is reduced in conductivity, and it is difficult to form a film by DC (direct current) sputtering.
The oxide semiconductor according to the embodiment of the present invention can be crystallized by low-temperature annealing at 180 to 340 ℃ which improves the resistivity of the copper alloy layer. In other words, according to the embodiment of the present invention, a composite oxide having a low crystallization temperature can be provided. In order to confirm whether or not the oxide semiconductor is crystallized, crystal grains at least greater than 3nm can be observed by an observation method such as TEM after low-temperature annealing. However, since the thickness of the channel layer used in the thin film transistor is selected from an extremely thin range of 3nm to 80nm, it is difficult to confirm a clear crystallization. In the oxide semiconductor according to the embodiment of the present invention including indium oxide and antimony oxide as main materials, even when no significant crystallization is observed after the low-temperature annealing, a thin film transistor having stable semiconductor characteristics can be provided by the low-temperature annealing. An etch stop layer may also be formed on the surface of the channel layer corresponding to the channel length L shown in fig. 3. The low temperature anneal is preferably performed in the atmosphere or in an oxygen-containing ambient gas.
In general, an oxide semiconductor of indium oxide, gallium oxide, or zinc oxide called IGZO is required to be annealed at a high temperature of 400 to 700 ℃ for crystallization.
However, annealing at a temperature exceeding 350 ℃ may promote copper diffusion and, in some cases, deteriorate the characteristics of the oxide semiconductor. In the conventional structure in which the copper wiring is Mo/Cu or Ti/Cu, interdiffusion of copper and titanium or the like may occur under heat treatment at a temperature exceeding 400 ℃, and the resistivity of the copper wiring may be deteriorated. Indium oxide has a melting point of 1910 ℃, gallium oxide has a melting point of 1740 ℃, zinc oxide has a melting point of 1980 ℃, and in any case, the melting point is a high temperature region of 1700 ℃ or higher. Therefore, it is presumed that the crystallization temperature of the composite oxide is also high. Compared to such high melting point oxides, antimony oxide has a melting point of 656 ℃. The crystallization temperature of an inorganic oxide is empirically 1/2 or 2/3 of the melting point of its oxide. However, the crystallization temperature of an ITO film (transparent conductive film formed of a composite oxide of indium oxide and tin oxide) or an indium oxide film containing about 10Wt% of tin oxide is around 200 ℃. Therefore, by forming a composite oxide (oxide semiconductor) containing antimony oxide and indium oxide having low melting points, the crystallization temperature of the composite oxide can be reduced. Note that, the melting point of the oxide is described in the fourth edition of the physical and chemical dictionary of rock wave (rock wave bookstore).
The composition of the oxide semiconductor of the embodiment of the present invention may be such that indium oxide and antimony oxide are about 1:1. The ratio of indium oxide to antimony oxide may vary by 20%, but is preferably close to 1 as an oxide semiconductor: 1. Antimony oxide is easily sublimated in vacuum film formation (sputtering) using a composite oxide target containing antimony oxide. Therefore, in the composition of the composite oxide target as a starting material, by making antimony oxide rich as a film of a vacuum-formed composite oxide, the ratio of indium oxide to antimony oxide can be made close to 1:1.
although the oxide semiconductor may be formed of only indium oxide and antimony oxide, an oxide semiconductor having such a composition is prone to oxygen deficiency. In order to reduce oxygen deficiency of the oxide semiconductor, cerium oxide is preferably added as a stabilizer for the oxidation state. The oxide semiconductor according to the embodiment of the present invention contains indium oxide and antimony oxide as main materials, and cerium oxide as an oxidation stabilizer. When the total of the elements excluding oxygen is set to 100 atomic% in the oxide semiconductor, the respective contents of indium and antimony are in the range of 45 atomic% to 49.8 atomic%, and the content of cerium is in the range of 10 atomic% to 0.4 atomic%. When the content of cerium is less than 0.4 atomic%, oxygen deficiency cannot be sufficiently compensated. When the content of cerium exceeds 10 atomic%, it becomes difficult to crystallize at an annealing temperature of 340 ℃ or lower. Alternatively, the conductivity of the composite oxide target having a cerium content exceeding 10 at% is greatly reduced, and direct current sputtering is difficult.
As a composite oxide target used for forming the channel layer formed of the oxide semiconductor, a sputtering target having a high conductivity and further containing tin oxide having a valence different from that of indium oxide and antimony oxide as a carrier dopant may be used.
Cerium (Ce) oxide (CeO) is produced by utilizing the characteristic that the oxidation state of 4f1-Ce (III) and the oxidation state of 4f0-Ce (IV) are easily converted to each other 2 ) Is used as a catalyst for automobile exhaust gas treatment and the like. In other words, ceO 2 Ce of (2) 4+ With Ce 3+ The oxidation-reduction potential difference is small and the oxidation-reduction reaction is liable to occur reversibly. For example, oxygen is easily taken in an oxidizing atmosphere and oxygen is easily released in a reducing atmosphere. The interconversion may be schematically represented, for example, by the following formula.
CeO 2 ＜＝＞CeO 2-x +“Ox”
"Ox" may also be referred to as a strong oxidizing superoxide.
In addition, ceO is expected as a behavior in the composite oxide 2 Excess electrons (carriers) can be taken in. Therefore, it is easy to prevent the electron concentration of the oxide semiconductor film from becoming excessive. In the embodiment described later, 9×10 is obtained 17 cm -3 An n-type semiconductor having the following electron concentration.
The oxide semiconductor according to the embodiment of the present invention is a composite oxide of indium oxide, antimony oxide, and cerium oxide. For example, in the case of sputtering vacuum film formation using a target composed of such a composite oxide, an oxide semiconductor film with little oxygen loss can be obtained by introducing a certain amount of oxygen into an argon base gas. For example, by annealing at 180 to 340 ℃ in the atmosphere, an oxide semiconductor film having further reduced oxygen loss and high acid resistance can be obtained. In vacuum film formation, the substrate temperature may be set to room temperature (for example, 25 ℃) to form a pattern of an oxide semiconductor film serving as a channel layer, and then annealing may be performed.
The oxide semiconductor may be formed as the channel layer 35 of the thin film transistor as described above. As an insulating layer material functioning as the gate insulating film (the second insulating layer 42) which is in contact with the channel layer 35, an insulating layer or the like obtained by mixing hafnium silicate (HfSiOx), silicon oxide, aluminum oxide, silicon nitride oxide, aluminum nitride oxide, titanium oxide, zirconium oxide, gallium oxide, zinc oxide, hafnium oxide, cerium oxide, lanthanum oxide, samarium oxide, or a mixture of these materials is used.
Cerium oxide has a high dielectric constant and bonds between cerium and oxygen atoms. Therefore, as the gate insulating layer, a composite oxide containing cerium oxide is preferably used. When cerium oxide is used as one of the oxides constituting the composite oxide, a high dielectric constant is easily maintained even in an amorphous state. The cerium oxide has an oxidizing power. Cerium oxide is capable of oxygen storage and release. Therefore, by adopting a structure in which the oxide semiconductor (channel layer) is in contact with the cerium oxide (gate insulating film), oxygen can be supplied from the cerium oxide to the oxide semiconductor, oxygen loss of the oxide semiconductor can be avoided, and a stable oxide semiconductor (channel layer) can be realized. In a structure in which a nitride such as SiN is used for the gate insulating layer, the above-described action is hardly exhibited. The material of the gate insulating layer (second insulating layer 42) may contain a lanthanide metal silicate typified by cerium silicate (CeSiOx). Or may further contain lanthanum-cerium composite oxide, lanthanum-cerium silicate, further cerium oxide nitride, and cerium oxide.
As a structure of the gate insulating layer, a single layer film, a mixed film, or a multilayer film can be used. When a mixed film or a multilayer film is used, the mixed film or the multilayer film may be formed using a material selected from the above insulating layer materials. The film thickness of the gate insulating layer is, for example, a film thickness that can be selected from a range of 2nm to 300 nm. When the channel layer is formed using an oxide semiconductor, an interface of the gate insulating film in contact with the channel layer 35 can be formed in a state where oxygen is contained in a large amount (film formation ambient gas), and oxygen loss in the oxide semiconductor layer (channel layer 35) can be reduced.
In order to obtain an effect of planarizing the upper surface of the insulating layer (the third insulating layer 43) covering the thin film transistor 39, an insulating layer of which part is an acrylic resin, a polyimide resin, a benzocyclobutene resin, a polyamide resin, a polyimide resin, or the like can be used. Low dielectric constant materials (low-k materials) may also be used.
(composite oxide sputtering target)
The composite oxide sputtering target is used by being bonded to the backing plate 206 in the device configuration of the sputtering device 200 shown in fig. 5, for example. As the sputtering target 207 shown in fig. 5, a composite oxide sputtering target used for film formation of an oxide semiconductor is used, whereby a composite oxide can be formed on the substrate 208 (the first substrate 1 and the second substrate 2).
The composite oxide sputtering target will be described below.
The following description of the method for producing a sputtering target is also applicable to a composite oxide sputtering target used for the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12.
The composite oxide sputtering target according to the embodiment of the present invention contains indium oxide (In 2 O 3 ) And antimony oxide (Sb) 2 O 3 ) And contains cerium oxide (CeO) 2 ) As an oxidation stabilizer that is less likely to cause oxygen deficiency of the composite oxide. Here, "host material" means that indium oxide and antimony oxide are contained in a larger proportion than cerium oxide.
The composite oxide sputtering target used for forming an oxide semiconductor according to the present invention has a total of elements excluding oxygen in the oxide semiconductor of 100 atomic%, for example, a content of indium and antimony of 45 atomic% or more and 49.8 atomic% or less, and a content of cerium of 10 atomic% or less and 0.4 atomic% or more.
The composite oxide sputtering target contains indium and antimony as main materials, and the respective contents of indium and antimony are at least 40 at% when the total of the elements excluding oxygen is set to 100 at%. Tin oxide (SnO) 2 ) Or titanium oxide (TiO) 2 ) The iso-oxide is added as a carrier dopant in the composite oxide sputter target. For example, the conductivity of the sputtering target can be adjusted by adding tin oxide or titanium oxide in an amount of 0.2 atomic% or more and 5 atomic% or less.
As a method for producing the composite oxide sputtering target according to the embodiment of the present invention, indium oxide powder (purity: 99.99%), antimony oxide powder (purity: 99.9%) and cerium oxide powder (purity: 99.9%) can be mixed, molded, and sintered to produce the composite oxide sputtering target. The present invention is not limited to this manufacturing method. The sintering may be performed, for example, under normal pressure in an oxygen-containing atmosphere at a temperature ranging from 800 to 1600 ℃. At a high temperature exceeding 1600 ℃, antimony oxide may evaporate, and thus 1600 ℃ or lower is preferable. Below 800 ℃, a sufficient density as a target may not be obtained.
The above-mentioned powders (indium oxide powder, antimony oxide powder, and cerium oxide powder) were dispersed in a slurry together with pure water by a wet method, and then granulated, molded, and rapidly dried. Thereafter, pressing (e.g., cold pressing) is performed. Further, the mixture was sintered at the above sintering temperature for several tens of hours to obtain a sintered body.
The sintered body is polished by a surface grinder, and further polished by a diamond grindstone or the like. The sintered body after finishing the fine polishing is bonded to a copper back plate with a low melting point metal such as indium as a bonding metal. Thus, a composite oxide sputtering target can be obtained.
Such a composite oxide sputtering target is set in the sputtering apparatus 200, and sputtering film formation is performed, whereby an oxide semiconductor having the above-described composition can be formed. The film formation method using such a composite oxide sputtering target can be applied to a second embodiment described later.
(formation of a Circuit Using a thin film transistor)
The resistive element can be formed by patterning the conductive metal oxide layer or the film of the oxide semiconductor in such a manner as to have a desired pattern. In addition, for example, when a semiconductor device (thin film transistor) is formed on the second substrate 2 (for example, in the case of the second embodiment described later), a plurality of thin film transistors (active elements) using a polysilicon semiconductor may be formed in a matrix form as channel layers, and then, through via holes formed in an insulating layer, a matrix of thin film transistors (active elements) using an oxide semiconductor as channel layers may be stacked.
In a known technique using a resistor element or an n-type thin film transistor, an inverter circuit or an SRAM can be configured. Also, a logic circuit such as a ROM circuit, a NAND circuit, a NOR circuit, a flip-flop, a shift register, or the like may be configured. Since the oxide semiconductor has extremely low leakage current, a circuit with low power consumption can be formed. Oxide semiconductors are used as power semiconductors because of their high electrical withstand voltage. In addition, since the memory (voltage holding property) is not provided by the silicon semiconductor, a good memory element can be provided. Alternatively, the memory element or the logic circuit may be formed by a stacked structure in which a matrix of active elements including a polysilicon semiconductor as a channel layer is formed in a first layer and a matrix of active elements including an oxide semiconductor as a channel layer is formed in a second layer over different substrates. The circuit formed over the different substrates may be attached to the semiconductor device according to the embodiment of the present invention or may be stacked in multiple layers.
As shown in a second embodiment described below, the display device according to the embodiment of the present invention may be provided with a touch sensing function. Alternatively, the second substrate 2 facing the first substrate 1 (array substrate) including the thin film transistor for driving the liquid crystal layer or the organic electroluminescent layer may be provided with a touch sensing function. In other words, a touch sensor control circuit for controlling touch sensing may be formed using the second substrate 2 as a touch panel, and further using the above-described resistive element or n-type thin film transistor on the second substrate 2.
The semiconductor device according to the embodiment of the present invention can be used as an active element for driving a Liquid Crystal (Liquid Crystal), a light emitting diode (LED: light Emitting Diode), or an organic EL (OLED: organic Light Emitting Diode), for example. Further, the semiconductor device according to the embodiment of the present invention can be applied to an active element that drives an EMS (Electro Mechanical System ) element, an MEMS (Micro Electro Mechanical System, microelectromechanical system) element, an IMOD (Interferometric Modulation ) element, and an RFID (Radio Frequency Identification, radio frequency identification) element. In addition, the semiconductor device according to the embodiment of the invention is also applicable to a touch sensor control circuit that controls touch sensing.
The active elements are electrically connected by the conductive wiring having low resistivity according to the embodiment of the present invention, whereby a circuit having less passivation of an electric signal and low power consumption can be formed. Passivation of an electrical signal refers to collapse or delay of the waveform of the input signal.
In the case of forming a thin film transistor as a driving organic EL layer or a liquid crystal layer, for example, the semiconductor device according to the embodiment of the present invention can make substantially complete ohmic contact with ITO of a pixel electrode (or a driving electrode) in a contact hole exposed on the surface of a conductive metal oxide layer. The ohmic contact contributes to improvement of semiconductor characteristics and reduction of power consumption. In general, a thin film transistor is often configured such that a high-melting-point metal layer such as molybdenum or titanium is in contact with ITO of a pixel electrode. These refractory metals have difficulty in electrical contact due to the formation of metal oxides on the surface. In addition, the ohmic contact between ITO and aluminum is not performed, and the adhesion between aluminum and ITO is also insufficient.
In addition, when a conventional Cu/Ti 2-layer structure or a Ti/Cu/Ti 3-layer structure is used as the structure of the conductive wiring, hydrogen which is easily contained in the Ti layer tends to adversely affect the oxide semiconductor. Specifically, hydrogen released from the Ti layer may change the channel length of the thin film transistor, thereby changing the transistor characteristics. The conductive wiring according to the embodiment of the present invention has a structure in which the Ti layer and the copper alloy layer are sandwiched between the conductive metal oxide layers, and thus has little adverse effect due to hydrogen.
Further, the metal wiring of Ti or Mo on the surface layer is liable to form titanium oxide or molybdenum oxide on the surface thereof. When a schottky barrier is formed in electrical connection in a contact hole, a threshold voltage (Vth) of a transistor may be adversely affected.
In contrast, the conductive wiring according to the present embodiment does not have such adverse effects.
(second embodiment)
Next, a second embodiment of the present invention will be described with reference to the drawings.
The display device DSP2 according to the second embodiment of the present invention will be described below with reference to fig. 6 to 13.
In the second embodiment, the characteristic portions will be described, and for example, portions where the constituent elements used in the normal display device are not different from the display device of the present embodiment will be omitted.
The display device DSP2 includes: a switching transistor 89 having the same structure as the thin film transistor 39; a driving transistor 139 (thin film transistor) controlled by the switching transistor 89; and an organic EL layer driven by the driving transistor 139. The display device DSP2 has a touch sensing function using an In-Cell system. Here, the "In-Cell system" refers to a display device In which a touch sensing function is built In the display device or a display device In which a touch sensing function is integrated with the display device. As a technical term used in the present invention, the term "touch sensing" as an adjective may be simply referred to as "touch".
(functional constitution of display device DSP 2)
Fig. 6 is a block diagram showing a control unit (an image signal control unit, a system control unit, and a touch sensor control unit) and a display unit constituting a display device DSP2 including a semiconductor device according to a second embodiment of the present invention.
As shown in fig. 6, the display device DSP2 of the present embodiment includes a display unit 110 and a control unit 120 for controlling the display unit 110 and the touch sensing function.
The control unit 120 has a known configuration and includes an image signal control unit 121 (first control unit), a touch sensor control unit 122 (second control unit), and a system control unit 123 (third control unit). Antenna units 81 to 84 are provided between the touch sensor control unit 122 and the system control unit 123.
As described later, the switching transistor 89 (see fig. 10), the driving transistor 139 (see fig. 8 and 10), and the organic EL layer are provided for each of the plurality of pixels constituting the display portion 110.
The image signal control unit 121 supplies a signal to a gate wiring (hereinafter referred to as a scanning line) and a source wiring (hereinafter referred to as a signal line) provided on the array substrate 300 while setting an upper electrode (common electrode) provided on the array substrate 300 (first substrate 1) to a constant potential, and supplies a driving voltage (electric power) for driving the organic EL layer to the power supply line 140 (see fig. 8 and 10). The image signal control section 121 drives the driving transistor 139 by selecting the switching transistor 89. The driving voltage is applied to the organic EL layer by the driving transistor 139, and the organic EL layer emits light on the array substrate 300, thereby displaying an image on the array substrate 300.
The touch sensor control unit 122 applies a touch sensor drive voltage to the touch sensor drive wiring, detects a change in electrostatic capacitance generated between the touch sensor drive wiring and the touch sensor detection wiring, and performs touch sensing. The touch sensing control unit 122 includes a power receiving unit 15, a power supply control unit 16, a touch drive control unit 17, a touch drive switch circuit 18, a touch detection switch circuit 19, a touch signal transmission/reception control unit 20, and a detection/AD conversion unit 130, which will be described later.
The system control unit 123 controls the image signal control unit 121 and the touch sensor control unit 122, and can alternately, that is, time-division, detect light emission of the organic EL layer and change in electrostatic capacitance. The system control unit 123 may have a function of causing the organic EL layer to emit light at a frequency different from the touch-sensing driving frequency or at a different voltage.
In the system control unit 123 having such a function, for example, it is also possible to detect the frequency of noise from the external environment picked up by the display device DSP2, and select a touch sensing driving frequency different from the noise frequency. Thereby, the influence of noise can be reduced. In addition, the system control unit 123 may select a touch sensing drive frequency corresponding to the scanning speed of the pointer such as a finger or a pen.
In the display device DSP2 having the configuration shown in fig. 6, the control section 120 has both a function of applying a display driving voltage to the lower electrode 88 to cause the organic EL layer to emit light and a touch sensing function of detecting a change in electrostatic capacitance generated between the touch sensing driving wiring and the touch sensing detecting wiring. The touch sensing wiring according to the embodiment of the present invention can be formed of a conductive wiring having good conductivity, and thus can reduce the resistance value of the touch sensing wiring and improve the touch sensitivity.
The control unit 120 preferably has a function of performing touch sensing driving during at least one of a stable period of image display and a stable period of black display after image display.
Fig. 7 is a sectional view partially showing a display device DSP2 including a semiconductor device according to a second embodiment of the present invention.
Fig. 8 is a cross-sectional view partially showing an array substrate (first substrate) constituting the display device DSP2 according to the second embodiment of the present invention, and is a diagram illustrating an active element and a light-emitting layer of an organic EL formed on the array substrate.
As shown in fig. 7 and 8, the display device DSP2 is an organic electroluminescence (hereinafter, referred to as organic EL) display device in which an array substrate 300 (first substrate 1) and a display device substrate 100 (second substrate 2) are bonded to each other through a transparent resin layer 97 as an adhesive layer.
In the display device DSP2 according to the embodiment of the present invention, the display functional layers are the light-emitting layer 92 (organic EL layer) and the hole injection layer 91. The first substrate 1 is provided with a switching transistor 89 and a driving transistor 139 (see fig. 8 and 10). The switching transistor 89 selected by the image signal control section 121 supplies a switching signal to the driving transistor 139, whereby the driving transistor 139 drives the light emitting layer 92.
The structure of the display device DSP2 in plan view is the same as the display device DSP1 of the first embodiment, and the shape of the pixel opening 14 is substantially the same as the first embodiment. As in the first embodiment, color filters such as red pixels R, green pixels G, and blue pixels B may be disposed in the pixel opening 14.
As in the first embodiment, the display device DSP2 includes thin film transistors using an oxide semiconductor as a channel layer, that is, the switching transistor 89 and the driving transistor 139, and further includes conductive wirings in which the copper alloy layer 13 is sandwiched by conductive metal oxide layers. The display device DSP2 shown in fig. 7 has a display device substrate 100 having touch sensing wiring, and has a touch sensing function.
(Cross-sectional Structure of display device substrate)
As shown in fig. 7, a black matrix BM having an effective display area 71 having a rectangular shape and a frame area 72 surrounding the effective display area 71 is provided on the second substrate 2 of the display device substrate 100 as described later.
A lower insulating layer 141 is provided on the black matrix BM, and a first conductive wiring 21 (fifth conductive wiring 55) is provided on the lower insulating layer 141. On the lower insulating layer 141, an intermediate insulating layer 142 (gate insulating layer) is provided so as to cover the first conductive wiring 21. The second conductive wiring 22 (sixth conductive wiring 56) is provided on the intermediate insulating layer 142. An upper insulating layer 143 is provided on the intermediate insulating layer 142 so as to cover the second conductive wiring 22. A transparent resin layer 97 is provided on the upper insulating layer 143, and the transparent resin layer 97 bonds the display device substrate 100 and the array substrate 300.
In addition, a circuit such as the touch drive switch circuit 18 is formed on the lower insulating layer 141 using a thin film transistor or the like, instead of forming the black matrix BM on a part of the frame region 72. The formation of such a circuit is the same as the first embodiment. The insulating layer formed on the second substrate 2 may be formed of a resin, or may be formed of silicon oxide, silicon nitride, or the like as necessary.
(Cross-sectional Structure of array substrate)
As shown in fig. 7 and 8, a first insulating layer 41, a second insulating layer 42, and a third insulating layer 43 are stacked on the first substrate 1. The first insulating layer 41 is provided with a driving transistor 139. The driving transistor 139 includes a channel layer 135, a source electrode 136, a drain electrode 137, and a gate electrode 138, and has a so-called top gate structure. The channel layer 135 has the same structure as the channel layer 35 of the first embodiment, and is formed of an oxide semiconductor. The source electrode 136, the drain electrode 137, and the gate electrode 138 are formed of conductive wirings having the same wiring structure as the source electrode 36, the drain electrode 37, and the gate electrode 38 in the first embodiment. In addition, as in the first embodiment, a semiconductor interface 30 is formed at the interface between the channel layer 135 and the source electrode 136 and the interface between the channel layer 135 and the drain electrode 137.
Although not shown in fig. 7 and 8, a switching transistor 89 (see fig. 10) for supplying a switching signal to the driving transistor 139 is provided on the first substrate 1. The switching transistor 89 has the same configuration as the thin film transistor 39 of the first embodiment. The drain electrode of the switching transistor 89 is not connected to the pixel electrode but to the gate electrode 138 of the driving transistor 139.
The source electrode 136 of the driving transistor 139 is connected to a power supply line 140. The power supply line 140 has 3 layers in which the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12. The power supply line 140 and the source electrode 136 have the same conductive wiring structure and are formed as the same layer.
The gate electrode 138 of the driving transistor 139 is connected to the drain electrode of the switching transistor 89. Accordingly, the driving of the driving transistor 139 is controlled by a switching signal output from the drain electrode of the switching transistor 89.
A holding capacitor (not shown) for maintaining the potential of the gate electrode 138 is provided on the gate electrode 138. The holding capacitance is formed between the gate electrode 138 and the power supply line 140.
Even in the connection structure between the drain electrode and the gate electrode 138 of the switching transistor 89 and the electrode or wiring constituting the storage capacitor, the conductive wiring having the 3-layer structure described in the first embodiment is applied.
A source wiring 67 (third conductive wiring 23) connected to a source electrode 36 constituting the switching transistor 89 and a power supply line 140 connected to a source electrode 136 constituting the driving transistor 139 are provided on the first insulating layer 41. On the first insulating layer 41, the second insulating layer 42 is formed so as to cover the first insulating layer 41, the source wiring 67, the source electrode 136, the power supply line 140, and the drain electrode 137. A gate wiring 69 (fourth conductive wiring 24) connected to the gate electrode 38 constituting the switching transistor 89 and a gate electrode 138 constituting the driving transistor 139 are provided over the second insulating layer 42. In the array substrate 300, the gate electrode 138 is arranged so as to face the channel layer 135. A third insulating layer 43 is formed on the second insulating layer 42 so as to cover the second insulating layer 42, the gate wiring 69, and the gate electrode 138. A planarization layer 96 is formed on the third insulating layer 43. The channel layer 135 is formed of an oxide semiconductor. The source wiring 67 and the third conductive wiring 23 have the same conductive wiring structure and are formed as the same layer. The gate wiring 69 and the fourth conductive wiring 24 have the same conductive wiring structure and are formed as the same layer.
In the planarizing layer 96, a contact hole 93 is formed at a position corresponding to the drain electrode 137 constituting the driving transistor 139. Further, a bank 94 is formed on the planarizing layer 96 at a position corresponding to the channel layer 135. In a region between adjacent banks 94 in a cross-sectional view, that is, in a region surrounded by the banks 94 in a plan view, a lower electrode 88 (pixel electrode) is formed so as to cover an upper surface of the planarizing layer 96, an inside of the contact hole 93, and the drain electrode 137. The lower electrode 88 may not be formed on the upper surface of the bank.
Further, a hole injection layer 91 is formed so as to cover the lower electrode 88, the bank 94, and the planarizing layer 96. A light-emitting layer 92, an upper electrode 87, and a sealing layer 109 are sequentially stacked on the hole injection layer 91. The lower electrode 88 has a structure in which a silver or silver alloy layer is sandwiched between conductive metal oxide layers.
As a material of the bank 94, an organic resin such as an acrylic resin, a polyimide resin, and a novolac phenol resin can be used. An inorganic material such as silicon oxide or silicon oxynitride may be further laminated on the banks 94.
As a material of the planarizing layer 96, an acrylic resin, a polyimide resin, a benzocyclobutene resin, a polyamide resin, or the like can also be used. Low dielectric constant materials (low-k materials) may also be used.
In addition, in order to improve visibility, either the planarizing layer 96 or the sealing layer 109, or the substrate may have a light scattering function. Alternatively, a light scattering layer may be formed on the visible side of the observer OB above the array substrate 300.
(planar Structure of display device substrate)
Fig. 9 is a view of the display device according to the second embodiment of the present invention as seen from the observer OB, and is a plan view showing circuits such as the first conductive wiring, the second conductive wiring, the first antenna unit, the second antenna unit, and the control unit formed on the display device substrate (second substrate). Fig. 9 is a plan view of the display device substrate 100 from the observer OB, and shows the components of the display device substrate 100 so as to see through the black matrix BM having light-shielding properties.
As shown in fig. 9, the first conductive wiring 21, the second conductive wiring 22, the first antenna unit 81, the second antenna unit 82, the power receiving unit 15, the power supply control unit 16, the touch drive control unit 17, the touch drive switch circuit 18, the touch detection switch circuit 19, the touch signal transmission/reception control unit 20, and the detection/AD conversion unit 130 are provided on the second substrate 2 (on the surface facing the array substrate 300) of the display device substrate 100. Surrounding wiring electrically connecting circuits such as the first antenna unit 81, the second antenna unit 82, the touch drive switch circuit 18, and the touch detection switch circuit 19 uses a part of the first conductive wiring 21 and a part of the second conductive wiring 22.
The black matrix BM has an effective display area 71 having a rectangular shape and a frame area 72 surrounding the effective display area 71. The power receiving unit 15, the power supply control unit 16, the touch drive control unit 17, the touch drive switch circuit 18, the touch detection switch circuit 19, the touch signal transmission/reception control unit 20, the detection/AD conversion unit 130, and the like shown in fig. 9 refer to "a circuit for controlling touch sensing" in the present invention. In addition, a part of the first conductive wiring 21, a part of the second conductive wiring 22, and the first active element constitute a circuit that controls touch sensing. The power receiving unit 15 smoothes the received voltage and makes the voltage constant, and outputs the smoothed received voltage to the power supply control unit 16 as a touch drive voltage.
The first conductive wiring 21, the second conductive wiring 22, the first antenna unit 81, the second antenna unit 82, the touch signal transmission/reception control unit 20, the touch driving switch circuit 18, the touch detection switch circuit 19, and the like may not necessarily be disposed on the black matrix BM. In this case, for example, the first conductive wiring 21 and the second conductive wiring 22 may be formed as touch sensing wiring on the black matrix BM in the effective display area, and the touch signal transmission/reception control unit 20, the touch driving switch circuit 18, the touch detection switch circuit 19, and the like may be formed on the glass surface on the outer side of the frame where the black matrix BM is not formed. Further, a part of the first conductive wiring 21 and the second conductive wiring 22 may be applied in a 2-layer conductive wiring structure of the first antenna unit 81 or the second antenna unit 82 through the lower insulating layer 141. The first antenna unit 81 and the second antenna unit 82 include loop antenna pairs having winding directions opposite to each other and having winding numbers of 2 or more.
A plurality of first touch sensing wires (first conductive wires 21) extending in the X direction (first direction) and a plurality of second touch sensing wires (second conductive wires 22) extending in the Y direction (second direction) are provided on a surface of the second substrate 2 opposite to the first substrate 1. The first conductive wiring 21 and the second conductive wiring 22 have the 3-layer structure described above.
An intermediate insulating layer 142, which is a transparent resin, is disposed between the first touch sensing wire and the second touch sensing wire. The touch sensing wiring according to the embodiment of the invention is a conductive wiring in which a copper alloy layer is sandwiched by conductive metal oxide layers.
These touch sensing wires include a thin film transistor using an oxide semiconductor as a channel layer, and fifth conductive wires 55 and sixth conductive wires 56 as constituent elements of a circuit for controlling touch sensing. Further, the fifth conductive wiring 55 and the first touch sensing wiring (first conductive wiring 21) are the same conductive wiring structure and are formed as the same layer. The sixth conductive wiring 56 and the second touch sensing wiring (second conductive wiring 22) are the same conductive wiring structure and are formed as the same layer.
(planar Structure of array substrate)
Fig. 10 is a plan view showing circuits such as a third antenna element, a fourth antenna element, a source signal switching circuit, a gate signal switching circuit, a driving transistor 139 for driving an organic EL, and a switching transistor 89 for driving the driving transistor 139, which are formed on an array substrate (first substrate) constituting a display device according to the second embodiment of the present invention.
As shown in fig. 10, circuits such as the third antenna element 83, the fourth antenna element 84, the source signal switching circuit 26, the gate signal switching circuit 27, the power transmission unit 28, the signal transmission/reception unit 29, and the like, and FPCs are provided on the first substrate 1 of the array substrate 300 (on the surface facing the display device substrate 100). The array substrate 300 is provided with a switching transistor 89 and a driving transistor 139 functioning as thin film transistors at positions corresponding to the pixel openings 14. The third antenna element 83 and the fourth antenna element 84 include loop antenna pairs having winding directions opposite to each other and having winding numbers of 2 or more.
The source signal switching circuit 26, the gate signal switching circuit 27, the power transmitting unit 28, the signal transmitting/receiving unit 29, and other circuits are formed outside the effective display area of the first substrate 1. The power supply for driving these circuits is connected to an external power supply such as 100V through an FPC or a battery or an adapter, not shown.
When the display device substrate 100 and the array substrate 300 are attached, the first antenna unit 81 and the third antenna unit 83 are arranged so as to overlap each other in a plan view (the first overlapping portion 51). The second antenna element 82 and the fourth antenna element 84 are arranged so as to overlap each other in a plan view (the second overlapping portion 52). The first superimposing unit 51 has a function of transmitting and receiving a touch sensor signal, and the second superimposing unit 52 has a function of receiving a power signal. The first antenna unit 81 and the third antenna unit 83 forming the first overlapping portion 51, and the second antenna unit 82 and the fourth antenna unit 84 forming the second overlapping portion 52 are arranged in the frame region 72.
In the example shown in fig. 10, a power supply line 140 extending from the FPC to the surrounding area of the display portion 110 is provided, and the power supply line 140 extends in the X direction in an end outside area (upper side in fig. 10) of the display portion 110 in the Y direction. Further, the power supply line 140 extending in the X direction is branched into a plurality of wirings extending in the Y direction. The power supply line 140 extending in the Y direction is connected to the source electrode 136 of the driving transistor 139 provided on a plurality of pixels arranged also toward the Y direction.
In addition, 1 thin film transistor is shown in each pixel in fig. 10, but the number of thin film transistors is not shown, and as described above, the switching transistor 89 and the driving transistor 139 controlled by the switching transistor 89 are provided in 1 pixel.
When the switching transistor 89 is selected, the image signal control unit 121 supplies a switching signal to the gate electrode 138 of the driving transistor 139 to drive the driving transistor 139. By driving the driving transistor 139, a driving voltage supplied from a power supply line 140 (source wiring of the driving transistor 139) is applied to the lower electrode 88 (pixel electrode) through the source electrode 136 and the drain electrode 137. That is, a driving voltage is applied to the organic EL layer, and the organic EL layer emits light on the array substrate 300, thereby displaying an image on the array substrate 300.
(antenna element)
Next, a specific configuration of the antenna unit will be described with reference to fig. 11 to 13. Here, the antenna unit means 1 or more (in fig. 11, a pair of loop antennas wound in opposite directions) antennas as shown in fig. 11. The antenna is not limited to a loop antenna.
Fig. 11 is a partial plan view showing a first antenna unit formed on a display device substrate 100 constituting a display device DSP2 including a semiconductor device according to a second embodiment of the present invention in an enlarged manner.
Fig. 12 is a view showing a first antenna element formed on a display device substrate 100 constituting a display device DSP2 provided with a semiconductor device according to a second embodiment of the present invention, and is a cross-sectional view taken along line A-A' of fig. 11.
Fig. 13 is a perspective view showing the overlapping of a first antenna unit formed on a display device substrate 100 constituting a display device DSP2 provided with a semiconductor device according to the second embodiment of the present invention and a third antenna unit formed on an array substrate 300.
In the following description, the configuration of the first antenna unit 81 will be described as a representative of the first antenna unit 81, the second antenna unit 82, the third antenna unit 83, and the fourth antenna unit 84, but the same configuration may be adopted for other antenna units. In the following description, the antenna element may be referred to as an "antenna element".
The "antenna unit" of the present invention is a structure in which 1 or more antennas are arranged on a substrate for the purpose of transmitting and receiving a touch sensor signal, receiving and giving electric power, and the like. When the antenna is a loop-shaped antenna (coil formed on the same plane, spiral pattern), the antenna unit is preferably configured such that 2 antennas wound in opposite directions are adjacent to each other, from the viewpoint of securing stability of communication. Alternatively, the antennas wound in opposite directions may be adjacent to each other by 2 or more, and 1 group of antennas may be selected for use.
In the second embodiment, the loop antenna may have a function of communicating with an external antenna of the display device DSP2, for example, an antenna provided in an IC card.
As shown in fig. 13, the first antenna unit 81 of the display device substrate 100 and the third antenna unit 83 of the array substrate 300 have the same loop antenna shape in a plan view, and are aligned and overlapped (first overlapping portion 51). Similarly, the second antenna element 82 of the display device substrate 100 and the fourth antenna element 84 of the array substrate 300 have the same loop antenna shape in a plan view, and are aligned and overlapped (the second overlapping portion 52).
In the first and second stacked portions 51 and 52, the line width of the conductive wiring forming the antenna is, for example, a thin line width of 1 μm to 20 μm, and it is necessary to house the antenna element in the narrow frame region 72, and therefore, it is preferable that the positional accuracy of the antenna is within ±3 μm. When the accuracy of the position matching is improved, the signal can be efficiently transmitted or received. By connecting 2 or more loop antennas in parallel, miniaturization of the antennas and high speed of noncontact data transfer become possible. In fig. 11 to 13, the capacitor or other components for forming the resonant circuits with the first antenna element 81 and the second antenna element 82, and the third antenna element 83 and the fourth antenna element 84, respectively, are not shown.
As a structure of the conductive wiring forming the antenna, for example, a conductive wiring formed of 3 layers in which the copper alloy layer is sandwiched by conductive metal oxide layers can be used. For example, the first antenna element 81 and the second antenna element 82 may be formed in the same layer as the first conductive wiring 21 (or the fifth conductive wiring 55) by the same process. The third antenna element 83 and the fourth antenna element 84 may be formed in the same layer as the third conductive wiring 23 (or the fourth conductive wiring 24) and in the same process.
As shown in fig. 11, each of the first antenna element 81, the second antenna element 82, the third antenna element 83, and the fourth antenna element 84 is formed of a pair of loop antennas wound in opposite directions. The magnetic field generation direction of the loop antenna wound in opposite directions can be reversed, so that stable transmission and reception with less noise generation can be performed. In other words, in the loop antenna wound in opposite directions, by forming magnetic fields having different directions, a shielding effect of an external magnetic field can be obtained, and the influence of external noise can be reduced. The reverse winding means that the winding directions of the pair of loop antennas 164 and 165 shown in fig. 11 are line-symmetric with respect to the center line 116 in a plan view.
The number of windings of the loop antenna is preferably 2 or more or 3 or more. When the outer shape of the antenna is a small size of 5mm or less, the number of winding wires can be 3 or more and 20 or less. In the second embodiment, the number of windings of each of the first antenna element 81, the second antenna element 82, the third antenna element 83, and the fourth antenna element 84 is 3. Here, the planar shape of the loop antenna having a number of windings of 2 or more is a curve that approaches the center along with the spiral on the same plane. An archimedes spiral with substantially equal spacing between the wires can typically be exemplified.
In order to reduce the influence of noise received from the outside (drive circuit, commercial power supply, general 100V external power supply, etc.), in the present embodiment, antenna elements 81, 82, 83, 84 are surrounded on a plane by conductor patterns 25A, 25B having a substantially U-shape as shown in fig. 11 or 13. The line width of the conductive wiring forming the antenna is 6 μm, and the positional accuracy (alignment accuracy) is within ±2 μm. The structure of these conductive wirings is 3 layers in which the copper alloy layer is sandwiched between conductive metal oxide layers, as in the first embodiment.
In the first superimposing section 51 where the first antenna unit 81 and the third antenna unit 83 are superimposed, for example, reception of a touch drive signal from the CPU or transmission of a touch detection signal output from the touch detection switch circuit 19 via the touch signal transmission/reception control section 20 is performed. The touch drive signal drives the touch drive switch circuit 18 via the touch drive control unit 17.
In the overlapping portion (second overlapping portion 52) of the second antenna unit 82 and the fourth antenna unit 84, for example, the second antenna unit 82 receives electric power generated from the fourth antenna unit 84 by electromagnetic wave generation of the resonance frequency. The power receiving unit 15 smoothes the received voltage to a constant voltage, and outputs the smoothed voltage to the power supply control unit 16 as a touch drive voltage.
As shown in fig. 12, a black matrix BM is formed on the second substrate 2, a lower insulating layer 141 is formed on the black matrix BM, and the first antenna element 81 and the second antenna element 82 are formed on the lower insulating layer 141. As shown in fig. 7 and 9, the first conductive wiring 21, the fifth conductive wiring 55, the first antenna element 81, and the second antenna element 82 are formed on the lower insulating layer 141. That is, the first conductive wiring 21, the fifth conductive wiring 55, the first antenna element 81, and the second antenna element 82 are located on the same layer. In addition, the conductor pattern 25A is also formed on the lower insulating layer 141.
More specifically, after the first conductive metal oxide layer 11, the copper alloy layer 13 (or the copper layer), and the second conductive metal oxide layer 12 (the conductive layer formed of 3 layers) are formed on the lower insulating layer 141, the conductive layer formed of 3 layers is patterned by a known photolithography method, whereby the respective patterns of the first conductive wiring 21, the fifth conductive wiring 55, the first antenna element 81, the second antenna element 82, and the conductor pattern 25A are formed. That is, the term "on the same layer" in the present invention means that after forming 3 conductive layers on a substrate, each wiring layer (conductive wiring, antenna element, etc.) is arranged as the same layer by patterning, and means that the wiring, antenna, etc. are arranged on the same layer with the same material and are formed of the same layer.
As described above, the first antenna element 81 and the second antenna element 82 each formed of the conductive wiring (first conductive wiring 21) having the same layer are electrically connected to different conductive wirings (second conductive wiring 22) through the through holes 50 provided in the first connection pads 60 and 61 located inside the antenna. An intermediate insulating layer 142 is present between the first conductive wiring 21 and the second conductive wiring 22.
Similarly, the third antenna element 83 and the fourth antenna element 84, which are formed of conductive wires (third conductive wires 23) having the same layer, are electrically connected to different conductive wires (fourth conductive wires 24) through holes provided in the second connection pads 62 and 63 located inside the antenna, respectively. A second insulating layer 42 is present between the third conductive wiring 23 and the fourth conductive wiring 24.
Each of the first conductive wiring 21 (fifth conductive wiring 55), the second conductive wiring 22 (sixth conductive wiring 56), the third conductive wiring 23, and the fourth conductive wiring 24 has 3 layers in which a copper alloy layer is sandwiched between a first conductive metal oxide layer and a second conductive metal oxide layer.
In the second embodiment, an oxide semiconductor used for the channel layer 35 uses In: sb: ce=1: 1: and (3) carrying out low-temperature annealing at 280 ℃ on the composite oxide with the element ratio of 0.06 to prepare the channel layer. The copper alloy layer of the second embodiment uses Cu: ca: zn=97: 2.5: copper alloy with 0.8 element ratio. After the low-temperature annealing, the resistivity of the copper alloy layer according to the second embodiment was 3.1. Mu. Ω cm.
In the display device DSP2 of the second embodiment, an organic EL layer is used as the light-emitting layer. The present invention is not limited to the configuration shown in the second embodiment. An LED display device including an LED chip may be configured instead of the organic EL layer. For example, as the LED chip, an LED chip called a horizontal type in which an electrode formed of n-type GaN is arranged on the same surface side as an LED reflection electrode is cited. In addition, the LED chip may be directly mounted on the lower electrode 88 as a reflective electrode without forming a layer of the organic EL such as the hole injection layer 91 or the light emitting layer 92 between the banks 94 shown in fig. 8. Conductors may be formed on the back or side of the LED chip to electrically connect the LED chip to the upper electrode 87. At this time, the conductor is in conduction with an electrode derived from n-type GaN. As a method of mounting the LED chip on the substrate, for example, an LED chip having a structure in which n-type GaN/light-emitting layer/p-type GaN/LED reflective electrode (thin film of Ag alloy or the like) is stacked in this order may be mounted on a substrate of sapphire, gaN or the like by face down mounting. At this time, the LED reflection electrode and the lower electrode 88 are electrically bonded. These LED chips can be arranged in the pixel openings between the banks 94 in 3 types of light emission, such as red light emission, green light emission, and blue light emission. Alternatively, blue light emitting LED chips may be mounted in the pixel openings between the banks 94, and wavelength conversion layers including quantum dots and the like may be directly or indirectly disposed in the pixel openings. The wavelength conversion layer converts blue light emission into green light emission or converts blue light emission into red light emission, for example. In addition, a red light emitting LED or an infrared light emitting LED may be mounted in addition to the blue light emitting LED.
According to the above embodiment, a conductive wiring having high conductivity can be formed while having a 3-layer structure in which the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12. Further, a semiconductor device including a thin film transistor electrically connected to the conductive wiring can be realized. Further, a semiconductor device including a minute loop antenna, a touch sensor wiring, or the like, and a display device including such a semiconductor device can be provided.
For example, the semiconductor device or the display device of the above embodiment can be applied to various applications. Examples of the electronic devices to which the display device according to the above embodiment can be applied include mobile phones, portable game machines, portable information terminals, personal computers, electronic books, image sensors, video cameras, digital cameras, head mounted displays, navigation systems, audio reproducing devices (car audio, digital audio players, etc.), copiers, facsimile machines, printers, printer complex machines, vending machines, automated Teller Machines (ATM), personal identification devices, and optical communication devices. The above embodiments can be freely combined.
While the foregoing describes the preferred embodiments of the present invention, these are illustrative of the present invention and should not be construed as limiting the invention. Additions, omissions, substitutions, and other modifications can be made without departing from the scope of the present invention. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.
In the display device DSP1 of the first embodiment, the antenna unit (loop antenna) and the touch sensing wiring shown in the second embodiment may be formed on the second substrate 2. These antenna elements or touch sensing wires may be formed of 3 layers of copper alloy layers sandwiched by a first conductive metal oxide layer and a second conductive metal oxide layer.
Symbol description
1. First substrate
2. Second substrate
3. Semiconductor device with a semiconductor device having a plurality of semiconductor chips
4. Liquid crystal layer
8. Transparent electrode
9. Pixel electrode
11. First conductive metal oxide layer
12. Second conductive metal oxide layer
13. Copper alloy layer
14. Pixel opening
15. Electric power receiving unit
16. Power supply control unit
17. Touch drive control unit
18. Touch drive switch circuit
19. Touch detection switch circuit
20. Touch signal transmission/reception control unit
21. First conductive wiring
22. Second conductive wiring
23. Third conductive wiring
24. Fourth conductive wiring
25A, 25B conductor pattern
26. Source signal switching circuit
27. Gate signal switching circuit
28. Power transmission unit
29. Signal transmitting/receiving unit
30. Semiconductor interface
31. Source wiring
35. 135 channel layer
36. 136 source electrode
37. 137 drain electrode
38. 138 gate electrode
39. Thin film transistor
41. A first insulating layer
42. Second insulating layer
43. Third insulating layer
45. 93 contact hole
50. Through hole
51. A first overlapping part
52. A second overlapping part
55. Fifth conductive wiring
56. Sixth conductive wiring
60. 61 first connection pad
62. 63 second connection pad
67. Source wiring
69. Gate wiring
71. Effective display area
72. Frame region
81. First antenna unit (antenna unit)
82. Second antenna unit (antenna unit)
83. Third antenna element (antenna element)
84. Fourth antenna unit (antenna unit)
87. Upper electrode
88. Lower electrode
89. Switch transistor (thin film transistor)
91. Hole injection layer (organic EL layer)
92. Luminescent layer (organic EL layer)
94. Dyke
96. Planarization layer
97. Transparent resin layer
100. Display device substrate
109. Sealing layer
110. Display unit
116. Center line
120. Control unit
121. Image signal control unit
122. Touch sensing control unit
123. System control unit
130. detection/AD conversion unit
139. Driving transistor (thin film transistor)
140. Power line
141. Lower insulating layer
142. Intermediate insulating layer
143. Upper insulating layer
164. 165 loop antenna
200. Sputtering apparatus
201. Vacuum chamber
202. Support frame
203. Vacuum pump
204. Sputtering gas supply unit
205. Power supply
206. Backboard
207. Sputtering target
208. Substrate board
300. Array substrate
R red pixel
G green pixel
B blue pixel
BM black matrix
OB observer
OC cap coating
DSP1 and DSP2 display device
Claims (7)
1. A semiconductor device is provided with:
a substrate;
a conductive wiring provided on one surface of the substrate; and
a thin film transistor electrically connected to the conductive wiring,
the conductive wiring has 3 layers in which a copper layer or a copper alloy layer is sandwiched between a first conductive metal oxide layer and a second conductive metal oxide layer,
the first conductive metal oxide layer and the second conductive metal oxide layer contain indium oxide,
the thin film transistor has a channel layer composed of an oxide semiconductor,
the oxide semiconductor is a composite oxide containing indium oxide, antimony oxide, and cerium oxide in an amount smaller than the respective amounts of the indium oxide and the antimony oxide,
in the oxide semiconductor, when the total amount of the elements excluding oxygen is set to 100 atomic%, the respective amounts of indium and antimony are 40 atomic% or more,
the copper alloy layer is composed of copper, zinc and calcium, and contains zinc in a range of 0.2 atomic% or more and 5.0 atomic% or less, calcium in a range of 0.2 atomic% or more and 5.0 atomic% or less, and copper as the remainder, assuming that the total of copper, zinc and calcium is 100 atomic%.
2. The semiconductor device according to claim 1, wherein in the oxide semiconductor, when a total of indium, antimony, and cerium which are not counted as 100 atomic%, an amount of each of indium and antimony is in a range of 45 atomic% or more and 49.8 atomic% or less, and an amount of cerium is in a range of 10 atomic% or less and 0.4 atomic% or more.
3. The semiconductor device according to claim 1, wherein the thin film transistor has an insulating film which is in contact with the channel layer and contains at least cerium oxide.
4. The semiconductor device according to claim 1, wherein,
the specific resistance increase rate of the zinc and the calcium when added to copper is 1 mu omega cm/atom% or less,
the specific resistance of the copper alloy layer is in the range of 1.9 mu omega cm-6 mu omega cm.
5. The semiconductor device according to claim 1, wherein the first conductive metal oxide layer and the second conductive metal oxide layer are conductive metal oxides containing indium oxide as a main conductive metal oxide and containing 1 or more kinds selected from antimony oxide, zinc oxide, and gallium oxide.
6. A display device provided with the semiconductor device according to claim 1.
7. The display device according to claim 6,
which comprises an antenna formed by a conductive wiring having 3 layers of a copper layer or a copper alloy layer sandwiched between a first conductive metal oxide layer and a second conductive metal oxide layer,
the first conductive metal oxide layer and the second conductive metal oxide layer contain indium oxide.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2017/020753 WO2018225114A1 (en) | 2017-06-05 | 2017-06-05 | Semiconductor device, display device and sputtering target |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110651370A CN110651370A (en) | 2020-01-03 |
| CN110651370B true CN110651370B (en) | 2023-12-22 |
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| CN201780090747.2A Active CN110651370B (en) | 2017-06-05 | 2017-06-05 | Semiconductor device, display device, and sputtering target |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP6451868B1 (en) |
| KR (1) | KR102370249B1 (en) |
| CN (1) | CN110651370B (en) |
| WO (1) | WO2018225114A1 (en) |
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| KR102218695B1 (en) * | 2018-09-17 | 2021-02-19 | 동우 화인켐 주식회사 | Touch sensor and method of manufacturing the same |
| TWI731683B (en) * | 2020-05-14 | 2021-06-21 | 友達光電股份有限公司 | Circuit of electronic device |
| KR102322045B1 (en) * | 2021-02-19 | 2021-11-05 | 동우 화인켐 주식회사 | Antenna device and display device including the same |
| EP4439679A1 (en) * | 2021-11-26 | 2024-10-02 | Korea Institute of Ceramic Engineering and Technology | Oxide semiconductor, manufacturing method therefor, and semiconductor device comprising same |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2018225114A1 (en) | 2018-12-13 |
| KR20200014275A (en) | 2020-02-10 |
| JP6451868B1 (en) | 2019-01-16 |
| CN110651370A (en) | 2020-01-03 |
| JPWO2018225114A1 (en) | 2019-06-27 |
| KR102370249B1 (en) | 2022-03-04 |
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