CN110649003A - Semiconductor substrate, array substrate, inverter circuit, and switching circuit - Google Patents
Semiconductor substrate, array substrate, inverter circuit, and switching circuit Download PDFInfo
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- CN110649003A CN110649003A CN201810669271.4A CN201810669271A CN110649003A CN 110649003 A CN110649003 A CN 110649003A CN 201810669271 A CN201810669271 A CN 201810669271A CN 110649003 A CN110649003 A CN 110649003A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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Abstract
The invention relates to a semiconductor substrate, which comprises a substrate, a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are arranged on the substrate; the first thin film transistor comprises a first source electrode and a first drain electrode, and the second thin film transistor comprises a second source electrode and a second drain electrode. One of the first source or the first drain is electrically connected with one of the second source or the second drain. The invention also provides an array substrate, an inverter circuit and a switch circuit applying the semiconductor substrate, wherein the semiconductor substrate comprises a metal oxide thin film transistor, and the metal oxide thin film transistor and the low-temperature polycrystalline silicon thin film transistor share a source/drain electrode, so that the volume of an electronic element using the semiconductor substrate and leakage current can be reduced.
Description
Technical Field
The invention relates to a semiconductor substrate, an array substrate, an inverter circuit and a switch circuit.
Background
The flat display device has many advantages of thin body, power saving, no radiation, etc., and is widely used. Conventional flat panel Display devices mainly include Liquid Crystal Displays (LCDs) and Organic electroluminescent devices (OELDs), which are also called Organic Light Emitting Diodes (OLEDs). Generally, an array substrate of a display includes a substrate on which a pixel array including a plurality of pixel units and a driving circuit for driving the pixel array are disposed, and the driving circuit is applied to a thin film transistor. In addition, a peripheral circuit of the display device is also applied to the thin film transistor. The electron mobility of the polysilicon thin film transistor manufactured by using a Low Temperature Polysilicon (LTPS) technology is greater than that of the metal oxide thin film transistor, but the leakage current of the polysilicon thin film transistor is higher than that of the metal oxide thin film transistor, which affects the performance of the array substrate or the peripheral circuit.
Disclosure of Invention
In view of the above, it is desirable to provide a semiconductor substrate with good performance.
A semiconductor substrate comprises a substrate, a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are arranged on the substrate; the first thin film transistor comprises a first grid electrode, a metal oxide semiconductor layer, a first source electrode and a first drain electrode, wherein the first grid electrode and the metal oxide semiconductor layer are arranged on the substrate, and the first source electrode and the first drain electrode are connected with the metal oxide semiconductor layer and are spaced from each other; the second thin film transistor comprises a polycrystalline silicon semiconductor layer, a second grid electrode, a second source electrode and a second drain electrode, wherein the polycrystalline silicon semiconductor layer and the second grid electrode are arranged on the substrate in sequence; one of the first source or the first drain is electrically connected with one of the second source or the second drain.
The invention also provides an array substrate, an inverter circuit and a switch circuit, which comprise the semiconductor substrate.
Compared with the prior art, the semiconductor substrate comprises the metal oxide thin film transistor, and the metal oxide thin film transistor and the low-temperature polycrystalline silicon thin film transistor share the source/drain electrode, so that the volume of an electronic element using the semiconductor substrate and the leakage current can be reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor substrate according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor substrate according to a second embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a semiconductor substrate according to a third embodiment of the invention.
Fig. 4 is a schematic plan view of an array substrate to which an embodiment of the invention is applied.
Fig. 5 is an equivalent circuit diagram of a pixel driving circuit in a pixel unit according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention.
Fig. 7 is an equivalent circuit diagram of an inverter circuit according to an embodiment of the present invention.
Fig. 8 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.
Fig. 9 is an equivalent circuit diagram of a switch circuit according to an embodiment of the invention.
Description of the main elements
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a semiconductor substrate 10 according to a first embodiment of the invention. The semiconductor substrate 10 includes a composite Transistor structure of at least two different types of Thin Film Transistors (TFTs), which are Low Temperature Polysilicon (LTPS) TFTs and Metal Oxide TFTs in this embodiment. The low-temperature polysilicon thin film transistor has the characteristic of high electron mobility, and the Metal Oxide thin film transistor has the characteristics of low leakage current and small volume.
As shown in fig. 1, in the present embodiment, the semiconductor substrate 10 includes a substrate 101, and a first thin film transistor T1 and a second thin film transistor T2 formed on the substrate 101. In this embodiment, the first thin film transistor T1 is a metal oxide thin film transistor, and the second thin film transistor T2 is a low temperature polysilicon thin film transistor.
The first thin film transistor T1 is a Bottom-gate thin film transistor, which includes a buffer layer 103, a first gate electrode 105, a gate insulating layer 107, a first source electrode 109, a first drain electrode 111, and a metal oxide semiconductor layer 113. The buffer layer 103, the first gate electrode 105, and the gate insulating layer 107 are sequentially disposed on the substrate 101. The gate insulating layer 107 is affected by the thickness of the first gate electrode 105, and thus has a convex shape corresponding to the first gate electrode 105. The first source 109 and the first drain 111 are separately disposed on the same layer and are respectively disposed on two opposite sides of the projection of the gate insulating layer 107. The metal oxide semiconductor layer 113 is disposed on the gate insulating layer 107 between the first source electrode 109 and the first drain electrode 111 corresponding to the first gate electrode 105, and partially covers the first source electrode 109 and the first drain electrode 111, respectively. The metal oxide semiconductor layer 113 electrically connects the first source electrode 109 and the first drain electrode 111. In this embodiment, the metal Oxide semiconductor layer 113 is Indium Gallium Zinc Oxide (IGZO). In other embodiments, the metal oxide semiconductor layer 113 may be a metal oxide material containing at least one of zinc, indium, and gallium.
The second thin film transistor T2 is located beside the first thin film transistor T1, and is a Top-gate (Top-gate) thin film transistor, which includes a Poly-silicon (Poly-silicon) semiconductor layer 201, the buffer layer 103, the second gate 205, the gate insulating layer 107, the second source 209, and the second drain 211. The polysilicon semiconductor layer 201, the buffer layer 103, the second gate 205, and the gate insulating layer 107 are sequentially stacked from bottom to top on the substrate 101, and the second gate 205 is disposed corresponding to the polysilicon semiconductor layer 201. The second source 209 is electrically connected to the polysilicon semiconductor layer 201 through a second via 215 penetrating through the buffer layer 103 and the gate insulating layer 107, and the second drain 211 is electrically connected to the polysilicon semiconductor layer 201 through the second via 215 penetrating through the buffer layer 103 and the gate insulating layer 107.
In this embodiment, the buffer layers 103 and 103 are made of an insulating material, such as silicon oxide or silicon nitride. The gate insulating layer 107 includes a first gate insulating layer 1071 and a second gate insulating layer 1072 stacked in this order in a direction away from the substrate 101, that is, the first gate insulating layer 1071 is relatively closer to the substrate 101. The first gate insulating layers 1071 and 1071 are made of silicon oxide, and the second gate insulating layers 1072 and 1072 are made of silicon nitride.
One of the first source 109 or the first drain 111 is electrically connected to one of the second source 209 or the second drain 211. As shown in fig. 1, in the present embodiment, the first drain 111 and the second source 209 are disposed in the same layer and directly connected. In the present embodiment, the first source electrode 109, the first drain electrode 111, the second source electrode 209 and the second drain electrode 211 are patterned from the same conductive layer, and the first drain electrode 111 and the second source electrode 209 are a continuous conductive layer.
In the embodiment, the metal oxide semiconductor layer 113 of the first tft T1 is formed after the first source 109 and the first drain 111 are formed, so that damage to the metal oxide semiconductor layer 113 when the second tft T2 is subjected to a high temperature hydrogenation process can be avoided, and the metal oxide semiconductor layer 113 is formed after the first source 109 and the first drain 111 are formed, so that damage to the metal oxide semiconductor layer 113 caused by etching a metal layer in which the first source 109 and the first drain 111 are located can be avoided.
In the present embodiment, the first gate 105 and the second gate 205 are located at the same layer, and the first gate 105 and the second gate 205 can be formed by the same conductive layer in the same manufacturing process.
For convenience of description, in the following embodiments, elements having the same structure and function as those in the first embodiment are not described herein again, and the reference numerals in the first embodiment are used.
Referring to fig. 2, fig. 2 is a schematic cross-sectional view of a semiconductor substrate 10 according to a second embodiment of the invention. The structure of the semiconductor substrate 10 of the present embodiment is similar to that of the semiconductor substrate 10 of the first embodiment, except that: in the present embodiment, the second gate insulating layer 1072 of the first thin film transistor T1 has a first via hole 115 penetrating through the metal oxide semiconductor layer 113 in a thickness direction thereof, so as to expose the first gate insulating layer 1071. The metal oxide semiconductor layer 113 directly contacts the first gate insulating layer 1071 through the first via hole 115 and partially covers the first source electrode 109 and the first drain electrode 111.
In the present embodiment, since the second gate insulating layer 1072 is provided with the first via 115 penetrating through the thickness direction thereof, the thickness of the gate insulating layer 107 between the first source 109, the first drain 111 and the first gate 105 is reduced, and the capacitance between the first source 109, the first drain 111 and the first gate 105 is reduced.
Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a semiconductor substrate 10 according to a third embodiment of the invention. For brevity, in this embodiment, elements having the same structure and function as those of the first embodiment are not described in detail herein.
In the present embodiment, the gate insulating layer 107 includes a first gate insulating layer 1071 and a second gate insulating layer 1072 stacked in this order in a direction perpendicular to and away from the substrate 101. The buffer layer 103, the second gate electrode 205, the first gate insulating layer 1071, the first gate electrode 105, and the second gate insulating layer 1072 are sequentially disposed on the substrate 101. The second gate 205 is located on a side of the first gate insulation layer 1071 away from the second gate insulation layer 1072, and the first gate 105 is located between the first gate insulation layer 1071 and the second gate insulation layer 1072.
In this embodiment, the first gate insulating layers 1071 and 1071 are made of silicon nitride, and the second gate insulating layers 1072 and 1072 are made of silicon oxide.
In the present embodiment, the first gate 105 is spaced apart from the first source 109 and the first drain 111 by the second gate insulating layer 1072, and the first gate insulating layer 1071 is not provided between the first gate 105 and the first source 109 and the first drain 111, so that the thickness of the gate insulating layer 107 between the first source 109 and the first drain 111 and the first gate 105 is reduced, and the capacitance between the first source 109 and the first drain 111 and the first gate 105 is reduced.
In the present embodiment, the first gate 105 and the second gate 205 are located at different layers, and the first gate 105 and the second gate 205 are formed by different conductive layers.
The semiconductor substrate 10 of the first to third embodiments described above may be applied to a pixel driving circuit in a pixel unit of an array substrate in an electronic device, and may also be applied to an inverter circuit or a switching circuit in a peripheral circuit in an electronic device. Hereinafter, only the application of the semiconductor substrate 10 of the third embodiment will be described, and it is understood that the semiconductor substrate 10 of the third embodiment applied to the following embodiments may be replaced with the semiconductor substrate 10 of the first embodiment or the semiconductor substrate 10 of the second embodiment.
Referring to fig. 4, fig. 4 is a schematic plan view of an array substrate 100 to which an embodiment of the invention is applied. The array substrate 100 of an embodiment of the invention is an organic electroluminescent (OLED) display panel, and the array substrate 100 includes a substrate 11, wherein the substrate 11 is provided with a plurality of scan lines S1-Sn parallel to each other and a plurality of data lines D1-Dn parallel to each other and intersecting with the scan lines S1-Sn. The scan lines S1-Sn are electrically connected to the first driving circuit 12, and the data lines D1-Dn are electrically connected to the second driving circuit 13. The scan lines S1-Sn intersect the data lines D1-Dn in a vertically isolated manner to define a plurality of pixel units 14. Each pixel cell 14 has a corresponding pixel drive circuit 15 (shown in figure 5). In the present embodiment, the first driving circuit 12 may include a multiplexing circuit and a gate driving circuit. The second driving circuit 13 is a data driving circuit.
Referring to fig. 5, fig. 5 is an equivalent circuit diagram of the pixel driving circuit 15 in the pixel unit 14 according to an embodiment of the invention. Includes a power line VDD, an initial terminal Vini, a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a first node A, a second node B, an organic light emitting diode OLED, a storage capacitor Cs, a parasitic capacitor COLEDAnd a ground terminal Vss. In this embodiment, the first thin film transistor T1 is a low temperature polysilicon thin film transistor, the second thin film transistor T2 is a metal oxide thin film transistor, and the third thin film transistor T3 and the fourth thin film transistor T4 may be any one of a low temperature polysilicon thin film transistor, an amorphous silicon thin film transistor, or an organic thin film transistor. In the present embodiment, the third thin film transistor T3 and the fourth thin film transistor T4 are low temperature polysilicon thin film transistors.
The gate of the third tft T3 is electrically connected to the first scan line S1, the drain is electrically connected to the data line D1, and the source is electrically connected to the gate of the first tft T1 through the first node a. The drain of the first thin film transistor T1 is electrically connected to the source of the second thin film transistor T2, and the source of the first thin film transistor T1 is electrically connected to the Anode (Anode) of the organic light emitting diode OLED through a second node B. The gate of the second tft T2 is electrically connected to the third scan line S3, and the drain of the second tft T2 is electrically connected to the power line VDD. The gate of the fourth tft T4 is electrically connected to the second scan line S2, and the drain of the fourth tft T4 is electrically connected to the second node B. The anode of the organic light emitting diode OLED is electrically connected to the source of the first thin film transistor T1, and the cathode thereof is electrically connected to the ground Vss. The storage capacitor Cs is electrically connected between the gate and the source of the first thin film transistor T1. The parasitic capacitance COLEDAnd the organic light emitting diode OLED is electrically connected between the cathode and the anode of the organic light emitting diode OLED.
It is understood that the pixel unit 14 is not limited to the structure shown in fig. 5, and may also be a pixel structure of 5T1C (including 5 Thin Film Transistors (TFTs) and a capacitor C) (not shown), so long as it is adapted to a structure in which one of the first source 109 or the first drain 111 of the first TFT T1 is electrically connected to one of the second source 209 or the second drain 211 of the second TFT T2.
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of an array substrate 100 according to an embodiment of the invention. For convenience of description, the first thin film transistor T1 and the second thin film transistor T2 are illustrated in fig. 6, and other elements such as the third thin film transistor T3 and the fourth thin film transistor T4 are omitted. The array substrate 100 in this embodiment uses the semiconductor substrate 10 of the third embodiment, and for the sake of brevity, the structures of the first thin film transistor T1 and the second thin film transistor T2 will not be described again.
As shown in fig. 6, the array substrate 100 further includes a planarization layer 16 covering the first and second thin film transistors T1 and T2. The planarization Layer 16 is provided with a third via 17 penetrating through the planarization Layer in a thickness direction perpendicular to the substrate 101, the third via 17 is filled with an anode 18 of the organic light emitting diode OLED, a Pixel Defining Layer 19 (PDL) is provided on the planarization Layer 16, and one end of the anode 18 is connected to the first source electrode 109 and the other end is connected to the Pixel Defining Layer 19.
In the array substrate 100 of the embodiment, the second thin film transistor T2 is a metal oxide thin film transistor, and compared with an array substrate that only uses a low temperature polysilicon thin film transistor, the second thin film transistor T2 that is a metal oxide thin film transistor has a smaller volume and a simpler process, and has a low leakage current to reduce power consumption and improve the performance of the array substrate 100.
In the present embodiment, the first drain 111 and the second source 209 are disposed at the same layer. The first drain 111 and the third source/drain are a continuous conductive layer, which can reduce the layout space occupied by the first thin film transistor T2 and the second thin film transistor T2, and in addition, the second thin film transistor T2 can realize the electrical connection between the metal oxide semiconductor layer 113 and the first source 109 and the first drain 111 without forming a through hole, and can also reduce the area occupied by the second thin film transistor T2.
Referring to fig. 7 and 8, fig. 7 is an equivalent circuit diagram of an inverter circuit 30 according to an embodiment of the invention. Fig. 8 is a schematic plan view of the inverter circuit 30 according to the embodiment of the present invention. In the present embodiment, the inverter circuit 30 is applied to the semiconductor substrate 10 of the third embodiment of the present invention. For convenience of description, elements such as a gate insulating layer are omitted in fig. 8.
As shown in fig. 8, the first gate 105 of the first thin film transistor T1 and the second gate 205 of the second thin film transistor T2 of the inverter circuit 30 are electrically connected. As shown IN fig. 7, IN the present embodiment, when the input terminal IN inputs a high level, the first thin film transistor T1 is turned on, the second thin film transistor T2 is turned off, and the first thin film transistor T1 outputs a low level. When the input terminal IN inputs a low level, the second thin film transistor T2 is turned on, the first thin film transistor T1 is turned off, and the second thin film transistor T2 outputs a high level.
Referring to fig. 9, fig. 9 is an equivalent circuit diagram of a switch circuit 40 according to an embodiment of the invention. In this embodiment, the semiconductor substrate 10 according to the third embodiment of the present invention is applied to the switching circuit 40. IN the present embodiment, the input terminal IN of the switch circuit 40 inputs a signal, the first gate 105 of the first thin film transistor T1 controls the switch of the first thin film transistor T1, and the second gate 205 of the second thin film transistor T2 controls the switch of the second thin film transistor T2. When the first thin film transistor T1 is turned on, a signal inputted from the input terminal IN is outputted through the first thin film transistor T1; when the second thin film transistor T2 is turned on, a signal inputted from the input terminal IN is outputted through the second thin film transistor T2.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention.
Claims (10)
1. A semiconductor substrate comprises a substrate, a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are arranged on the substrate, and the semiconductor substrate is characterized in that:
the first thin film transistor is a top gate type metal oxide thin film transistor, and the second thin film transistor is a bottom gate type low-temperature polycrystalline silicon thin film transistor;
the first thin film transistor comprises a first grid electrode, a metal oxide semiconductor layer, a first source electrode and a first drain electrode, wherein the first grid electrode and the metal oxide semiconductor layer are arranged on the substrate, and the first source electrode and the first drain electrode are connected with the metal oxide semiconductor layer and are spaced from each other;
the second thin film transistor comprises a polycrystalline silicon semiconductor layer, a second grid electrode, a second source electrode and a second drain electrode, wherein the polycrystalline silicon semiconductor layer and the second grid electrode are arranged on the substrate in sequence; and
one of the first source or the first drain is electrically connected with one of the second source or the second drain.
2. The semiconductor substrate of claim 1, wherein: one of the first source electrode or the first drain electrode and one of the second source electrode or the second drain electrode are arranged on the same layer and are directly connected.
3. The semiconductor substrate of claim 2, wherein: the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are formed by patterning the same conductive layer.
4. The semiconductor substrate of claim 1, wherein: the metal oxide semiconductor layer is positioned on one side of the first source electrode and the first drain electrode, which is far away from the substrate.
5. The semiconductor substrate of claim 1, wherein: the semiconductor substrate further comprises a gate insulating layer formed on the substrate and covering the first gate and the second gate;
the grid insulation layer comprises a first grid insulation layer and a second grid insulation layer which are sequentially stacked along the direction far away from the substrate; and
the second gate insulating layer is provided with at least one through hole penetrating through the second gate insulating layer in the thickness direction, and the first source electrode and the first drain electrode are in direct contact with the first gate insulating layer through the at least one through hole.
6. The semiconductor substrate of claim 5, wherein: the first gate and the second gate are patterned from the same conductive layer.
7. The semiconductor substrate of claim 1, wherein: the semiconductor substrate comprises a first grid insulating layer and a second grid insulating layer which are sequentially stacked on the substrate, the second grid is positioned on one side, away from the second grid insulating layer, of the first grid insulating layer, and the first grid is positioned between the first grid insulating layer and the second grid insulating layer.
8. An array substrate comprising the semiconductor substrate of any one of claims 1-7.
9. An inverter circuit comprising the semiconductor substrate according to any one of claims 1 to 7.
10. A switching circuit comprising the semiconductor substrate of any one of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810669271.4A CN110649003A (en) | 2018-06-26 | 2018-06-26 | Semiconductor substrate, array substrate, inverter circuit, and switching circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810669271.4A CN110649003A (en) | 2018-06-26 | 2018-06-26 | Semiconductor substrate, array substrate, inverter circuit, and switching circuit |
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| CN110649003A true CN110649003A (en) | 2020-01-03 |
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| CN201810669271.4A Pending CN110649003A (en) | 2018-06-26 | 2018-06-26 | Semiconductor substrate, array substrate, inverter circuit, and switching circuit |
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| CN113764437A (en) * | 2021-09-06 | 2021-12-07 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
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