CN110610858A - Gate electrode current conversion thyristor and manufacturing method thereof - Google Patents
Gate electrode current conversion thyristor and manufacturing method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
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Abstract
The invention discloses a gate commutated thyristor and a manufacturing method thereof. The thyristor comprises P+Transparent emitting anode, N' buffer layer, N‑Base region, P base region and N+And the N' buffer layer and the P base region are respectively provided with at least one low minority carrier lifetime region with a minority carrier lifetime lower than that of other regions. Compared with the prior art, the gate pole converter thyristor provided by the invention has the advantages that the turn-off capability is improved, the turn-off loss is reduced, and meanwhile, the influence on the on-state voltage drop is small.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a gate commutated thyristor and a manufacturing method thereof.
Background
In the prior art, Gate commutated thyristors (Gate Co)The main structure of the mmuted Thyristors, GCT) chip in the longitudinal direction comprises four PNPN layers, as shown in fig. 1, corresponding to 1(P + transparent emitting anode), 2 (N' buffer layer), and 3(N +) respectively-Base region), 4(P base region) and 5(N base region)+The emitter region is also referred to as the cathode sliver). Three electrodes are led out, namely 6 (anode), 7 and 9 (gate pole) and 8 (cathode).
The device has 3 PN junctions, 10(J1 junction, anode transparent junction), 11(J2 junction, main junction of blocking voltage) and 12(J3 junction, gate cathode junction) from the anode to the cathode. When the GCT chips are viewed in the transverse direction, as shown in fig. 2, the chip cathode comb strips are uniformly arranged in a wafer by sector arcs or circumferences. For GCT tube cores with different diameters, the cathode comb strips are generally radially arranged according to 2-16 circles. According to the magnitude of the GCT turn-off current, the GCT gate leading-out part is arranged at the center of the wafer, namely called a central gate, or is arranged at the center or the periphery of the wafer, namely called a middle ring gate or an edge ring gate.
An important criterion for measuring GCT performance is its turn-off capability. However, in the prior art, improvements aimed at increasing the turn-off capability of the GCT are often accompanied by complex processes and higher manufacturing costs.
Disclosure of Invention
The invention provides a gate-commutated thyristor, which comprises P+Transparent emitting anode, N' buffer layer, N-Base region, P base region and N+And the N' buffer layer and the P base region are respectively provided with at least one low minority carrier lifetime region with a minority carrier lifetime lower than that of other regions.
In one embodiment, the thyristor includes two low minority carrier lifetime regions respectively configured in the N' buffer layer and the P base region.
The invention also provides a manufacturing method of the gate commutated thyristor, which comprises the following steps:
manufacturing P of chip structure from bottom to top+Transparent emitting anode, N' buffer layer, N-Base region, P base region and N+A chip of the emitter region;
and respectively establishing at least one low minority carrier lifetime region with minority carrier lifetime lower than that of other regions on the N' buffer layer and the P base region of the chip.
In one embodiment, respectively establishing at least one low minority carrier lifetime region with a minority carrier lifetime lower than that of other regions in the N' buffer layer and the P base region of the chip includes:
after the chip finishes a mesa passivation process, adopting proton or helium irradiation on the anode surface of the chip to establish the low minority carrier lifetime region;
and (5) annealing treatment.
In one embodiment, in the process of establishing the low minority carrier lifetime region by the N' buffer layer of the chip, the distance from the center of the at least one irradiation region to the anode surface is 20-50 μm.
In one embodiment, in the process of establishing the low minority carrier lifetime region in the P base region of the chip, the distance from the center of at least one irradiation region to the cathode plane is 30 μm to 140 μm.
In one embodiment, the dose range of proton or helium irradiation is 1E9cm-3～1E13cm-3。
In an embodiment, the method further comprises:
after establishing the low minority carrier lifetime region, before performing the annealing treatment step, controlling the whole lifetime value of the chip by using electron irradiation.
In one embodiment, the method comprises:
manufacturing 6500V GCT chips, wherein:
the resistivity range of the N-type silicon single crystal is 470 omega cm;
the thickness of the GCT chip is 760 to 770 μm;
the doping concentration range of the P base region is 1E13cm-3To 5E17cm-3The junction depth is 120-140 μm;
the doping concentration range of the N' buffer layer is 1E13cm-3To 5E16cm-3A junction depth of about 30 μm to 35 μm;
and respectively establishing a low minority carrier lifetime region on the N' buffer layer and the P base region of the chip by adopting twice proton or helium irradiation on the anode surface of the chip, wherein:
the proton or helium irradiation area of the P base region is located at 110-115 μm, and the proton or helium irradiation dose is 2E10cm-2～6E10cm-2；
The proton or helium ion irradiation region of the N' buffer layer is located at 30 μm-35 μm, and the proton or helium ion irradiation dose is 6E10cm-2～1E11cm-2；
Carrying out electron irradiation to adjust the on-state voltage drop of the chip to a target value;
annealing treatment is carried out for 200 ℃/10h to 20 h.
In one embodiment, the method comprises:
manufacturing 4500V reverse conducting type GCT chips, wherein:
the resistivity range of the N-type silicon single crystal is 300 omega cm,
the chip thickness is 540 μm to 550 μm,
the doping concentration range of the P base region of the GCT part is 1E13cm-3To 5E17cm-3The junction depth is 115 mu m to 125 mu m;
the doping concentration range of the P base region of the FRD part is 1E13cm-3To 5E18cm-3The junction depth is 115 mu m to 125 mu m;
the doping concentration range of the N' buffer layer in the GCT part is 1E13cm-3To 5E16cm-3The knot depth is 30-35 μm;
the doping concentration range of the N' buffer layer of the FRD part is 1E13cm-3To 5E16cm-3Junction depths of about 40 μm to 45 μm;
and respectively establishing the low minority carrier lifetime region on the anode surface of the chip by irradiating the N' buffer layer and the P base region of the GCT part and the P base region of the FRD part with three times of protons or helium ions, wherein:
the proton or helium irradiation region of the P base region of the GCT portion is located at 60 μm-70 μm with a proton or helium irradiation dose of 2E10cm-2；
The proton or helium irradiation region of the N' buffer layer of the GCT portion is located at 30 μm-35 μm at a dose of 6E10cm-2～1E11cm-2；
P base region of FRD partThe proton or helium ion irradiation region of (1) is located at 60 μm to 70 μm, and the proton or helium ion irradiation dose is 1E12cm-2～1E13cm-2；
Carrying out electron irradiation to adjust the on-state voltage drop of the chip to a target value;
annealing treatment is carried out for 200 ℃/10h to 20 h.
Compared with the prior art, the gate pole converter thyristor provided by the invention has the advantages that the turn-off capability is improved, the turn-off loss is reduced, and meanwhile, the influence on the on-state voltage drop is small.
Additional features and advantages of the invention will be set forth in the description which follows. Also, some of the features and advantages of the invention will be apparent from the description, or may be learned by practice of the invention. The objectives and some of the advantages of the invention may be realized and attained by the process particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of the longitudinal structure of a prior art GCT;
FIG. 2 is a schematic top view of a prior art GCT;
FIG. 3 is a schematic diagram of a GCT longitudinal structure according to an embodiment of the present invention;
FIG. 4 and FIG. 5 are graphs comparing GCT performance with the prior art according to an embodiment of the present invention;
FIGS. 6-14 are schematic diagrams of the vertical structure of the chip at various stages in the GCT manufacturing process according to one embodiment of the present invention;
fig. 15 and 16 are schematic diagrams of GCT longitudinal structures and corresponding minority carrier lifetimes made in accordance with various embodiments of the invention.
Detailed Description
The following detailed description will be provided for the embodiments of the present invention with reference to the accompanying drawings and examples, so that the practitioner of the present invention can fully understand how to apply the technical means to solve the technical problems, achieve the technical effects, and implement the present invention according to the implementation procedures. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
In the prior art, the main structure of a Gate Commutated Thyristor (GCT) chip in the longitudinal direction includes four PNPN layers, as shown in fig. 1, corresponding to 1(P + transparent emitting anode), 2(N 'buffer layer), and 3 (N' buffer layer), respectively-Base region), 4(P base region) and 5(N base region)+The emitter region is also referred to as the cathode sliver). Three electrodes are led out, namely 6 (anode), 7 and 9 (gate pole) and 8 (cathode).
The device has 3 PN junctions, 10(J1 junction, anode transparent junction), 11(J2 junction, main junction of blocking voltage) and 12(J3 junction, gate cathode junction) from the anode to the cathode. When the GCT chips are viewed in the transverse direction, as shown in fig. 2, the chip cathode comb strips are uniformly arranged in a wafer by sector arcs or circumferences. For GCT tube cores with different diameters, the cathode comb strips are generally radially arranged according to 2-16 circles. According to the magnitude of the GCT turn-off current, the GCT gate leading-out part is arranged at the center of the wafer, namely called a central gate, or is arranged at the center or the periphery of the wafer, namely called a middle ring gate or an edge ring gate.
An important criterion for measuring GCT performance is its turn-off capability. However, in the prior art, improvements aimed at increasing the turn-off capability of the GCT are often accompanied by complex processes and higher manufacturing costs.
In view of the above problems, the present invention provides a new gate commutated thyristor structure.
Specifically, in one embodiment, the thyristor includes P+Transparent emitting anode, N' buffer layer, N-Base region, P base region and N+And the N' buffer layer and the P base region are respectively provided with at least one low minority carrier lifetime region with a minority carrier lifetime lower than that of other regions.
Specifically, as shown in fig. 3, in one embodiment, the thyristor includes: 201 and 204 cathodes, 202And 205N+Emitter region 203 gate, 206P base region 208N-A base region, a 210N' buffer layer, a 211P + transparent emitter anode, and a 212 anode. The thyristor includes two low minority carrier lifetime regions 207 and 209, and the low minority carrier lifetime regions 207 and 209 are respectively formed in the 206N' buffer layer and the 210P base region.
3 PN junctions exist in the device, and from the anode to the cathode, J1 junctions (anode transparent junctions), J2 junctions (main junction of blocking voltage) and J3 junctions (gate cathode junctions) are respectively formed. In practice, the gate-cathode bias of the GCT is turned on by-20V to turn off the J3 junction, and the cathode current is switched to the gate before the voltage of the J2 junction rises (so-called hard turn-off), so that the GCT enters the PNP transistor operation mode with the open base. At the moment, the surplus electron carriers of the N-base region can pass through the transparent anode J1 to be pumped away, and the surplus hole carriers of the P-base region are pumped away through the gate electrode, so that the anode current of the GCT is reliably turned off in a very short time, and meanwhile, the J2 junction recovers the blocking capability. Macroscopically it appears that the GCT switch transitions from a low resistance state to a high resistance state.
In the turn-off process of the GCT, dv/dt and di/dt in the turn-off process are increased along with the reduction of minority carrier lifetime of the GCT, the turn-off time of the GCT is reduced, and the turn-off energy is reduced. In particular at the voltage and current crossing points, where dv/dt and di/dt have the most significant effect on the turn-off energy.
Aiming at the chip provided by the invention, the low-minority carrier lifetime region in the P base region of the GCT chip can enable the current carriers of the P base region to be rapidly transferred to the gate electrode in the turn-off process of the GCT, so that the accumulation of the current carriers under the cathode comb strip is avoided, the false turn-on caused by the accumulation of the current carriers when the GCT is turned off is further avoided, and the turn-off capability of the device is improved. And in the GCT turn-off process, the low minority carrier lifetime region of the N' buffer layer can accelerate the establishment of a J2 junction depletion region to lead to the rapid discharge of residual carriers of the N-base region, so that the anode voltage is rapidly raised, and the device is rapidly turned off, thereby shortening the trailing time of the anode current and reducing the turn-off loss of the device.
The performance of embodiments of the present invention is described next by specific experimental data.
As shown in fig. 4, the current density under the same conditions under the comb strip is compared for a standard type of GCT structure (represented by the line x in fig. 4) with a GCT structure according to an embodiment of the invention (represented by the line x in fig. 4) at the position indicated by the tangent line a-a in fig. 1. As can be seen from fig. 4, the current density under the cathode comb is greatly reduced by the novel structure provided by the present invention, because a large number of recombination centers are introduced into the low minority carrier lifetime region of the P region, and electrons and holes are rapidly recombined in the low lifetime region, resulting in a lower current density under the cathode comb. According to the GCT dynamic avalanche damage mechanism, the GCT turn-off capability can be improved.
Fig. 5 shows the turn-off waveform of a standard type CGT (represented by the x-line in fig. 5) under the same conditions as the GCT (represented by the o-line in fig. 5) according to an embodiment of the present invention. As shown in fig. 5, the GCT anode voltage of an embodiment of the present invention rises more rapidly, i.e., dv/dt is greater than that of the standard GCT, which indicates that all excess carriers in the J2 junction are extracted more efficiently, so that a depletion layer is formed earlier to establish the anode voltage. This is due to two reasons: firstly, electron hole recombination under the GCT cathode comb strip is rapid, and carriers in a P region are fewer, and on the other hand, excessive carrier recombination in a J2 junction can be accelerated due to a large number of recombination centers in a low minority carrier lifetime region of a GCT N-base region, so that the establishment of a depletion region is accelerated.
In addition, the anode tail time of the GCT according to an embodiment of the present invention is shorter because the recombination center of the N-base region with low minority carrier lifetime enables electrons outside the depleted region to reach the anode transparent layer more rapidly and be extracted by the electrode, so the anode tail time is shorter. The turn-off loss of the GCT of an embodiment of the invention at 125 c to turn-off 4000A is reduced by about 4J (about 20%) compared to the standard GCT.
Local low minority carrier lifetime region affects on-state voltage drop V of Integrated Gate Commutated Thyristor (IGCT)TMBecause the service life of the carriers injected into the P base region is reduced, the carriers are quickly compounded to weaken the conductivity modulation effect, thereby causing VTMAnd (4) increasing. FIG. 6 is the on-state pressure drop of a typical GCT versus a standard GCT at 4000A @ ambient temperature. As shown in fig. 6, in the P base region and N base region-The base region establishes a low minority carrier lifetime region with an on-state voltage drop increase of only about 0.1V, compared to their superiority for GCT turn-off capability and turn-off lossIn terms of on-state pressure drop, a rise of 0.1V is quite acceptable. In summary, the GCT according to an embodiment of the present invention has a small influence on the on-state voltage drop while improving the turn-off capability and reducing the turn-off loss.
The invention also provides a method for manufacturing the gate commutated thyristor. In one embodiment, a method comprises:
manufacturing P of chip structure from bottom to top+Transparent emitting anode, N' buffer layer, N-Base region, P base region and N+A chip of the emitter region;
at least one low minority carrier lifetime region with the minority carrier lifetime shorter than that of other regions is respectively established on the N' buffer layer and the P base region of the chip.
In one embodiment, the process of establishing the low minority carrier lifetime region comprises:
after the chip finishes the mesa passivation technology, adopting proton or helium irradiation to establish the low minority carrier lifetime region on the anode surface of the chip;
and (5) annealing treatment.
In one embodiment, the distance between the center of the at least one irradiation region and the anode surface is 20-50 μm in the process of establishing the low minority carrier lifetime region in the N' buffer layer of the chip.
In one embodiment, in the process of establishing the low minority carrier lifetime region in the P base region of the chip, the distance from the center of the at least one primary irradiation region to the cathode surface is 30-140 μm.
Specifically, in one embodiment, after the mesa passivation process is completed on the chip, two times of proton or helium irradiation are performed on the anode surface of the chip to respectively establish a low minority carrier lifetime region on the N' buffer layer and the P base region of the chip.
Further, in one embodiment, the dose range of proton or helium irradiation is 1E9cm-3～1E13cm-3。
Further, in one embodiment, in the annealing treatment, the annealing temperature is 200-400 ℃, and the annealing time is 8-15 h.
Further, in an embodiment, the method further includes:
after establishing the low minority carrier lifetime region, before performing the annealing treatment step, the whole lifetime value of the chip is controlled by electron irradiation so as to adjust the on-state voltage drop of the chip to a target value.
Specifically, in one embodiment, the entire process of chip fabrication includes the following steps:
1) n-type single crystal silicon substrate preparation
Providing an N-type doped monocrystalline silicon substrate, wherein the doping concentration and the sheet thickness of the substrate are selected mainly according to the parameter requirements of GCT blocking voltage, on-state voltage drop and the like.
2) P + short base region formation
P of GCT+The base region is formed by B implantation diffusion, specifically P first+Base full-area implant (as shown in fig. 6), then P+Base drive in (as shown in fig. 7).
3) P base region formation
The P-base region fabrication includes P-base region formation (as shown in fig. 8) and back side P-type doping layer removal (as shown in fig. 9).
The P base region is manufactured by selecting an aluminum injection diffusion process or a closed tube aluminum diffusion process, and the two process schemes are as follows:
a) and (3) aluminum injection diffusion process: firstly, the whole surface implantation is carried out on the front surface of a monocrystalline silicon substrate, doping impurities are implanted into the monocrystalline silicon substrate to be Al +, and the implantation dosage is EAlDepending on the doping concentration of the P-base region. Depositing a layer of Si3N4 film by using a Low Pressure Chemical Vapor Deposition (LPCVD) process, performing high-temperature propulsion in a nitrogen atmosphere to control the Al junction depth of the P base region within a design range, and removing the P-type doped layer on the back surface.
b) Closed tube aluminum expansion: and (3) performing high-temperature propulsion for a certain time t in the saturated aluminum atmosphere of the vacuum furnace tube, controlling the time t according to the Al junction depth design value of the P base region, and then removing the P-type doping layer on the back surface.
The two processes have advantages and disadvantages respectively: the chip formed by the aluminum injection diffusion process has better surface quality and utilizes the formation of a subsequent cathode comb strip structure. The closed pipe aluminum expanding process is simple, and the batch production cost is low.
4) Formation of N' buffer layer
As shown in FIG. 10, the N' buffer layer is implanted into the back surface of the single crystal silicon substrate at a whole surface, the doping impurity is phosphorus, and the implantation dose is EPAnd (3) controlling the junction depth of the N ' buffer layer within a design range according to the doping concentration of the N ' buffer layer and then propelling the N ' buffer layer in a high-temperature diffusion furnace.
5)N+Cathode sliver formation
As shown in fig. 11, N is performed on the front surface of the single crystal silicon substrate+Diffusion of phosphorus according to N+The doping concentration and the junction depth of the sliver structure determine the flow rate and the diffusion time of a doping gas source in a phosphorus diffusion furnace, and N is converted into N+The structure of the cathode comb strip layer is controlled within a design range. And then selectively etching the cathode comb strip layer to form a GCT cathode comb strip structure.
6) Transparent anode P+Form a
As shown in fig. 12, a transparent anode P+The layer is implanted into the back of the monocrystalline silicon substrate at the whole surface, the doping impurity is boron, and the implantation dosage is EAPAccording to the transparent anode P+The doping concentration of the layer is determined, and then the transparent anode P is pushed in a high-temperature diffusion furnace+The layer junction depth is controlled within the design range.
7) Metal electrode and mesa passivation formation
As shown in fig. 13, after the chip electrode metallization process, metal electrode layers are deposited on the respective surfaces of the die, and after etching treatment, a GCT unit cell structure is formed.
8) Multi-energy proton irradiation
As shown in fig. 14, after the GCT unit cell structure is formed, the whole GCT chip is irradiated with protons or helium ions twice, and the position and the lifetime of the low minority carrier lifetime region are controlled by controlling the irradiation energy and dose, so that two low minority carrier lifetime regions are formed in the P base region and the N' buffer layer region of the GCT chip. And finally, carrying out annealing treatment after the irradiation is finished.
Two specific application examples according to the present invention are described below, respectively.
Aiming at 6500V asymmetric GCT, the manufacturing method comprises the following steps:
manufacturing 6500V GCT chips, wherein:
the resistivity range of the N-type silicon single crystal is 470 omega cm;
the thickness of the GCT chip is 760 to 770 μm;
the doping concentration range of the P base region is 1E13cm-3To 5E17cm-3The junction depth is 120-140 μm;
the doping concentration range of the N' buffer layer is 1E13cm-3To 5E16cm-3A junction depth of about 30 μm to 35 μm;
and respectively establishing a low minority carrier lifetime region on the N' buffer layer and the P base region of the chip by adopting twice proton or helium irradiation on the anode surface of the chip, wherein:
the proton or helium irradiation area of the P base region is located at 110-115 μm, and the proton or helium irradiation dose is 2E10cm-2～6E10cm-2；
The proton or helium ion irradiation region of the N' buffer layer is located at 30 μm-35 μm, and the proton or helium ion irradiation dose is 6E10cm-2～1E11cm-2；
Carrying out electron irradiation to adjust the on-state voltage drop of the chip to a target value;
annealing treatment is carried out for 200 ℃/10h to 20 h.
The final chip structure and the corresponding minority carrier lifetime are shown in fig. 15.
Aiming at the 4500V reverse conducting GCT chip, the manufacturing method comprises the following steps:
manufacturing 4500V reverse conducting type GCT chips, wherein:
the resistivity range of the N-type silicon single crystal is 300 omega cm,
the chip thickness is 540 μm to 550 μm,
the doping concentration range of the P base region of the GCT part is 1E13cm-3To 5E17cm-3The junction depth is 115 mu m to 125 mu m;
the P base region doping concentration range of the Fast Recovery Diode (FRD) part is 1E13cm-3To 5E18cm-3The junction depth is 115 mu m to 125 mu m;
the doping concentration range of the N' buffer layer in the GCT part is 1E13cm-3To 5E16cm-3The knot depth is 30-35 μm;
FRD partial N' buffer layer dopingThe range of impurity concentration is 1E13cm-3To 5E16cm-3Junction depths of about 40 μm to 45 μm;
and respectively establishing the low minority carrier lifetime region on the anode surface of the chip by irradiating the N' buffer layer and the P base region of the GCT part and the P base region of the FRD part with three times of protons or helium ions, wherein:
the proton or helium irradiation region of the P base region of the GCT portion is located at 60 μm-70 μm with a proton or helium irradiation dose of 2E10cm-2；
The proton or helium irradiation region of the N' buffer layer of the GCT portion is located at 30 μm-35 μm at a dose of 6E10cm-2～1E11cm-2；
The proton or helium irradiation region of the P base region of the FRD part is located at 60 μm-70 μm, and the proton or helium irradiation dose is 1E12cm-2～1E13cm-2；
Carrying out electron irradiation to adjust the on-state voltage drop of the chip to a target value;
annealing treatment is carried out for 200 ℃/10h to 20 h.
The final chip structure and the corresponding minority carrier lifetime are shown in fig. 16.
The invention proposes to reduce the GCT N' buffer region and the P base region (namely P) below the cathode comb strip+Short base region and P base region) to form multiple low minority carrier lifetime regions, thereby achieving the purposes of reducing the turn-off energy of the device and improving the turn-off capability of the device. The low minority carrier lifetime region near the N' buffer region is beneficial to extracting N when the GCT is turned off-Due to free carriers of the base region, the trailing time of anode current is shortened, the turn-off loss is reduced, and the advantage of low GCT on-state voltage drop is kept; and the low minority carrier lifetime region in the P region below the GCT cathode comb strip is beneficial to extracting free carriers right below the cathode comb strip, and the phenomenon that the J3 junction is switched on by mistake and the chip is switched off and fails due to the accumulation of the free carriers generated by dynamic avalanche during switching off is avoided. In summary, the solution proposed by the present invention is not only beneficial to reducing the turn-off loss of the GCT, but also capable of improving the turn-off capability of the device, maintaining the advantage of low-pass voltage drop, and is applicable to GCT designs of all kinds and sizes, and the manufacturing process is simple.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. There are various other embodiments of the method of the present invention. Various corresponding changes or modifications may be made by those skilled in the art without departing from the spirit of the invention, and these corresponding changes or modifications are intended to fall within the scope of the appended claims.
Claims (10)
1. A gate-commutated thyristor, comprising P+Transparent emitting anode, N' buffer layer, N-Base region, P base region and N+And the N' buffer layer and the P base region are respectively provided with at least one low minority carrier lifetime region with a minority carrier lifetime lower than that of other regions.
2. The thyristor of claim 1, wherein the thyristor comprises two low minority carrier lifetime regions configured in the N' buffer layer and the P base region, respectively.
3. A method of manufacturing a gate commutated thyristor, the method comprising:
manufacturing P of chip structure from bottom to top+Transparent emitting anode, N' buffer layer, N-Base region, P base region and N+A chip of the emitter region;
and respectively establishing at least one low minority carrier lifetime region with minority carrier lifetime lower than that of other regions on the N' buffer layer and the P base region of the chip.
4. The method of claim 3, wherein the step of establishing at least one low minority carrier lifetime region with a minority carrier lifetime lower than that of other regions in the N' buffer layer and the P base region of the chip respectively comprises the steps of:
after the chip finishes a mesa passivation process, adopting proton or helium irradiation on the anode surface of the chip to establish the low minority carrier lifetime region;
and (5) annealing treatment.
5. The method of claim 4, wherein the distance from the center of the at least one irradiation region to the anode surface is 20 μm to 50 μm during the process of establishing the low minority carrier lifetime region in the N' buffer layer of the chip.
6. The method according to claim 4, wherein the distance from the center of the at least one irradiation region to the cathode surface is 30 μm to 140 μm in the process of establishing the low minority carrier lifetime region in the P base region of the chip.
7. The method of claim 4, wherein the dose of proton or helium irradiation is in the range of 1E9cm-3～1E13cm-3。
8. The method of claim 4, further comprising:
after establishing the low minority carrier lifetime region, before performing the annealing treatment step, controlling the whole lifetime value of the chip by using electron irradiation.
9. The method of claim 8, wherein the method comprises:
manufacturing 6500V GCT chips, wherein:
the resistivity range of the N-type silicon single crystal is 470 omega cm;
the thickness of the GCT chip is 760 to 770 μm;
the doping concentration range of the P base region is 1E13cm-3To 5E17cm-3The junction depth is 120-140 μm;
the doping concentration range of the N' buffer layer is 1E13cm-3To 5E16cm-3A junction depth of about 30 μm to 35 μm;
and respectively establishing a low minority carrier lifetime region on the N' buffer layer and the P base region of the chip by adopting twice proton or helium irradiation on the anode surface of the chip, wherein:
the proton or helium irradiation area of the P base region is located at 110-115 μm, and the proton or helium irradiation dose is 2E10cm-2～6E10cm-2；
The proton or helium ion irradiation region of the N' buffer layer is located at 30 μm-35 μm, and the proton or helium ion irradiation dose is 6E10cm-2～1E11cm-2；
Carrying out electron irradiation to adjust the on-state voltage drop of the chip to a target value;
annealing treatment is carried out for 200 ℃/10h to 20 h.
10. The method of claim 8, wherein the method comprises:
manufacturing 4500V reverse conducting type GCT chips, wherein:
the resistivity range of the N-type silicon single crystal is 300 omega cm,
the chip thickness is 540 μm to 550 μm,
the doping concentration range of the P base region of the GCT part is 1E13cm-3To 5E17cm-3The junction depth is 115 mu m to 125 mu m;
the doping concentration range of the P base region of the FRD part is 1E13cm-3To 5E18cm-3The junction depth is 115 mu m to 125 mu m;
the doping concentration range of the N' buffer layer in the GCT part is 1E13cm-3To 5E16cm-3The knot depth is 30-35 μm;
the doping concentration range of the N' buffer layer of the FRD part is 1E13cm-3To 5E16cm-3Junction depths of about 40 μm to 45 μm;
and respectively establishing the low minority carrier lifetime region on the anode surface of the chip by irradiating the N' buffer layer and the P base region of the GCT part and the P base region of the FRD part with three times of protons or helium ions, wherein:
the proton or helium irradiation region of the P base region of the GCT portion is located at 60 μm-70 μm with a proton or helium irradiation dose of 2E10cm-2；
The proton or helium irradiation region of the N' buffer layer of the GCT portion is located at 30 μm-35 μm at a dose of 6E10cm-2～1E11cm-2；
The proton or helium irradiation region of the P base region of the FRD part is located at 60 μm-70 μm, and the proton or helium irradiation dose is 1E12cm-2～1E13cm-2；
Carrying out electron irradiation to adjust the on-state voltage drop of the chip to a target value;
annealing treatment is carried out for 200 ℃/10h to 20 h.
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| CN111933705A (en) * | 2020-06-30 | 2020-11-13 | 株洲中车时代半导体有限公司 | Manufacturing method of power semiconductor device and power semiconductor device |
| CN116504824A (en) * | 2023-06-27 | 2023-07-28 | 清华大学 | Power semiconductor device and manufacturing method thereof |
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