CN110610858A - A gate commutated thyristor and its manufacturing method - Google Patents

Abstract

The invention discloses a gate commutated thyristor and a manufacturing method thereof. The thyristor includes a P ⁺ transparent emission anode, an N' buffer layer, an N ^- base region, a P base region, and an N ⁺ emission region, wherein at least one minority carrier is constructed in the N' buffer layer and the P base region, respectively The lifetime is lower than the low minority carrier lifetime region of other regions. Compared with the prior art, the gate commutated thyristor proposed by the present invention has little effect on the on-state voltage drop while improving the turn-off capability and reducing the turn-off loss.

Description

A gate commutated thyristor and its manufacturing method

technical field

The present invention relates to the field of electronic technology, in particular to a gate commutated thyristor and a manufacturing method thereof.

Background technique

In the prior art, the main vertical structure of a gate commutated thyristors (GCT) chip includes four layers of PNPN, as shown in FIG. 1, corresponding to 1 (P+ transparent emission anode), 2 (N' buffer layer), 3 ⁽ N- base region), 4 (P base region) and 5 (N ⁺ emitter region also known as cathode bar). The three electrodes drawn out are 6 (anode), 7 and 9 (gate) and 8 (cathode).

There are 3 PN junctions inside the device, 10 (J1 junction, anode transparent junction), 11 (J2 junction, blocking voltage main junction) and 12 (J3 junction, gate cathode junction) from anode to cathode. Viewed from the lateral direction of the GCT chip, as shown in Figure 2, the cathode strips of the chip are evenly arranged in a wafer using sector arcs or circumferences. For GCT dies of different diameters, the cathode combs are generally arranged in a radial pattern according to 2 to 16 turns. According to the size of the GCT turn-off current, the GCT gate lead-out part is arranged in the center of the wafer, which is called the center gate, or is arranged in the center or outer periphery of the wafer, which is called the middle ring gate or the edge ring gate.

An important criterion for measuring GCT performance is its turn-off capability. However, in the prior art, improvements aimed at improving the turn-off capability of GCTs are often accompanied by complex processes and higher manufacturing costs.

SUMMARY OF THE INVENTION

The present invention provides a gate commutated thyristor, the thyristor includes a P ⁺ transparent emission anode, an N' buffer layer, an N ^- base region, a P base region and an N ⁺ emission region, wherein the N' buffer layer and At least one low minority carrier lifetime region with a minority carrier lifetime lower than other regions is respectively configured in the P base region.

In one embodiment, the thyristor includes two low minority carrier lifetime regions, and the low minority carrier lifetime regions are respectively constructed in the N' buffer layer and the P base region.

The present invention also provides a method for manufacturing a gate commutated thyristor, the method comprising:

Manufacture the chip whose structure from bottom to top is the chip's P ⁺ transparent emitting anode, N' buffer layer, N ^- base region, P base region and N ⁺ emitting region;

At least one low minority carrier lifetime region with a minority carrier lifetime lower than other regions is established in the N' buffer layer and the P base region of the chip, respectively.

In an embodiment, at least one low minority carrier lifetime region with a minority carrier lifetime lower than other regions is established in the N' buffer layer and the P base region of the chip, respectively, including:

After the chip completes the mesa passivation process, the anode surface of the chip is irradiated with protons or helium to establish the low minority carrier lifetime region;

Annealed.

In one embodiment, in the process of establishing the low minority carrier lifetime region in the N' buffer layer of the chip, the distance from the center of the irradiation region to the anode surface is 20 μm˜50 μm at least once.

In one embodiment, in the process of establishing the low minority carrier lifetime region in the P base region of the chip, the distance from the center of the irradiation region to the cathode surface is 30 μm˜140 μm at least once.

In one embodiment, the dose of proton or helium irradiation ranges from 1E9 cm ^-3 to 1E13 cm ^-3 .

In one embodiment, the method further includes:

After establishing the low minority carrier lifetime region, electron irradiation is used to control the overall lifetime value of the chip before performing the annealing treatment step.

In one embodiment, the method includes:

Fabrication of 6500V GCT chips with:

The resistivity range of N-type silicon single crystal is 470Ω·cm;

GCT chip thickness is 760μm to 770μm;

The doping concentration of the P base region ranges from 1E13cm ^-3 to 5E17cm ^-3 , and the junction depth ranges from 120 μm to 140 μm;

The N' buffer layer doping concentration ranges from 1E13cm ^-3 to 5E16cm ^-3 , and the junction depth is about 30 μm to 35 μm;

The N' buffer layer and the P base region of the chip are irradiated twice with protons or helium on the anode surface of the chip to establish the low minority carrier lifetime region, wherein:

The proton or helium irradiation area of the P base region is located at 110 μm-115 μm, and the proton or helium irradiation dose is 2E10cm ^-2 to 6E10cm ^-2 ;

The proton or helium irradiation area of the N' buffer layer is located at 30μm-35μm, and the proton or helium irradiation dose is 6E10cm ^-2 -1E11cm ^-2 ;

Implement electron irradiation to adjust the on-state voltage drop of the chip to the target value;

Perform annealing treatment at 200°C/10h-20h.

In one embodiment, the method includes:

Manufacture of 4500V reverse conduction type GCT chips, where:

The resistivity range of N-type silicon single crystal is 300Ω·cm,

Chip thickness is 540μm to 550μm,

The doping concentration of the P base region of the GCT part ranges from 1E13cm ^-3 to 5E17cm ^-3 , and the junction depth ranges from 115μm to 125μm;

The doping concentration of the P base region of the FRD part ranges from 1E13cm ^-3 to 5E18cm ^-3 , and the junction depth ranges from 115μm to 125μm;

The doping concentration of the N' buffer layer in the GCT part ranges from 1E13cm ^-3 to 5E16cm ^-3 , and the junction depth is 30μm to 35μm;

The doping concentration of the N' buffer layer in the FRD part ranges from 1E13cm ^-3 to 5E16cm ^-3 , and the junction depth is about 40 μm to 45 μm;

On the anode surface of the chip, the N' buffer layer of the GCT part, the P base region and the P base region of the FRD part are respectively irradiated with protons or helium ions three times to establish the low minority carrier lifetime region, wherein:

The proton or helium irradiation area of the P base region of the GCT part is located at 60μm-70μm, and the proton or helium irradiation dose is 2E10cm ^-2 ;

The proton or helium irradiation area of the N' buffer layer of the GCT part is located at 30μm-35μm, and the proton or helium irradiation dose is 6E10cm ^-2 -1E11cm ^-2 ;

The proton or helium irradiation area of the P base region of the FRD part is located at 60 μm-70 μm, and the proton or helium irradiation dose is 1E12cm ^-2 -1E13cm ^-2 ;

Implement electron irradiation to adjust the on-state voltage drop of the chip to the target value;

Perform annealing treatment at 200°C/10h-20h.

Compared with the prior art, the gate commutated thyristor proposed by the present invention has little effect on the on-state voltage drop while improving the turn-off capability and reducing the turn-off loss.

Other features or advantages of the present invention will be set forth in the description that follows. Also, some of the features or advantages of the present invention will become apparent from the description, or may be learned by practice of the present invention. The objectives and some advantages of the invention may be realized and attained by means of the steps particularly pointed out in the description, claims and drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the specification, and together with the embodiments of the present invention, are used to explain the present invention, and do not constitute a limitation to the present invention. In the attached image:

1 is a schematic diagram of the longitudinal structure of GCT in the prior art;

Fig. 2 is the top view schematic diagram of GCT in the prior art;

3 is a schematic diagram of a longitudinal structure of a GCT according to an embodiment of the present invention;

FIG. 4 and FIG. 5 are a comparison diagram of GCT performance according to an embodiment of the present invention and the prior art;

6 to 14 are schematic diagrams of longitudinal structures of chips at different stages in the process of manufacturing a GCT according to an embodiment of the present invention;

FIG. 15 and FIG. 16 are schematic diagrams of longitudinal structures and corresponding minority carrier lifetimes of GCTs fabricated according to different embodiments of the present invention.

Detailed ways

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples, whereby the practitioners of the present invention can fully understand how the present invention applies technical means to solve technical problems, and achieve the realization process of technical effects and according to the above realization process The present invention is specifically implemented. It should be noted that, as long as there is no conflict, each embodiment of the present invention and each feature of each embodiment can be combined with each other, and the formed technical solutions all fall within the protection scope of the present invention.

In the prior art, the main vertical structure of a gate commutated thyristors (GCT) chip includes four layers of PNPN, as shown in FIG. 1, corresponding to 1 (P+ transparent emission anode), 2 (N' buffer layer), 3 ⁽ N- base region), 4 (P base region) and 5 (N ⁺ emitter region also known as cathode bar). The three electrodes drawn out are 6 (anode), 7 and 9 (gate) and 8 (cathode).

There are 3 PN junctions inside the device, 10 (J1 junction, anode transparent junction), 11 (J2 junction, blocking voltage main junction) and 12 (J3 junction, gate cathode junction) from anode to cathode. Viewed from the lateral direction of the GCT chip, as shown in Figure 2, the cathode strips of the chip are evenly arranged in a wafer using sector arcs or circumferences. For GCT dies of different diameters, the cathode combs are generally arranged in a radial pattern according to 2 to 16 turns. According to the size of the GCT turn-off current, the GCT gate lead-out part is arranged in the center of the wafer, which is called the center gate, or is arranged in the center or outer periphery of the wafer, which is called the middle ring gate or the edge ring gate.

An important criterion for measuring GCT performance is its turn-off capability. However, in the prior art, improvements aimed at improving the turn-off capability of GCTs are often accompanied by complex processes and higher manufacturing costs.

In view of the above problems, the present invention proposes a new gate commutated thyristor structure.

Specifically, in one embodiment, the thyristor includes a P ⁺ transparent emission anode, an N' buffer layer, an N ^- base region, a P base region, and an N ⁺ emission region, wherein the N' buffer layer and the P base region are respectively constructed with At least one of the low minority carrier lifetime regions has a lower minority carrier lifetime than other regions.

Specifically, as shown in FIG. 3, in one embodiment, the thyristor includes: 201 and 204 cathodes, 202 and 205N ⁺ emitter regions, 203 gate electrodes, 206P base region, 208N ^- base region, 210N' buffer layer, 211P+ transparent Emitting anode and 212 anode. In addition, the thyristor includes two low minority carrier lifetime regions 207 and 209, and the low minority carrier lifetime regions 207 and 209 are respectively constructed in the 206N' buffer layer and the 210P base region.

There are 3 PN junctions inside the device, from anode to cathode are J1 junction (anode transparent junction), J2 junction (blocking voltage main junction) and J3 junction (gate cathode junction). In practical applications, a -20V bias is applied to the gate-cathode of the conducting GCT to turn off the J3 junction. Before the voltage of the J2 junction rises, the cathode current is fully switched to the gate (this is the so-called hard turn-off), and the GCT enters the PNP tube working mode with open base. At this time, the excess electron carriers in the N-base region can be extracted through the transparent anode J1, and the excess hole carriers in the P-base region are extracted and drained through the gate electrode, so that the anode current of the GCT is reliable in a very short time. turned off, and the J2 junction restores its blocking capability. Macroscopically, the GCT switch changes from a low-resistance state to a high-resistance state.

During the turn-off process of the GCT, as the minority carrier lifetime of the GCT decreases, the dv/dt and di/dt of the turn-off process increase, the turn-off time of the GCT decreases, and the turn-off energy decreases. Especially at the intersection of voltage and current, the influence of dv/dt and di/dt on turn-off energy is the most obvious.

For the chip proposed by the present invention, the low minority carrier lifetime region in the P base region of the GCT chip can quickly transfer the carriers of the P base region to the gate electrode during the turn-off process of the GCT, thereby avoiding the current carrier under the cathode bar. Sub-aggregation, thereby avoiding false turn-on caused by carrier aggregation when the GCT is turned off, and improving the turn-off capability of the device. The low minority carrier lifetime region of the N' buffer layer can accelerate the establishment of the depletion region of the J2 junction during the GCT turn-off process, resulting in the rapid discharge of the remaining carriers in the N- base region, so that the anode voltage rises rapidly and the device turns off quickly. Therefore, the tailing time of the anode current is shortened, and the turn-off loss of the device is reduced.

Next, the performance of the embodiments of the present invention will be described through specific experimental data.

As shown in FIG. 4, along the position indicated by the tangent line A-A in FIG. 1, comparing the standard GCT structure (represented by the ◇ line in FIG. 4) and the GCT structure of an embodiment of the present invention (represented by the × line in FIG. 4) under the comb bar current density under the same conditions. It can be seen from Fig. 4 that the new structure proposed by the present invention greatly reduces the current density under the cathode bar, which is due to the introduction of a large number of recombination centers in the low minority carrier lifetime region of the P region, and the rapid recombination of electrons and holes in the low lifetime region, resulting in The current density is lower under the cathode bars. According to the dynamic avalanche damage mechanism of GCT, it is beneficial to improve the turn-off capability of GCT.

FIG. 5 shows the turn-off waveforms of the standard CGT (represented by the × line in FIG. 5 ) and the GCT of an embodiment of the present invention (represented by the ◇ line in FIG. 5 ) under the same conditions. As shown in FIG. 5 , the anode voltage of the GCT of an embodiment of the present invention rises more rapidly, that is, the dv/dt is larger than that of the standard GCT, which means that the extraction efficiency of all excess carriers in the J2 junction is higher, so the formation is earlier. A depletion layer builds up the anode voltage. This is due to two reasons: one is the rapid recombination of electrons and holes under the GCT cathode comb strip, and there are fewer carriers in the P region, and the other is due to the low minority carrier lifetime region of the GCT N-base region. Excess charge carriers in the J2 junction recombine, thereby accelerating the establishment of the depletion region.

In addition, the anode tailing time of the GCT of an embodiment of the present invention is shorter, because the recombination center of the low minority carrier lifetime region of the N-base region can make the electrons outside the depleted region reach the anode transparent layer more quickly, and the electrons outside the depleted region can reach the anode transparent layer more quickly. extraction, so the anode tailing time is shorter. Compared with the standard GCT, the turn-off loss of the GCT at 125° C. for turning off 4000A is reduced by about 4J (about 20%).

The local low minority carrier lifetime region affects the on-state voltage drop V _TM of the Integrated Gate Commutated Thyristors (IGCT). Due to the reduced lifetime of carriers injected into the P base region, the faster carrier recombination weakens the conductance modulation effect , resulting in an increase in _VTM . Figure 6 shows the typical structure of the GCT and the on-state voltage drop of the standard GCT at 4000A@normal temperature. As shown in Fig. 6, establishing low minority carrier lifetime regions in the P-base and N ^- base regions, the increase in on-state voltage drop is only about 0.1V, compared to their optimization for GCT turn-off capability and turn-off loss , a 0.1V rise in on-state voltage drop is perfectly acceptable. To sum up, the GCT of an embodiment of the present invention has little effect on the on-state voltage drop while improving the turn-off capability and reducing the turn-off loss.

The present invention also provides a method for manufacturing the gate commutated thyristor of the present invention. In one embodiment, the method includes:

Manufacture the chip whose structure from bottom to top is the chip's P ⁺ transparent emitting anode, N' buffer layer, N ^- base region, P base region and N ⁺ emitting region;

At least one low minority carrier lifetime region with a minority carrier lifetime lower than other regions is established in the N' buffer layer and the P base region of the chip respectively.

In one embodiment, the process of establishing the low minority carrier lifetime region includes:

After the chip completes the mesa passivation process, the anode surface of the chip is irradiated with protons or helium to establish the low minority carrier lifetime region;

Annealed.

In one embodiment, in the process of establishing the low minority carrier lifetime region in the N' buffer layer of the chip, the distance from the center of the irradiation region to the anode surface is 20 μm˜50 μm at least once.

In one embodiment, in the process of establishing the low minority carrier lifetime region in the P base region of the chip, the distance from the center of the irradiation region to the cathode surface is 30 μm˜140 μm at least once.

Specifically, in one embodiment, after the chip completes the mesa passivation process, the anode surface of the chip is irradiated twice with protons or helium ions on the N' buffer layer and the P base region of the chip to respectively establish a low minority carrier lifetime region.

Further, in one embodiment, the dose of proton or helium irradiation ranges from 1E9cm ^-3 to 1E13cm ^-3 .

Further, in an embodiment, in the annealing treatment, the annealing temperature is 200°C-400°C, and the annealing time is 8h-15h.

Further, in one embodiment, the method further includes:

After establishing the low minority carrier lifetime region, before performing the annealing treatment step, the overall lifetime value of the chip is controlled by electron irradiation so as to adjust the on-state voltage drop of the chip to a target value.

Specifically, in one embodiment, the complete process of chip manufacturing includes the following steps:

1) Preparation of N-type single crystal silicon substrate

An N-type doped single crystal silicon substrate is provided. The substrate doping concentration and the thickness of the substrate are mainly determined according to the GCT blocking voltage, on-state voltage drop and other parameter requirements.

2) P+ short base region formation

The P ⁺ base region of GCT is formed by B implantation and diffusion. Specifically, the entire surface of the P ⁺ base region is implanted first (as shown in Figure 6), and then the P ⁺ base region is advanced (as shown in Figure 7).

3) P base region formation

The fabrication of the P base region includes the formation of the P base region (as shown in FIG. 8 ) and the removal of the backside P-type doped layer (as shown in FIG. 9 ).

The manufacturing of P base area is carried out by aluminum injection diffusion or closed tube aluminum expansion process. The two process schemes are as follows:

a) Diffusion process of aluminum injection: First, the whole surface is implanted on the front surface of the single crystal silicon substrate, and the implanted impurity is Al+, and the implantation dose E _Al is determined according to the doping concentration of the P base region. Then, a layer of Si3N4 film is deposited by the Low Pressure Chemical Vapor Deposition (LPCVD) process, and then the high temperature push is performed in a nitrogen atmosphere to control the Al junction depth of the P base region within the design range, and then remove the P on the backside. type doped layer.

b) Closed tube aluminum expansion: in the vacuum furnace tube saturated aluminum atmosphere, carry out high temperature advance for a certain time t, the time t is controlled according to the design value of the Al junction depth in the P base region, and then remove the P-type doping layer on the backside.

The two processes have their own advantages and disadvantages: the surface quality of the chip formed by the aluminum injection diffusion process is better, and the subsequent formation of the cathode comb structure is used. The closed-tube aluminum expansion process is simple, and the mass production cost is low.

4) N' buffer layer formation

As shown in Figure 10, the N' buffer layer is implanted on the back of the single crystal silicon substrate, and the implanted impurity is _phosphorus . The junction depth of the N' buffer layer is controlled within the design range.

5) N ⁺ cathode comb bar formation

As shown in Figure 11, N ⁺ phosphorus diffusion is performed on the front surface of the single crystal silicon substrate, and the doping gas source flow rate and diffusion time in the phosphorus diffusion furnace are determined according to the doping concentration and junction depth of the N ⁺ comb structure. ⁺ The structure of the cathode comb layer is controlled within the design range. Then, selective etching is performed on the cathode comb layer to form a GCT cathode comb structure.

6) Transparent anode P ⁺ formation

As shown in Figure 12, the transparent anode P ⁺ layer is implanted on the back of the single crystal silicon substrate, and the implanted impurity is boron. The implantation dose E _AP depends on the doping concentration of the transparent anode P ⁺ layer, and then at high temperature It is advanced in a diffusion furnace to control the junction depth of the transparent anode P ⁺ layer within the design range.

7) Formation of metal electrode and mesa passivation

As shown in FIG. 13 , after the chip electrode metallization process, metal electrode layers are deposited on each surface of the die, and after etching, a GCT unit cell structure is formed.

8) Pluripotent proton irradiation

As shown in Figure 14, after the GCT unit cell structure is formed, the whole GCT chip is irradiated with protons or helium ions twice. By controlling the irradiation energy and dose, the position and lifetime of the low minority carrier lifetime region are controlled. The base region and the N' buffer layer region form two low minority carrier lifetime regions. Finally, an annealing treatment is performed after the irradiation is completed.

Next, two specific application examples according to the present invention are described respectively.

For 6500V asymmetric GCTs, fabrication methods include:

Fabrication of 6500V GCT chips with:

The resistivity range of N-type silicon single crystal is 470Ω·cm;

GCT chip thickness is 760μm to 770μm;

The doping concentration of the P base region ranges from 1E13cm ^-3 to 5E17cm ^-3 , and the junction depth ranges from 120 μm to 140 μm;

The N' buffer layer doping concentration ranges from 1E13cm ^-3 to 5E16cm ^-3 , and the junction depth is about 30 μm to 35 μm;

The N' buffer layer and the P base region of the chip are irradiated twice with protons or helium on the anode surface of the chip to establish the low minority carrier lifetime region, wherein:

The proton or helium irradiation area of the P base region is located at 110 μm-115 μm, and the proton or helium irradiation dose is 2E10cm ^-2 to 6E10cm ^-2 ;

The proton or helium irradiation area of the N' buffer layer is located at 30μm-35μm, and the proton or helium irradiation dose is 6E10cm ^-2 -1E11cm ^-2 ;

Implement electron irradiation to adjust the on-state voltage drop of the chip to the target value;

Perform annealing treatment at 200°C/10h-20h.

The final chip structure and corresponding minority carrier lifetime are shown in Figure 15.

For the 4500V reverse conduction type GCT chip, the manufacturing method includes:

Manufacture of 4500V reverse conduction type GCT chips, where:

The resistivity range of N-type silicon single crystal is 300Ω·cm,

Chip thickness is 540μm to 550μm,

The doping concentration of the P base region of the GCT part ranges from 1E13cm ^-3 to 5E17cm ^-3 , and the junction depth ranges from 115μm to 125μm;

The fast recovery diode (Fast Recovery Diode, FRD) part of the P base region doping concentration range is 1E13cm ^-3 to 5E18cm ^-3 , and the junction depth is 115μm to 125μm;

The doping concentration of the N' buffer layer in the GCT part ranges from 1E13cm ^-3 to 5E16cm ^-3 , and the junction depth is 30μm to 35μm;

The doping concentration of the N' buffer layer in the FRD part ranges from 1E13cm ^-3 to 5E16cm ^-3 , and the junction depth is about 40 μm to 45 μm;

On the anode surface of the chip, the N' buffer layer of the GCT part, the P base region and the P base region of the FRD part are respectively irradiated with protons or helium ions three times to establish the low minority carrier lifetime region, wherein:

The proton or helium irradiation area of the P base region of the GCT part is located at 60μm-70μm, and the proton or helium irradiation dose is 2E10cm ^-2 ;

The proton or helium irradiation area of the N' buffer layer of the GCT part is located at 30μm-35μm, and the proton or helium irradiation dose is 6E10cm ^-2 -1E11cm ^-2 ;

The proton or helium irradiation area of the P base region of the FRD part is located at 60 μm-70 μm, and the proton or helium irradiation dose is 1E12cm ^-2 -1E13cm ^-2 ;

Implement electron irradiation to adjust the on-state voltage drop of the chip to the target value;

Perform annealing treatment at 200°C/10h-20h.

The final chip structure and corresponding minority carrier lifetime are shown in Figure 16.

The present invention proposes to form a plurality of low minority carrier lifetime regions by reducing the local minority carrier lifetime of the GCT N' buffer zone and the P base region below the cathode comb (that is, the collective term for the P ⁺ short base region and the P base region), so as to reduce device turn-off. energy to improve the turn-off capability of the device. When the GCT is turned off, the low minority carrier lifetime region near the N' buffer zone is beneficial to extract the free carriers of the N ^- base region, shorten the anode current tailing time, reduce the turn-off loss, and maintain the advantage of GCT on-state voltage reduction; The low minority carrier lifetime region located in the P region under the GCT cathode comb is beneficial to extract the free carriers directly under the cathode comb, avoiding the J3 junction erroneously turned on due to the accumulation of free carriers generated by dynamic avalanche during turn-off, and the chip is turned off. break failure. To sum up, the solution proposed by the present invention is not only beneficial to reduce the turn-off loss of GCT, but also improves the turn-off capability of the device, maintains its advantage of low on-state voltage drop, is suitable for all types and sizes of GCT design, and can be manufactured The process method is simple.

Although the disclosed embodiments of the present invention are as above, the content described is only an embodiment adopted to facilitate understanding of the present invention, and is not intended to limit the present invention. There are also various other embodiments of the method described in the present invention. Without departing from the essence of the present invention, those skilled in the art can make various corresponding changes or deformations according to the present invention, but these corresponding changes or deformations should all belong to the protection scope of the claims of the present invention.

Claims (10)

1. A gate commutated thyristor, characterized in that the thyristor comprises a P ⁺ transparent emission anode, an N' buffer layer, an N ^- base region, a P base region and an N ⁺ emission region, wherein the N' buffer The layer and the P base region are respectively configured with at least one low minority carrier lifetime region with a lower minority carrier lifetime than other regions. 2 . The thyristor according to claim 1 , wherein the thyristor comprises two low minority carrier lifetime regions, and the low minority carrier lifetime regions are respectively constructed in the N′ buffer layer and the P base region. 3 . 3. A method for manufacturing a gate commutated thyristor, wherein the method comprises: Manufacture the chip whose structure from bottom to top is the chip's P ⁺ transparent emitting anode, N' buffer layer, N ^- base region, P base region and N ⁺ emitting region; At least one low minority carrier lifetime region with a minority carrier lifetime lower than other regions is established in the N' buffer layer and the P base region of the chip, respectively. 4. The method according to claim 3, wherein at least one low minority carrier lifetime region with a minority carrier lifetime lower than other regions is established in the N' buffer layer and the P base region of the chip respectively, comprising: After the chip completes the mesa passivation process, the anode surface of the chip is irradiated with protons or helium to establish the low minority carrier lifetime region; Annealed. 5 . The method according to claim 4 , wherein, in the process of establishing the low minority carrier lifetime region in the N′ buffer layer of the chip, the distance from the center of the irradiation region to the anode surface is 20 μm～ 50μm. 6 . The method according to claim 4 , wherein in the process of establishing the low minority carrier lifetime region in the P base region of the chip, the distance from the center of the irradiation region to the cathode surface is 30 μm˜140 μm at least once. 7 . . 7 . The method according to claim 4 , wherein the dose range of proton or helium irradiation is 1E9 cm ⁻³ to 1E13 cm ⁻³ . 8 . 8. The method according to claim 4, wherein the method further comprises: After establishing the low minority carrier lifetime region, electron irradiation is used to control the overall lifetime value of the chip before performing the annealing treatment step. 9. The method of claim 8, wherein the method comprises: Fabrication of 6500V GCT chips with: The resistivity range of N-type silicon single crystal is 470Ω·cm; GCT chip thickness is 760μm to 770μm; The P base region doping concentration ranges from 1E13cm ^-3 to 5E17cm ^-3 , and the junction depth ranges from 120μm to 140μm; The N' buffer layer doping concentration ranges from 1E13cm ^-3 to 5E16cm ^-3 , and the junction depth is about 30μm to 35μm; The N' buffer layer and the P base region of the chip are irradiated twice with protons or helium on the anode surface of the chip to establish the low minority carrier lifetime region, wherein: The proton or helium irradiation area of the P base region is located at 110 μm-115 μm, and the proton or helium irradiation dose is 2E10cm ^-2 to 6E10cm ^-2 ; The proton or helium irradiation area of the N' buffer layer is located at 30μm-35μm, and the proton or helium irradiation dose is 6E10cm ^-2 -1E11cm ^-2 ; Implement electron irradiation to adjust the on-state voltage drop of the chip to the target value; Perform annealing treatment at 200°C/10h-20h. 10. The method of claim 8, wherein the method comprises: Manufacture of 4500V reverse conduction type GCT chips, where: The resistivity range of N-type silicon single crystal is 300Ω·cm, Chip thickness is 540μm to 550μm, The doping concentration of the P base region of the GCT part ranges from 1E13cm ^-3 to 5E17cm ^-3 , and the junction depth ranges from 115μm to 125μm; The doping concentration of the P base region of the FRD part ranges from 1E13cm ^-3 to 5E18cm ^-3 , and the junction depth ranges from 115μm to 125μm; The doping concentration of the N' buffer layer in the GCT part ranges from 1E13cm ^-3 to 5E16cm ^-3 , and the junction depth is 30μm to 35μm; The doping concentration of the N' buffer layer in the FRD part ranges from 1E13cm ^-3 to 5E16cm ^-3 , and the junction depth is about 40μm to 45μm; On the anode surface of the chip, the N' buffer layer of the GCT part, the P base region, and the P base region of the FRD part are respectively irradiated with protons or helium three times to establish the low minority carrier lifetime region, wherein: The proton or helium irradiation area of the P base region of the GCT part is located at 60μm-70μm, and the proton or helium irradiation dose is 2E10cm ^-2 ; The proton or helium irradiation area of the N' buffer layer of the GCT part is located at 30μm-35μm, and the proton or helium irradiation dose is 6E10cm ^-2 -1E11cm ^-2 ; The proton or helium irradiation area of the P base region of the FRD part is located at 60 μm-70 μm, and the proton or helium irradiation dose is 1E12cm ^-2 -1E13cm ^-2 ; Implement electron irradiation to adjust the on-state voltage drop of the chip to the target value; Perform annealing treatment at 200°C/10h-20h.