CN110571187A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN110571187A CN110571187A CN201810570150.4A CN201810570150A CN110571187A CN 110571187 A CN110571187 A CN 110571187A CN 201810570150 A CN201810570150 A CN 201810570150A CN 110571187 A CN110571187 A CN 110571187A
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- contact hole
- layer
- dielectric layer
- top surface
- active region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the steps of forming an interlayer dielectric layer with a first contact hole and a second contact hole, wherein the first contact hole exposes the top surface of a first active region, the second contact hole exposes the top surface of a second active region, forming a filling layer with the top surface lower than the top surface of the interlayer dielectric layer in the first contact hole and the second contact hole, and enabling the part of the first contact hole above the filling layer and the part of the second contact hole above the filling layer to be in a shape with a wide top and a narrow bottom; on the other hand, the step coverage performance of the subsequent covering layer can be improved, so that the thickness uniformity of the covering layer is improved, the damage of the first active region in the etching process for forming the common contact hole can be avoided, the punch-through problem of the common contact hole for forming the common conductive plug is avoided, and the device performance is improved.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device.
background
with the continuous development of integrated circuit technology, the integration level of semiconductor devices is continuously improved, and the feature size of semiconductor devices is becoming smaller and smaller. The requirements for integrated circuit manufacturing processes, such as photolithography, etching, deposition, ion implantation, etc., are more stringent, and small process deviations can cause variations in device performance, thereby causing the overall circuit to deviate from design requirements. In the integrated circuit manufacturing process, after a semiconductor element structure such as a MOS transistor is formed on a semiconductor substrate, it is necessary to connect semiconductor elements together to form a circuit using a conductive plug formed in a contact hole, which connects semiconductor devices, and an interconnection line, which connects conductive plugs on different semiconductor elements to form a circuit. In order to further improve the integration level of the circuit and reduce the area occupied by the surfaces of the source region, the drain region and the gate structure of the MOS transistor as the conductive plugs of the electrical interconnection structure, in the current integrated circuit, the gate structure and the active region (including the source region or the drain region) which need to be connected with the same interconnection line and are adjacent share one conductive plug (that is, the contact hole where the shared conductive plug is located on the surface of the gate structure and the surface of the active region at the same time), and the conductive plugs at other positions are still independent of each other. However, the common conductive plug formed by the conventional method for manufacturing a semiconductor device has the problems of punch-through leakage (punch-through) and filling voids (cavities) in the common conductive plug, which cannot meet the requirements of device performance.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which can avoid punch-through of a contact hole for forming a common conductive plug, improve the problem of filling holes of each conductive plug and improve the performance of the device.
in order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
Providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate, and a first active region and a second active region are formed in the semiconductor substrate on two sides of the grid structure;
Forming an interlayer dielectric layer covering the surfaces of the semiconductor substrate and the gate structure, wherein the interlayer dielectric layer is provided with a first contact hole exposing the top surface of the first active region and a second contact hole exposing the top surface of the second active region;
forming a filling layer with the top surface lower than that of the interlayer dielectric layer in the first contact hole and the second contact hole, and enabling the parts of the first contact hole and the second contact hole above the filling layer to be in a shape with a wide top and a narrow bottom;
sequentially forming a covering layer and a patterned mask layer on the surface of the first contact hole and the surface of the interlayer dielectric layer, wherein the patterned mask layer is provided with openings corresponding to the top surface of the first active region and the top surface of the gate structure;
Etching the covering layer, the interlayer dielectric layer and the filling layer by taking the patterned mask layer as a mask so as to form a common contact hole exposing the top surface of the first active region and the top surface of the gate structure;
Removing the patterned mask layer and the residual covering layer and filling layer to re-expose the interlayer dielectric layer and expose the second contact hole on the top surface of the second active region;
And forming a common conductive plug respectively filled in the common contact hole and an independent conductive plug in the second contact hole on the top surface of the second active region.
Optionally, the gate structure is a polysilicon gate structure or a metal gate structure.
optionally, when the gate structure is a metal gate structure, the step of providing the semiconductor substrate on which the gate structure is formed includes:
Forming a pseudo gate structure on the semiconductor substrate, and forming a gate side wall on the side wall of the pseudo gate structure;
forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer exposes the top surface of the pseudo gate structure;
Removing the pseudo gate structure to form a gate groove;
And forming a metal gate structure filled in the gate trench.
optionally, after the gate sidewall spacer is formed and before the first dielectric layer is formed on the semiconductor substrate, the first active region and the second active region are formed in the semiconductor substrate on both sides of the dummy gate structure and the gate sidewall spacer.
Optionally, after the first active region and the second active region are formed and before the first dielectric layer is formed on the semiconductor substrate, a contact hole etching stop layer is formed first, and the contact hole etching stop layer covers the semiconductor substrate, the gate sidewall and the surface of the dummy gate structure; and after depositing a first dielectric layer on the semiconductor substrate, processing the first dielectric layer and the contact hole etching stop layer through a chemical mechanical polishing process or an etching process so as to expose the top surface of the pseudo gate structure.
Optionally, the first active region and the second active region are formed by an embedded source-drain process.
optionally, the step of forming the interlayer dielectric layer covering the surfaces of the semiconductor substrate and the gate structure includes:
depositing a second dielectric layer on the surfaces of the first dielectric layer, the metal gate structure and the gate side wall, and flattening the top surface of the second dielectric layer;
And sequentially etching the second dielectric layer and the first dielectric layer, wherein the etching is stopped at the top surfaces of the first source region and the second source region to form a first contact hole exposing the top surface of the first active region and a second contact hole exposing the top surface of the second active region, and the interlayer dielectric layer comprises the first dielectric layer and the second dielectric layer.
Optionally, the step of forming a filling layer with a top surface lower than the top surface of the interlayer dielectric layer in the first contact hole and the second contact hole includes:
covering filling layers on the surfaces of the interlayer dielectric layer, the first contact hole and the second contact hole, wherein the filling layers can at least fill the first contact hole and the second contact hole;
And carrying out back etching on the filling layer to enable the top surface of the filling layer to be lower than that of the interlayer dielectric layer, and simultaneously etching the interlayer dielectric layer to enable the part of the first contact hole above the filling layer and the part of the second contact hole above the filling layer to be in a shape with a wide top and a narrow bottom.
Optionally, before forming the capping layer, a portion of the interlayer dielectric layer above the filling layer is rounded.
optionally, the patterned mask layer is made of a photoresist, and after the common contact hole is formed, the photoresist is removed by using an ashing process, and the remaining cover layer and the filling layer are removed by using a wet etching process.
optionally, the covering layer and the filling layer are made of the same material.
The optional step of forming the common conductive plug and the independent conductive plugs comprises:
forming an adhesion layer on the surfaces of the interlayer dielectric layer, the common contact hole and the second contact hole;
Forming a conductive metal layer on the surface of the adhesion layer, wherein the conductive metal layer at least fills the second contact hole and the common contact hole;
and flattening the top surface of the conductive metal layer to the top surface of the interlayer dielectric layer to form the common conductive plug and the independent conductive plugs.
Optionally, a metal silicide is further formed between the common conductive plug and the gate structure, between the top surfaces of the first active regions, and between the independent conductive plug and the top surface of the second active region.
Optionally, a plurality of gate structures are formed on the semiconductor substrate, two adjacent gate structures share one first active region or one second active region, and when two adjacent gate structures share one first active region, the shared contact hole exposes the first active region shared by two adjacent gate structures and a top surface of one of the two adjacent gate structures.
Optionally, in the step of forming an interlayer dielectric layer covering the surfaces of the semiconductor substrate and the gate structures, a gate contact hole exposing a top surface of another one of the two adjacent gate structures is further formed in the interlayer dielectric layer.
Compared with the prior art, the manufacturing method of the semiconductor device of the invention forms the filling layer with the top surface lower than the top surface of the interlayer dielectric layer in the first contact hole and the second contact hole after forming the interlayer dielectric layer with the first contact hole exposing the top surface of the first active area and the second contact hole exposing the top surface of the second active area, and makes the part of the first contact hole above the filling layer and the part of the second contact hole above the filling layer become the shape with wide top and narrow bottom, on one hand, the filling process window of the subsequent independent conductive plug can be widened, and the problem of filling the cavity is improved; on the other hand, the step coverage performance of the subsequent covering layer can be improved, so that the thickness uniformity of the covering layer is improved, the damage of the first active region in the etching process for forming the common contact hole can be avoided, the punch-through problem of the common contact hole for forming the common conductive plug is avoided, and the device performance is improved.
drawings
FIGS. 1A to 1D are schematic cross-sectional views of a device structure in a process of manufacturing a semiconductor device;
FIG. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention;
fig. 3A to 3G are schematic cross-sectional views of device structures in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
the size of the conductive plug formed on the surface of the source region, the drain region and the gate structure as an electrical interconnection structure is limited by the process, and the size is not easy to become small, so that the size of the source region, the drain region and the gate structure cannot be too small due to the size of the conductive plug, and the integration level of the semiconductor device cannot be continuously improved, for this reason, the prior art proposes a manufacturing method of the semiconductor device, which uses a conductive plug to share an active region (which may be the source region or the drain region) and a gate structure, which need to be connected with the same interconnection line and are adjacent to the same interconnection line, so as to reduce the size of the active region and the gate structure, and the specific process comprises the following steps:
first, referring to fig. 1A, a gate structure 101 (including a gate dielectric layer 1011 and a gate electrode layer 1012) of a MOS transistor is formed on a semiconductor substrate 100, a gate sidewall 101A is formed on a sidewall of the gate structure 101, and a first active region 103 (which may be a drain region or a source region) and a second active region 102 (which may be a source region or a drain region) are formed in the semiconductor substrate 100 at two sides of the gate structure 101 and the gate sidewall 101A;
Then, with reference to fig. 1A, sequentially covering the surfaces of the gate structure 101, the gate sidewall 101A, the first active region 103 and the second active region 102 with a contact hole etching stop layer 104 and an interlayer dielectric layer 105, and etching the interlayer dielectric layer 105 and the contact hole etching stop layer 104 (i.e., M0Etch process), so as to form a contact hole 106 exposing the top surface of the first active region 103 and a contact hole 107 exposing the top surface of the second active region 102;
then, referring to fig. 1B, an Organic Dielectric Layer (ODL)108 is coated on the surface of the interlayer dielectric layer 105 and the surfaces of the contact holes 106 and 107 (i.e., M0G ODL coating process), the contact holes 106 and 107 are filled with the Organic Dielectric Layer (ODL)108, and a certain thickness is formed above the contact holes 106 and 107; then, a bottom anti-reflection layer (BARC)109 and a patterned photoresist layer 110 are sequentially formed on the surface of the organic dielectric layer 108 (i.e., a MOG Photo process), wherein the patterned photoresist layer 110 has an opening 110a corresponding to the first active region 103 and the top surface of the gate structure 101;
next, referring to fig. 1B and 1C, with the patterned photoresist layer 110 as a mask, sequentially etching the bottom anti-reflection layer 109, the organic dielectric layer 108, the interlayer dielectric layer 105, and the contact hole etching stop layer 104 until the top surface of the first active region 103 and the top surface of the gate structure 101 are exposed, thereby forming a contact hole 106a capable of simultaneously exposing the top surface of the first active region 103 and the top surface of the gate structure 101, and removing the patterned photoresist layer 110, the bottom anti-reflection layer 109, and the organic dielectric layer 108 to re-expose the contact hole 107 on the top surface of the second active region 102;
then, by deposition of a conductive metal (which may be tungsten W), Chemical Mechanical Polishing (CMP), or the like, the conductive plug 111 filled in the contact hole 106a and the conductive plug 112 filled in the contact hole 107 are formed.
In the above-mentioned method for manufacturing a semiconductor device, on one hand, due to the large aspect ratio of the contact holes 106 and 107, the organic dielectric layer 108 coated on the surface of the interlayer dielectric layer 105 and the surfaces of the contact holes 106 and 107 may be recessed (deforming) in the regions of the contact holes 106 and 107, resulting in the uneven top surface of the organic dielectric layer 108, thereby causing a large process deviation of the pattern in the patterned photoresist layer 110 formed above the organic dielectric layer 108, and then easily causing the insufficient thickness of the organic dielectric layer 108 in the region and the loss (loss, as shown by the dashed line leakage block in fig. 1C) of the first active region 103 when the contact hole 106a is formed by etching, so that the formed contact hole 106a has a punch-through problem, and the formed common plug has a punch-through phenomenon; on the other hand, since the aspect ratio of the contact hole 107 is much larger than that of the contact hole 106a, when conductive metal is deposited into the contact hole 106a and the contact hole 107 at the same time, a filling void 112a is easily formed in the contact hole 107, and after CMP of the conductive metal, the void 112a may be completely exposed, thereby causing problems such as conductive plug missing or even failure, and affecting the device performance.
based on the above, the present invention provides a method for manufacturing a semiconductor device, which can avoid the recess of a coated organic dielectric layer in a contact hole region, so as to avoid the increase of the top opening width of each contact hole in the first active region, and can avoid the punch-through of the contact holes for forming a common conductive plug, improve the problem of filling holes of each conductive plug, and improve the device performance.
The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
referring to fig. 2, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:
S1, providing a semiconductor substrate, wherein a gate structure is formed on the semiconductor substrate, and a first active region and a second active region are formed in the semiconductor substrate on two sides of the gate structure;
s2, forming an interlayer dielectric layer covering the surfaces of the semiconductor substrate and the grid structure, wherein the interlayer dielectric layer exposes a first contact hole on the top surface of the first active region and a second contact hole on the top surface of the second active region;
S3, forming a filling layer with a top surface lower than that of the interlayer dielectric layer in the first contact hole and the second contact hole, and enabling the parts of the first contact hole and the second contact hole above the filling layer to be in a shape with a wide top and a narrow bottom;
S4, sequentially forming a covering layer and a patterned mask layer on the surface of the first contact hole and the surface of the interlayer dielectric layer, wherein the patterned mask layer is provided with openings corresponding to the top surface of the first active region and the top surface of the gate structure;
S5, with the patterned mask layer as a mask, etching the covering layer, the interlayer dielectric layer and the filling layer to form a common contact hole exposing the top surface of the first active region and the top surface of the gate structure;
S6, removing the patterned mask layer and the residual covering layer and filling layer to re-expose the interlayer dielectric layer and expose the second contact hole on the top surface of the second active region;
and S7, forming a common conductive plug filled in the common contact hole and an independent conductive plug filled in the second contact hole on the top surface of the second active region.
referring to fig. 3A, in step S1, the semiconductor substrate 300 is provided to provide a platform for subsequent processes, wherein the material of the platform may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like; other materials, such as III-V compounds such as gallium arsenide, are also possible. The semiconductor substrate 300 is also formed with a well structure and an isolation structure inside, which may be a shallow trench isolation structure, or other isolation structures for device isolation or active area isolation known to those skilled in the art. In addition, when the semiconductor device to be formed is a FinFET device, a plurality of protruding fins (Fin, not shown) and shallow trench isolation structures (not shown) located between two adjacent fins and having top surfaces flush with or lower than the top surfaces of the fins may also be formed in the semiconductor substrate 300. In step S1, a gate structure 301 may be formed on the semiconductor substrate 300 through a gate formation process, where the gate structure 301 may be a polysilicon gate structure or a metal gate structure, and includes a gate dielectric layer 3011 and a gate electrode layer 3012; a gate sidewall spacer 301a may be further formed on the sidewall of the gate structure 301; and a first active region 303 and a second active region 302 are formed in the semiconductor substrate 300 on both sides of the gate structure 301 through a source-drain formation process. When the gate structure 301 is a metal gate structure, the step of providing the semiconductor substrate 300 on which the gate structure 301 is formed includes:
First, a silicon dioxide gate dielectric layer (not shown) may be formed on the surface of the semiconductor substrate 300 by a deposition process or a thermal oxidation process, etc., a dummy gate material layer (not shown) may be further deposited on the surface of the silicon dioxide gate dielectric layer by the deposition process, the material of the dummy gate material layer may include at least one of polysilicon (including doped polysilicon and/or undoped polysilicon), amorphous silicon (including doped amorphous silicon and/or undoped amorphous silicon), amorphous carbon, photoresist and metal silicide, and a part of the dummy gate material layer and the silicon dioxide gate dielectric layer (not shown) are removed by a photolithography and etching process, so as to form a dummy gate structure (i.e., including the remaining silicon dioxide gate dielectric layer and the dummy gate material layer) on the surface of the semiconductor substrate 300, and when there is a fin on the semiconductor substrate 300, the dummy gate structure surrounds the sidewalls and the top surface of the fin, the dummy Gate structure needs to be replaced by a High-K Metal Gate (HKMG) structure through a Gate Last process, and the height of the subsequently formed High-K Metal Gate structure is determined by the thickness of the dummy Gate structure;
Then, depositing a side wall material on the surface of the dummy gate structure and the semiconductor substrate 300 by using processes such as chemical vapor deposition, and etching the deposited side wall material to form a gate side wall 301a for protecting the side wall of the dummy gate structure, wherein the gate side wall 301a may be a single-layer structure or a stacked structure, and the material thereof includes silicon nitride;
Then, LDD (lightly doped drain) implantation, HALO (pocket) implantation, heavily doped source/drain ion implantation, and the like may be performed on the semiconductor substrate outside the gate sidewall 301a by using the dummy gate structure and the gate sidewall 301a as masks to form a first active region 303 (which may be a drain region or a source region) and a second active region 302 (which may be a source region or a drain region); or, forming the raised source and drain regions by using an embedded source and drain process, specifically including: etching the semiconductor substrate 300 on two sides of the dummy gate structure by taking the dummy gate structure and the gate side wall 301a as masks to form a source-drain groove, and epitaxially growing a semiconductor layer which is different from the semiconductor substrate 300 in the source-drain groove until the top of the grown semiconductor layer exceeds the top of the semiconductor substrate 300 by a certain thickness (when the semiconductor substrate 300 is provided with fins, the top of the grown semiconductor layer exceeds the top of the fins), so as to form a raised embedded source-drain region;
then, a Contact Etching Stop Layer (CESL) 304 and a first dielectric layer 3051 are sequentially deposited on the surface of the semiconductor substrate 300 with the raised embedded source/drain regions, the top surface of the dummy gate structure, and the sidewalls and the top surfaces of the gate spacers 301a by using chemical vapor deposition (cvd), coating (coating), and other processes, so as to form a Contact Etching Stop Layer (CESL)The contact hole etch stop layer 304 may be made of silicon nitride (SiN), silicon oxynitride (SiON), or silicon oxide (SiO)2) Or a combination thereof, the material of the first dielectric layer 3051 is different from the contact hole etch stop layer 304, so as to achieve a higher etch selectivity in a subsequent etching process for removing the first dielectric layer 3051, the material of the first dielectric layer 3051 may include silicon dioxide, silicon oxynitride, Tetraethylorthosilicate (TEOS), a low-K dielectric material having a dielectric constant smaller than that of silicon dioxide, metal silicon nitride, and the like, the deposition thickness of the first dielectric layer 3051 on the surface of the semiconductor substrate 300 is greater than the thickness of the dummy gate structure, and then the top surface of the first dielectric layer 3051 may be planarized by a chemical mechanical polishing process (CMP, also referred to as a chemical mechanical planarization process) until the top surface of the dummy gate structure is exposed, so as to expose the top portions of the dummy gate structure and the gate sidewall 301a, or the first dielectric layer 3051 may be etched by a back etching process (Blanket etch back), to expose the top surface of the dummy gate structure, and at this time, the top of the gate sidewall spacer 301a may be exposed at the same time;
Then, firstly, a dry etching process can be adopted to carry out primary etching on the pseudo gate structure, and then a wet etching process is adopted to etch and remove the residual pseudo gate structure (comprising the pseudo gate material layer and the silicon dioxide gate dielectric layer) so as to form a gate groove;
Then, sequentially depositing a high-K gate dielectric layer (i.e., 3011 in fig. 3A) and a metal gate layer (i.e., 3012 in fig. 3A) at least filling up the gate trench on the surfaces of the first dielectric layer 3051 and the gate trench, and then performing chemical mechanical polishing on the deposited metal gate layer to the surface of the first dielectric layer 3051 to form a high-K metal gate structure (i.e., 301 in fig. 3A), wherein the high-K dielectric layer is generally formed by an Atomic Layer Deposition (ALD), so as to ensure that the deposited high-K dielectric layer has excellent coverage (compatibility) on the sidewall and the bottom of the gate trench, and the material of the high-K dielectric layer may be one or more of hafnium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, and hafnium zirconium oxide; the metal gate layer can comprise a work function metal layer and a metal gate electrode layer, wherein the work function metal layer is generally formed by a Radio Frequency Physical Vapor Deposition (RFPVD) method and can be made of one or more of Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN and TiAlN, the TiN is commonly used as the work function metal layer in the metal gate of a P-type metal oxide semiconductor (PMOS), and the TiAl is commonly used as the work function metal layer in the metal gate of an N-type metal oxide semiconductor (NMOS); then, the metal gate electrode layer is usually deposited by vacuum evaporation, sputtering, electroplating or chemical vapor deposition, and the material may be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and WSi. In addition, before the work function metal layer is deposited, at least one metal barrier layer for blocking the metal gate electrode layer and the diffusion of the metal in the work function metal layer into the high-K gate dielectric layer may be formed on the surface of the high-K dielectric layer, and after the work function metal layer is deposited and before the metal gate electrode layer is deposited, at least one metal barrier layer for blocking the downward diffusion of the metal in the metal gate electrode layer may be formed on the surface of the work function metal layer.
In addition, in order to reduce the contact resistance between the subsequently formed conductive plug and the first active region, the second active region and the gate structure, a metal silicide may be formed on the surfaces of the first active region, the second active region and the gate structure.
with reference to fig. 3A, in step S2, first, in order to avoid unnecessary damage to the top surface of the gate structure 301 caused by the subsequent processes and ensure the performance of the gate structure 301, an etching protection layer 3052 may be covered on the surfaces of the gate structure 301 and the first dielectric layer 3051 by using processes such as chemical vapor deposition, atomic layer deposition, and the like; then, a deposition process may be used to form a second dielectric layer 3053 on the surface of the etching protection layer 3052, and a chemical mechanical polishing process (CMP, also referred to as a chemical mechanical planarization process) is used to planarize the top surface of the second dielectric layer 3053, so as to provide a planar process platform for subsequent processes, where the first dielectric layer 3051, the etching protection layer 3052, and the second dielectric layer 3053 form the interlayer dielectric layer 305 in this embodiment, the second dielectric layer 3053 may be made of the same material as or different from the first dielectric layer 3051, and the second dielectric layer 3053 may be made of silicon dioxide, silicon oxynitride, silicon carbide, silicon carbonitride, tetraethyl orthosilicate (TEOS), a low-K dielectric material with a dielectric constant smaller than that of silicon dioxide, silicon metal nitride, and the like; next, a hard mask layer and a patterned photoresist layer (having a pattern defining a first contact hole) are formed on the surface of the second dielectric layer 3053, and the hard mask layer, the second dielectric layer 3053, the etching protection layer 3052, the first dielectric layer 3051 and the contact hole etching stop layer 304 are sequentially etched using the patterned photoresist layer as a mask, thereby forming a first contact hole 306 exposing the top surface of the first active region 303 and a second contact hole 307 exposing the top surface of the second active region 302. When some of the gate structures formed on the semiconductor substrate 300 need to have gate contact holes formed separately, gate contact holes (not shown) exposing the top surfaces of these gate structures may be formed simultaneously in this step. That is, a plurality of gate structures may be formed on the semiconductor substrate 300, two adjacent gate structures share one of the first active region 303 or one of the second active region 302, and when two adjacent gate structures share one of the first active region 303, the step S2 may further form a gate contact hole (not shown) exposing a top surface of one of the two adjacent gate structures, and the common contact hole formed in the subsequent step S5 exposes the first active region 303 shared by the two adjacent gate structures and a top surface of the other of the two adjacent gate structures.
Referring to fig. 3B and 3C, in step S3, first, a filling material may be coated on the second dielectric layer 3053 and the surface of each first contact hole by a deposition process or a coating process, the filling material may be different from the first dielectric layer 3051, the etching protection layer 3052 and the second dielectric layer 3053, for example, an organic dielectric material (ODL) or amorphous carbon (SOC), and the filling material has a thickness at least filling each first contact hole; then, the filling material may be etched back by using a dry etching process or the like, to remove excess filling material above the second dielectric layer 3053, and to make the top surface of the filling material in each first contact hole lower than the top surface of the second dielectric layer 3053, and at the same time, to remove a portion of the second dielectric layer 3053 on the sidewall of the top of each first contact hole, so as to form a filling layer 308 with a top surface lower than the top surface of the second dielectric layer 3053 in each first contact hole, and to make a portion of the first contact hole 306 above the filling layer 308 and a portion of the second contact hole 307 above the filling layer 308 change into a shape with a wide top and a narrow bottom (e.g., an inverted trapezoid shape); then, a portion of the second dielectric layer 3053 above the filling layer 308 is rounded (trench top rounding) by using a plasma etching process or the like, so that at least a top corner of the portion of the second dielectric layer 3053 above the filling layer 308 is rounded, that is, a top corner of both the portion of the first contact hole 306 above the filling layer 308 and the portion of the second contact hole 307 above the filling layer 308 are rounded. As a result of the step S3, on one hand, the aspect ratio of the filling window of the subsequent covering layer can be reduced, the step coverage capability can be improved, and the thickness of the formed covering layer can be uniform; on the other hand, the aspect ratio of the first contact hole 306 and the second contact hole 307 can be reduced, and a gap-fill window (gap-fill window) of the subsequent independent conductive plug is increased, which is beneficial to the subsequent filling of the independent conductive plug and improves the problem of filling the cavity.
Referring to fig. 3D, in step S4, first, a capping layer 309, a bottom anti-reflection layer 310 and a photoresist layer may be sequentially formed on the surfaces of the first contact hole 306 and the second contact hole 307 and the surface of the second dielectric layer 3053 through a deposition process or a coating process; then, the photoresist layer is patterned by a photolithography process such as exposure and development to form a patterned mask layer 311 (including the bottom anti-reflection layer 310 and the remaining photoresist layer in this embodiment), where the patterned mask layer 311 has an opening 311a corresponding to the top surface of the first active region 303 and the area of the top surface of the gate structure 301. Since the step S3 forms the filling layer 308 with a certain height in the first contact hole 306 and the second contact hole 307 in advance, and the first contact hole 306 and the second contact hole 307 above the filling layer 308 are rounded, the step coverage performance of the capping layer 309 in this step is excellent, and a relatively flat top surface can be provided, so that the pattern effect of the patterned mask layer 311 can be ensured, and an excessive process variation (overlay) can be avoided.
referring to fig. 3D and fig. 3E, in step S5, the patterned mask layer 311 is used as a mask, and an appropriate etching process is selected according to the material of each layer to sequentially etch the bottom anti-reflection layer 310, the cap layer 309, the second dielectric layer 3053, the filling layer 308, the etching protection layer 3052, and the first dielectric layer 3051, so as to form a common contact hole 306a exposing the top surface of the first active region 303 and the top surface of the gate structure 301, where the common contact hole 306a substantially consists of the first contact hole 306 on the top surface of the first active region 303 and the space above the top surface of the gate structure 301 shown in fig. 3A; in this step, since the thickness of the capping layer formed in step S4 is relatively uniform in each region, and the precision of the position and shape of the opening in the patterned mask layer 311 is high, when the common contact hole 306a is formed by etching, the loss of the first active region 303 due to stack deviation and over-etching, that is, the problem of punch-through of the common contact hole 306a, does not occur. In step S4, the area of the second contact hole 307 over the second active region 302 is protected from etching by the patterned mask layer 311.
referring to fig. 3E, in step S6, the patterned mask layer 311 may be removed by an oxygen ashing process; capping layer 309 and fill layer 308 may then be separately etched away using a suitable wet etch process to re-expose second contact holes 307 on the top surface of second dielectric layer 3053 and the top surface of second active region 302, and when there are separate gate contact holes on the top surfaces of some gate structures, step S6 also exposes gate contact holes on the top surfaces of those gate structures.
Referring to fig. 3F and 3G, in step S7, first, an adhesion layer (glue layer)312, which may be Ti, Ta, TiN, TaN, or TaN, is formed on the surfaces of the common contact hole 306a, the second contact hole 307, and the second dielectric layer 3053 by vacuum sputtering, and the like, wherein the adhesion layer 312 may be a single-layer structure or a multi-layer stacked structure, and the adhesion layer 312 may be used to improve adhesion between the conductive metal layer 313 filled subsequently and the first dielectric layer 3051 and the second dielectric layer 3053, and prevent the conductive metal layer 313 from reacting with the first dielectric layer 3051 and the second dielectric layer 3053; then, the common contact hole 306a and the second contact hole 307 may be filled with a conductive metal layer 313 by electroplating, sputtering, or the like until the common contact hole 306a and the second contact hole 307 are filled with the conductive metal layer 313, and further, a top surface of the conductive metal layer 313 is planarized by a CMP process to a surface of the second dielectric layer 3053, thereby forming a common conductive plug filled in the common contact hole 306a and an independent conductive plug filled in the second contact hole 307 on a top surface of the second active region 302, and providing a planar process window for a subsequent process. The material of the conductive metal layer 313 may be at least one selected from aluminum, silver, chromium, nickel, palladium, molybdenum, titanium, tantalum, tungsten, cobalt, and copper. The common conductive plug filled in the common contact hole 306a is shared by the gate structure 301 and the first active region 303 adjacent to one side thereof, and the independent conductive plug filled in the second contact hole 307 on the top surface of the second active region 302 is independently used by the second active region 302. When there are separate gate contact holes on the top surfaces of some gate structures, the gate contact holes on the top surfaces of these gate structures are simultaneously exposed in step S6, and then gate conductive plugs filled in the gate contact holes are simultaneously formed in step S7.
In summary, in the manufacturing method of the semiconductor device of the present invention, after forming the interlayer dielectric layer having the first contact hole exposing the top surface of the first active region and the second contact hole exposing the top surface of the second active region, the filling layer having a top surface lower than the top surface of the interlayer dielectric layer is formed in the first contact hole and the second contact hole, and the portion of the first contact hole above the filling layer and the portion of the second contact hole above the filling layer are changed into a shape with a wide top and a narrow bottom, so that on one hand, a subsequent filling process window (gap-fill window) of the independent conductive plug can be widened, and the problems of filling a void (video) and an independent conductive plug missing (missing) are improved; on the other hand, the step coverage performance of the subsequent covering layer can be improved, so that the thickness uniformity of the covering layer is improved, the damage of the first active region in the etching process for forming the common contact hole can be avoided, and the punch-through problem of the common contact hole for forming the common conductive plug is avoided. The technical method is suitable for various metal interconnection processes and various processes needing protection of a source region, a drain region and the like.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (15)
1. A method of manufacturing a semiconductor device, comprising the steps of:
Providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate, and a first active region and a second active region are formed in the semiconductor substrate on two sides of the grid structure;
Forming an interlayer dielectric layer covering the surfaces of the semiconductor substrate and the gate structure, wherein the interlayer dielectric layer is provided with a first contact hole exposing the top surface of the first active region and a second contact hole exposing the top surface of the second active region;
Forming a filling layer with the top surface lower than that of the interlayer dielectric layer in the first contact hole and the second contact hole, and enabling the parts of the first contact hole and the second contact hole above the filling layer to be in a shape with a wide top and a narrow bottom;
sequentially forming a covering layer and a patterned mask layer on the surface of the first contact hole and the surface of the interlayer dielectric layer, wherein the patterned mask layer is provided with openings corresponding to the top surface of the first active region and the top surface of the gate structure;
etching the covering layer, the interlayer dielectric layer and the filling layer by taking the patterned mask layer as a mask so as to form a common contact hole exposing the top surface of the first active region and the top surface of the gate structure;
Removing the patterned mask layer and the residual covering layer and filling layer to re-expose the interlayer dielectric layer and expose the second contact hole on the top surface of the second active region;
forming a common conductive plug filled in the common contact hole and an independent conductive plug filled in a second contact hole on a top surface of the second active region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the gate structure is a polysilicon gate structure or a metal gate structure.
3. the method for manufacturing a semiconductor device according to claim 2, wherein when the gate structure is a metal gate structure, the step of providing the semiconductor substrate on which the gate structure is formed includes:
forming a pseudo gate structure on the semiconductor substrate, and forming a gate side wall on the side wall of the pseudo gate structure;
forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer exposes the top surface of the pseudo gate structure;
removing the pseudo gate structure to form a gate groove;
And forming a metal gate structure filled in the gate trench.
4. The method for manufacturing the semiconductor device according to claim 3, wherein the first active region and the second active region are formed in the semiconductor substrate on both sides of the dummy gate structure and the gate sidewall after the gate sidewall is formed and before the first dielectric layer is formed on the semiconductor substrate.
5. the method for manufacturing a semiconductor device according to claim 4, wherein a contact hole etching stop layer is formed after the first active region and the second active region are formed and before a first dielectric layer is formed on the semiconductor substrate, and the contact hole etching stop layer covers the semiconductor substrate, the gate sidewall and the surface of the dummy gate structure; and after depositing a first dielectric layer on the semiconductor substrate, processing the first dielectric layer and the contact hole etching stop layer through a chemical mechanical polishing process or an etching process so as to expose the top surface of the pseudo gate structure.
6. the method for manufacturing a semiconductor device according to claim 4, wherein the first active region and the second active region are formed by an embedded source-drain process.
7. the method of manufacturing a semiconductor device according to claim 3, wherein the step of forming the interlayer dielectric layer covering the surface of the semiconductor substrate and the gate structure comprises:
depositing a second dielectric layer on the surfaces of the first dielectric layer, the metal gate structure and the gate side wall, and flattening the top surface of the second dielectric layer;
And sequentially etching the second dielectric layer and the first dielectric layer, wherein the etching is stopped at the top surfaces of the first source region and the second source region to form a first contact hole exposing the top surface of the first active region and a second contact hole exposing the top surface of the second active region, and the interlayer dielectric layer comprises the first dielectric layer and the second dielectric layer.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming a filling layer having a top surface lower than a top surface of the interlayer dielectric layer in the first contact hole and the second contact hole comprises:
covering filling layers on the surfaces of the interlayer dielectric layer, the first contact hole and the second contact hole, wherein the filling layers can at least fill the first contact hole and the second contact hole;
and carrying out back etching on the filling layer to enable the top surface of the filling layer to be lower than that of the interlayer dielectric layer, and simultaneously etching the interlayer dielectric layer to enable the part of the first contact hole above the filling layer and the part of the second contact hole above the filling layer to be in a shape with a wide top and a narrow bottom.
9. the method of manufacturing a semiconductor device according to claim 1 or 8, wherein a portion of the interlayer dielectric layer above the filling layer is rounded before forming the capping layer.
10. the method of manufacturing a semiconductor device according to claim 1, wherein the material of the patterned mask layer includes a photoresist, and after the common contact hole is formed, the photoresist is removed by an ashing process, and the remaining capping layer and the filling layer are removed by a wet etching process.
11. The method for manufacturing a semiconductor device according to claim 1, wherein the material of the cap layer and the material of the filling layer are the same.
12. the method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the common conductive plug and the individual conductive plugs comprises:
forming an adhesion layer on the surfaces of the interlayer dielectric layer, the common contact hole and the second contact hole;
Forming a conductive metal layer on the surface of the adhesion layer, wherein the conductive metal layer at least fills the second contact hole and the common contact hole;
and flattening the top surface of the conductive metal layer to the top surface of the interlayer dielectric layer to form the common conductive plug and the independent conductive plugs.
13. The method for manufacturing a semiconductor device according to claim 1 or 12, wherein a metal silicide is further formed between the common conductive plug and the gate structure, between a top surface of the first active region, and between the independent conductive plugs and a top surface of the second active region.
14. the method of manufacturing a semiconductor device according to claim 1, wherein a plurality of gate structures are formed on the semiconductor substrate, two adjacent gate structures share one of the first active region or one of the second active region, and when two adjacent gate structures share one of the first active region, the common contact hole exposes the first active region shared by two adjacent gate structures and a top surface of one of the two adjacent gate structures.
15. the method for manufacturing a semiconductor device according to claim 14, wherein in the step of forming an interlayer dielectric layer covering the surfaces of the semiconductor substrate and the gate structures, a gate contact hole exposing a top surface of the other of two adjacent gate structures is further formed in the interlayer dielectric layer.
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