CN110553645B - Dual-system clock synchronization processing method based on periodic pulse reference - Google Patents
Dual-system clock synchronization processing method based on periodic pulse reference Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/10—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration
- G01C21/12—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning
- G01C21/16—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning by integrating acceleration or speed, i.e. inertial navigation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/20—Instruments for performing navigational calculations
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Abstract
The invention discloses a dual-system clock synchronization processing method based on a periodic pulse reference, and relates to the technical field of clock synchronization processing. According to the dual-system clock synchronization processing method, the clock synchronization is not needed when the data acquisition is carried out on the respective sensors of the master system and the slave system, when the data acquisition is completed, and after the data acquired by the master system is resolved and the resolving result is completely sent to the slave system, the clocks of the master system and the slave system are synchronized through the periodic pulse reference signal generated by the master system, and meanwhile, the synchronization signal sent by the programmable logic device of the slave system enables the digital signal processor of the slave system to start navigation resolving processing on the data acquired by the slave system according to the resolving result of the master system, so that the synchronous processing of the effective data of the master system and the slave system is realized, and the problem of poor combined navigation resolving effect caused by asynchronous effective data processing is solved.
Description
Technical Field
The invention belongs to the technical field of clock synchronization processing, and particularly relates to a dual-system clock synchronization processing method based on a periodic pulse reference.
Background
Different single systems are integrated, and the combined data are complemented by effective data provided by each system, so that a navigation system with high performance index and powerful functions is formed in a common group, which is called as combined navigation. With the development of navigation technologies, the types of navigation systems are increasing, and it is a necessary trend of the development of navigation technologies to combine multiple navigation technologies to form a combined navigation system.
The single system adopts an internal unified clock reference, acquires sensor data at a certain sampling frequency, performs navigation calculation and obtains a related calculation result. A dual-system combined navigation mode is adopted, and the traditional method is that a digital signal processing chip sets a certain control period through a timer, completes data sampling in the control period, and performs navigation calculation by sampling data with multiple control periods. Due to the fact that frequency and phase are affected by environment, the change results are different, and the like, clock asynchronization exists on respective clock references of the double systems, the problem that effective data of the double systems are not synchronous in processing is caused, and the integrated navigation resolving result is greatly affected.
Disclosure of Invention
Aiming at the problem of poor combined navigation resolving result caused by asynchronous dual-system clock reference in the prior art, the invention provides a dual-system clock synchronization processing method based on periodic pulse reference, which realizes clock synchronization of a master system and a slave system by using periodic pulse reference signals generated by a master system, thereby realizing synchronous processing of effective data.
The invention solves the technical problems through the following technical scheme: a dual-system clock synchronization processing method based on periodic pulse reference comprises the following steps:
step 1: the master system and the slave system respectively complete the acquisition of the data of the respective sensors, and the data acquired by the master system is resolved and then the resolved result is sent to the slave system;
step 2: the programmable logic device of the master system generates a periodic pulse reference signal by taking an internal clock of the programmable logic device as a reference, and transmits the periodic pulse reference signal to the slave system, and the programmable logic device of the slave system recognizes the rising edge of the periodic pulse reference signal;
and step 3: the programmable logic device of the slave system synchronously resets the counter by taking an internal clock as a reference and generates a sampling period, meanwhile, the programmable logic device of the slave system sends a synchronous signal to the digital signal processor of the slave system, and the digital signal processor of the slave system carries out navigation calculation processing on data acquired by the slave system according to a calculation result of the master system.
According to the dual-system clock synchronization processing method, the clock synchronization is not needed when the master system and the slave system acquire data through respective sensors, when the data acquisition is completed, and after the data acquired by the master system are resolved and the resolving result is sent to the slave system, the clocks of the master system and the slave system are synchronized through the periodic pulse reference signal generated by the master system, and meanwhile, the synchronization signal sent by the programmable logic device of the slave system enables the digital signal processor of the slave system to start navigation resolving processing on the data acquired by the slave system according to the resolving result of the master system, so that the synchronous processing of the effective data of the master system and the slave system is realized, and the problem of poor combined navigation (dual-system) resolving effect caused by asynchronous effective data processing is avoided; the clock synchronization processing method takes the synchronization signal as an external interrupt input source of the slave system digital signal processor, and does not need to adopt a timer to generate periodic interrupt, thereby reducing the resource use, reducing the design cost and improving the reliability of the design.
Further, in step 2, the periodic pulse reference signal is transmitted to the slave system in an RS422 communication manner, and the RS422 transmission manner is differential mode transmission, which has strong interference resistance and long transmission distance.
Further, the generation time of the periodic pulse reference signal is determined by the data sampling period of the master system and the slave system.
When the pulse reference signal of the previous cycle is sent out, the counter of the programmable logic device of the slave system is synchronously reset, the sampling period T1 is accumulated, the master system and the slave system start the acquisition of the next round of data, the sampling period T2 of the next round of data is integral multiple of T1, and meanwhile, the digital signal processor of the slave system starts the calculation of the data acquired in the previous round; when the next round of data acquisition of the master-slave system is completed, the programmable logic device of the master system generates a next period pulse reference signal and transmits the next period pulse reference signal to the slave system, and the data processing of the two systems is synchronous by the circulation.
Furthermore, the programmable logic device is an FPGA which has greater flexibility and higher integration level, and the FPGA is more suitable for finishing sequential logic and is more suitable for a structure with rich triggers.
Correspondingly, the integrated navigation system for performing clock synchronization processing by using the method comprises a master inertial navigation system and a slave inertial navigation system which are in communication connection with each other;
the main inertial navigation system comprises a main data acquisition unit, a main FPGA unit, a main DSP unit and a main data storage unit; the main data acquisition unit is used for acquiring acceleration main data and angular velocity main data of the carrier; the master FPGA unit is used for sending a navigation calculation result of the master data to the slave inertial navigation system, generating a periodic pulse reference signal after the master data and the slave data are acquired, and sending the periodic pulse reference signal to the slave inertial navigation system; the main data storage unit is used for storing the main data acquired by the main data acquisition unit and a main data navigation resolving result; the main DSP unit is used for navigation resolving of the main data acquired by the main data acquisition unit;
the slave inertial navigation system comprises a slave data acquisition unit, a slave FPGA unit, a slave data storage unit and a slave DSP unit; the slave data acquisition unit is used for acquiring acceleration slave data and angular velocity slave data of the carrier; the slave FPGA unit is used for synchronously resetting the counter and generating a sampling period when the rising edge of the periodic pulse reference signal is identified, and simultaneously sending a synchronous signal to the slave DSP unit; the slave data storage unit is used for storing the slave data acquired by the slave data acquisition unit and resolving the slave data through data navigation; and the slave DSP unit is used for performing navigation calculation on slave data according to the calculation result of the master inertial navigation system when receiving the synchronous signal.
Advantageous effects
Compared with the prior art, the dual-system clock synchronization processing method based on the periodic pulse reference provided by the invention has the advantages that the clock synchronization is not needed when the master system and the slave system carry out data acquisition on respective sensors, when the data acquisition is completed, and after the data acquired by the master system is resolved and a resolving result is sent to the slave system, the clocks of the master system and the slave system are synchronized through the periodic pulse reference signal generated by the master system, and meanwhile, the synchronous signal sent by the programmable logic device of the slave system enables the digital signal processor of the slave system to start navigation resolving processing on the data acquired by the slave system according to the resolving result of the master system, so that the synchronous processing of the effective data of the master system and the slave system is realized, and the problem of poor resolving effect of combined navigation (dual systems) caused by asynchronous effective data processing is solved.
The clock synchronization processing method takes the synchronization signal as an external interrupt input source of the slave system digital signal processor, and does not need to adopt a timer to generate periodic interrupt, thereby reducing the resource use, reducing the design cost and improving the reliability of the design.
The clock synchronization processing method is also suitable for synchronization processing of other data correlation algorithms of the master system and the slave system, and has strong expandability.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only one embodiment of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a block diagram of reference signal and data transmission of a dual system in an embodiment of the present invention;
FIG. 2 is a timing diagram of synchronization of a reference signal, a sampling period, and a synchronization signal in an embodiment of the present invention;
FIG. 3 is a comparison graph of inertial navigation directions when clocks are not synchronized according to an embodiment of the present invention;
FIG. 4 is a comparison graph of inertial navigation directions during clock synchronization according to an embodiment of the present invention.
Detailed Description
The technical solutions in the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a dual-system clock synchronization processing method based on a periodic pulse reference, which comprises the following steps:
1. the master system and the slave system respectively complete the acquisition of data of a plurality of sensors, the data acquired by the master system is resolved and then the resolved result is sent to the slave system, so that a digital signal processor of the slave system subsequently performs resolving processing on the data acquired by the slave system according to the resolved result of the master system, as shown in fig. 1, the resolved result of the master system plays a role in assisting or correcting navigation resolving of the slave system.
2. The FPGA of the master system generates a periodic pulse reference signal based on the internal clock of the master system and transmits the periodic pulse reference signal to the slave system via RS422 communication, and the FPGA of the slave system recognizes the rising edge of the periodic pulse reference signal, as shown in fig. 1 and 2. Data acquisition and master system resolving results are firstly sent to the slave system, and then periodic pulse reference signals are generated, so that clocks of the master system and the slave system are synchronized, and transmission integrity of the master system resolving results sent to the slave system is guaranteed.
3. The FPGA of the slave system synchronously resets the counter and generates a sampling period T1 with reference to the internal clock of the slave system, and simultaneously, the FPGA of the slave system sends a synchronization signal to the digital signal processor of the slave system, and the digital signal processor of the slave system performs navigation solution processing on data acquired from the slave system according to the solution result of the master system, as shown in fig. 2.
The generation time of the periodic pulse reference signal is determined by the data sampling period T2 of the previous round of the master system and the slave system and the data resolving time of the previous round of the slave system. When a pulse reference signal of the previous period is sent out, a counter of a slave system FPGA is synchronously reset, sampling periods T1 are accumulated, a master system and a slave system start to collect data of the next round, the sampling period T2 of the data of the next round is integral multiple of T1, and meanwhile, a digital signal processor of the slave system starts to calculate the collected data of the previous round (a synchronous signal is used as an external interrupt input source of the digital signal processor, interrupts to receive the data sent by a master system, and utilizes respective effective data after clocks of the master system and the slave system are synchronized to complete combined navigation calculation); when the next round of data acquisition of the master-slave system is completed, the FPGA of the master system generates a next period pulse reference signal and transmits the next period pulse reference signal to the slave system in an RS422 communication mode, and all data processing of the double systems are synchronized by means of circulation.
And (3) carrying out simulation analysis comparison on time synchronization or asynchronism: as shown in fig. 3, under the condition of asynchronous clocks, the inertial navigation azimuth angles at each time within 40s are calculated by the master inertial navigation and the slave inertial navigation according to respective sampling data, and it can be known from the local enlarged display in fig. 3 that the calculation results of the master inertial navigation and the slave inertial navigation for the azimuth angles have obvious deviation (the calculation result of the master inertial navigation does not play a role in assistance or correction), and especially under maneuvering conditions such as traveling and turning, the deviation can be further increased, and the alignment accuracy of navigation calculation is finally affected; as shown in fig. 4, under the condition of clock synchronization, the inertial navigation azimuth angle at each moment in 40s is calculated for respective sampling data by the master inertial navigation and the slave inertial navigation, and according to the local enlarged display in fig. 4, the calculation results of the azimuth angles by the master inertial navigation and the slave inertial navigation are basically overlapped; therefore, the time consistency of the data resolved by the master inertial navigation and the slave inertial navigation is ensured through the clock synchronization design, the effective estimation of the azimuth angle, the pitch angle and the roll angle of the slave inertial navigation can be further carried out, particularly, the increase of errors can be inhibited under maneuvering conditions such as turning, and the alignment precision after navigation resolution is ensured.
According to the dual-system clock synchronization processing method, the clock synchronization is not needed when the respective sensors of the master system and the slave system acquire data, when the data acquisition is completed, and after the data acquired by the master system is resolved and the resolving result is completely sent to the slave system, the clocks of the master system and the slave system are synchronized through the periodic pulse reference signal generated by the master system, and meanwhile, the synchronizing signal sent by the FPGA of the slave system enables the digital signal processor of the slave system to perform combined navigation resolving processing on the data acquired by the slave system according to the resolving result of the master system, and the navigation resolving of the data acquired by the slave system is assisted or corrected through the resolving result of the master system, so that the synchronous processing of the effective data of the master system and the slave system is realized, and the problem of poor resolving effect of combined navigation (dual systems) caused by the asynchronous processing of the effective data is avoided; the clock synchronization processing method takes the synchronization signal as an external interrupt input source of the slave system digital signal processor, and does not need to adopt a timer to generate periodic interrupt, thereby reducing the resource use, reducing the design cost and improving the reliability of the design.
As shown in fig. 1, a combined navigation system for performing clock synchronization processing by using the method includes a master inertial navigation system and a slave inertial navigation system that are communicatively connected to each other;
the main inertial navigation system comprises a main data acquisition unit, a main FPGA unit, a main DSP unit and a main data storage unit; the main data acquisition unit is used for acquiring the acceleration main data and the angular velocity main data of the carrier; the master FPGA unit is used for sending a navigation resolving result of the master data to the slave inertial navigation system, generating a periodic pulse reference signal after the master data and the slave data are acquired, and sending the periodic pulse reference signal to the slave inertial navigation system; the main data storage unit is used for storing the main data acquired by the main data acquisition unit and a main data navigation resolving result; the main DSP unit is used for performing navigation calculation on the main data acquired by the main data acquisition unit (the calculation result of the main inertial navigation system is the attitude results such as course angle, pitch angle, rolling angle and the like);
the slave inertial navigation system comprises a slave data acquisition unit, a slave FPGA unit, a slave data storage unit and a slave DSP unit; the slave data acquisition unit is used for acquiring acceleration slave data and angular velocity slave data of the carrier; the slave FPGA unit is used for synchronously resetting the counter and generating a sampling period when the rising edge of the periodic pulse reference signal is identified, and simultaneously sending a synchronous signal to the slave DSP unit; the slave data storage unit is used for storing the slave data acquired by the slave data acquisition unit and resolving the slave data through data navigation; and the slave DSP unit is used for performing navigation calculation on slave data according to the calculation result of the master inertial navigation system when receiving the synchronous signal (the slave inertial navigation system calculates attitude results such as a course angle, a pitch angle, a roll angle, a longitude, a latitude, an altitude, an east speed, a north speed, a sky speed and the like under the assistance or correction of the calculation result of the master inertial navigation system).
The above disclosure is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of changes or modifications within the technical scope of the present invention, and shall be covered by the scope of the present invention.
Claims (5)
1. A dual-system clock synchronization processing method based on periodic pulse reference is characterized by comprising the following steps:
step 1: the master system and the slave system respectively complete the acquisition of the data of the respective sensors, and the data acquired by the master system is resolved and then the resolved result is sent to the slave system;
step 2: the programmable logic device of the master system generates a periodic pulse reference signal by taking an internal clock of the programmable logic device as a reference, and transmits the periodic pulse reference signal to the slave system, and the programmable logic device of the slave system recognizes the rising edge of the periodic pulse reference signal;
and step 3: the programmable logic device of the slave system synchronously resets the counter by taking an internal clock thereof as a reference and generates a sampling period, meanwhile, the programmable logic device of the slave system sends a synchronous signal to the digital signal processor of the slave system, and the digital signal processor of the slave system carries out navigation calculation processing on data acquired by the slave system according to a calculation result of the master system.
2. The dual system clock synchronization processing method of claim 1, wherein in the step 2, the periodic pulse reference signal is transmitted to the slave system in RS422 communication.
3. The dual system clock synchronization processing method of claim 1, wherein the generation time of the periodic pulse reference signal is determined by a data sampling period of the master system and the slave system.
4. The dual system clock synchronization processing method of claim 1, wherein the programmable logic device is an FPGA.
5. An integrated navigation system for clock synchronization processing by using the method of any one of claims 1 to 4, comprising a master inertial navigation system and a slave inertial navigation system which are communicatively connected to each other;
the main inertial navigation system comprises a main data acquisition unit, a main FPGA unit, a main DSP unit and a main data storage unit; the main data acquisition unit is used for acquiring acceleration main data and angular velocity main data of the carrier; the master FPGA unit is used for sending a navigation calculation result of the master data to the slave inertial navigation system, generating a periodic pulse reference signal after the master data and the slave data are acquired, and sending the periodic pulse reference signal to the slave inertial navigation system; the main data storage unit is used for storing the main data acquired by the main data acquisition unit and a main data navigation resolving result; the main DSP unit is used for navigation resolving the main data acquired by the main data acquisition unit;
the slave inertial navigation system comprises a slave data acquisition unit, a slave FPGA unit, a slave data storage unit and a slave DSP unit; the slave data acquisition unit is used for acquiring acceleration slave data and angular velocity slave data of the carrier; the slave FPGA unit is used for synchronously resetting the counter and generating a sampling period when the rising edge of the periodic pulse reference signal is identified, and simultaneously sending a synchronous signal to the slave DSP unit; the slave data storage unit is used for storing the slave data acquired by the slave data acquisition unit and resolving the slave data by navigation; and the slave DSP unit is used for carrying out navigation calculation on slave data according to the calculation result of the master inertial navigation system when receiving the synchronous signal.
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