CN110544722A - gate-controlled bipolar-field effect composite gallium nitride transverse double-diffusion metal oxide semiconductor transistor - Google Patents
gate-controlled bipolar-field effect composite gallium nitride transverse double-diffusion metal oxide semiconductor transistor Download PDFInfo
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- CN110544722A CN110544722A CN201910749636.9A CN201910749636A CN110544722A CN 110544722 A CN110544722 A CN 110544722A CN 201910749636 A CN201910749636 A CN 201910749636A CN 110544722 A CN110544722 A CN 110544722A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 37
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000002131 composite material Substances 0.000 title claims abstract description 18
- 230000000694 effects Effects 0.000 title claims abstract description 18
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 15
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 15
- 238000009792 diffusion process Methods 0.000 title abstract description 7
- 230000003071 parasitic effect Effects 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 5
- 239000002210 silicon-based material Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 239000011777 magnesium Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 230000005611 electricity Effects 0.000 abstract description 2
- 239000002585 base Substances 0.000 description 53
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
the invention discloses a grid-controlled bipolar-field effect composite gallium nitride transverse double-diffusion metal oxide semiconductor transistor. The device replaces the traditional electrode connection mode of short circuit between the base region and the source electrode in the gallium nitride LDMOS by adopting the electrode connection mode of connecting the base region and the grid electrode. When the device works in an off state, the voltage-resistant characteristic of the device is consistent with that of the traditional gallium nitride LDMOS, the grid electrode, the base region and the source electrode of the device are grounded, and the drain electrode is connected with a high potential; when the bipolar transistor works in an on state, the parasitic bipolar transistor is turned on, a new conductive channel is provided, and the channel can be also normally turned on to conduct electricity. The structure adopts an electrode connection mode that the grid electrode is connected with the base region, and compared with the traditional gallium nitride LDMOS device, the structure ensures that the device has the same breakdown voltage, greatly improves the conduction current of the device and greatly improves the conduction performance of a gallium nitride transistor.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a transverse double-diffusion transistor.
background
Compared with the traditional narrow-bandgap semiconductor, the wide-bandgap gallium nitride has more excellent physical properties, such as high forbidden bandwidth, high breakdown electric field, high electron mobility, acid and alkali resistance and the like, is suitable for preparing power electronic devices working under the conditions of high temperature, high pressure, high frequency and the like, and has wide prospects in the aspects of military affairs, civil engineering and the like. The growth of gallium nitride material has already had a relatively mature solution, and the advantage of HVPE can be utilized to prepare a high-quality thick-film gallium nitride epitaxial layer. Therefore, power electronic devices made of gallium nitride materials have become a popular research field in the semiconductor field.
LDMOS is a very important structure in the development of power MOS field effect transistors and is widely used because it is more compatible with CMOS processes. In order to realize high voltage and large current, the LDMOS layout area is large, the chip cost is high, and the compromise between the on-resistance and the breakdown voltage is the main defect.
the traditional LDMOS does not pay enough attention to a parasitic bipolar transistor, and adopts a short-circuit electrode connection mode between a base region and a source region. In an open state, the parasitic bipolar transistor cannot be opened because the base region is in short circuit with the source region, and the device can only conduct electricity in a normally opened channel.
Disclosure of Invention
the invention provides a grid-controlled bipolar-field effect composite gallium nitride transverse double-diffusion metal oxide semiconductor transistor, aiming at further effectively increasing the on-current of a device (reducing the on-resistance of the device) on the premise of meeting the voltage withstanding requirement.
the technical scheme of the invention is as follows:
A gated bipolar-field effect composite gallium nitride lateral double diffused metal oxide semiconductor transistor comprising:
A substrate of silicon material;
Generating an epitaxial layer of gallium nitride material on the substrate;
A base region and a drift region formed on the epitaxial layer;
a source region and a corresponding channel are formed in the middle area of the upper part of the base region;
A drain region formed on one end of the drift region far away from the base region;
A gate insulating layer covering the channel and a part of the drift region adjacent to the channel (while a part close to the drain region mainly serves as a passivation layer);
The grid electrode is positioned on the surface of the grid insulation layer above the channel;
the base electrode is positioned on the surface of the base region far away from one end of the channel;
the source electrode is positioned on the surface of the source region;
the drain electrode is positioned on the surface of the drain region;
the base electrode is isolated from the source electrode and is electrically connected with the grid electrode, and the requirements of: when the grid is connected with voltage, the voltage obtained by the base region enables the parasitic bipolar transistor of the device to be started.
The connecting material between the base and the gate can be a conductor material, so that the base and the gate are in the same potential when the gate is connected with voltage. The conductor material is preferably copper or aluminum.
the connecting material between the base electrode and the grid electrode can also be a semiconductor material, so that the potential of the base electrode is greater than the potential of the grid electrode when the base electrode is connected with voltage, and the potential of the grid electrode is greater than the potential of the base electrode when the grid electrode is connected with voltage. The semiconductor material is preferably semi-insulating polysilicon.
The silicon substrate is preferably an undoped single crystal silicon material.
The parameters of each region of the device are optimized as follows:
the length of the base region is 4-6 microns, the thickness of the base region is 1-3 microns, and the magnesium doping concentration of the base region is 1 x 1018 cm-3-2 x 1018 cm-3; the length of the source region is 1-2 mu m, and the silicon doping concentration of the source region is 1 x 1018 cm-3-2 x 1018 cm-3; the length of the drain region is 1-2 mu m, and the silicon doping concentration of the drain region is 1 x 1018 cm-3-2 x 1018 cm-3; the length of the drift region is 10-90 μm, the thickness of the drift region is 1-3 μm, and the silicon doping concentration of the drift region is 1 × 1016 cm-3-2 × 1016 cm-3.
The thickness of the GaN epitaxial layer is 10-50 μm.
The source region and the source electrode are in ohmic contact, the drain region and the drain electrode are in Schottky contact, and the base electrode and the base region are in ohmic contact.
the technical scheme of the invention has the following beneficial effects:
according to the grid-controlled bipolar-field effect composite gallium nitride transverse double-diffusion metal oxide semiconductor transistor, a gallium nitride material is applied, and a traditional electrode connection mode of short circuit between a base region and a source region is changed into an electrode connection mode of connecting a base region electrode and a grid electrode. When the device works in an off state, the breakdown characteristic of the device is consistent with that of a gallium nitride device. The grid electrode, the base region and the source electrode of the device are grounded, and the drain electrode is connected with a high potential, so that a parasitic bipolar transistor does not work among the source region, the base region and the drift region when the device works in an off state, secondary breakdown is prevented, and the breakdown characteristic of the device is the same as that of the traditional device. When the bipolar transistor works in an on state, the grid electrode is connected with the base region electrode, and when the grid electrode is connected with grid voltage, the base region is also connected with certain voltage, so that the parasitic bipolar transistor of the device is started, and a new conductive channel is provided; at the same time, the channel of the device can also be normally turned on for conduction.
Compared with the traditional gallium nitride LDMOS device, the invention ensures that the device has the same breakdown voltage, greatly improves the conduction current of the device and greatly improves the conduction performance of the gallium nitride transistor.
drawings
fig. 1 is a schematic structural diagram of a gated bipolar-field effect composite gan ldmos transistor according to the present invention.
fig. 2 illustrates a conductive path based on the structure shown in fig. 1. Wherein, A is a conductive channel formed by a channel, and B is a conductive channel formed by starting a parasitic bipolar transistor.
The reference numbers illustrate:
1-a silicon substrate; 2-an epitaxial layer of gallium nitride; 3-base region; a 4-source region; 5-a drain region; 6-a drift region; a 7-source electrode; 8-a grid; 9-a drain electrode; a 10-base.
Detailed Description
as shown in fig. 1, the gated bipolar-field effect composite gan ldmos transistor of the present embodiment includes:
the silicon substrate 1 adopts undoped monocrystalline silicon material, so that large-size gallium nitride can grow on the silicon substrate conveniently;
Growing a gallium nitride epitaxial layer 2 on a silicon substrate 1, wherein the thickness of the gallium nitride epitaxial layer is 10-50 mu m;
forming a P-type base region 3 and a drift region 6 on the gallium nitride epitaxial layer 2, and forming an active region on the surface of the device;
Forming a gate insulating layer on the active region, and forming a gate electrode 8 over the gate insulating layer;
Forming a source region 4 on the base region and simultaneously forming a channel;
forming a drain region 5 on the drift region;
The length of the base region is 4-6 microns, the thickness of the base region is 1-3 microns, and the magnesium doping concentration of the base region is 1 x 1018 cm-3-2 x 1018 cm-3; the length of the source region is 1-2 mu m, and the silicon doping concentration of the source region is 1 x 1018 cm-3-2 x 1018 cm-3; the length of the drain region is 1-2 mu m, and the silicon doping concentration of the drain region is 1 x 1018 cm-3-2 x 1018 cm-3; the length of the drift region is 10-90 mu m, the thickness of the drift region is 1-3 mu m, and the silicon doping concentration of the drift region is 1 x 1016 cm-3-2 x 1016 cm-3;
Respectively generating a base electrode 10, a source electrode 7 and a drain electrode 9 on the base region 3, the source region 4 and the drain region 5; the source region and the source electrode are in ohmic contact, the drain region and the drain electrode are in Schottky contact, and the base electrode and the base region are in ohmic contact.
the base 10 of the device is connected to the gate 8. Specifically, the method comprises the following steps:
the connecting material between the base region 2 and the grid 8 can be a conductor material (such as copper and aluminum), and when the grid 8 is connected with a voltage, the base region and the grid 8 are in consistent potential.
The connecting material between the base region 2 and the gate 8 may be a resistive material (e.g., semi-insulating polysilicon, etc.). When the base region 2 is connected with voltage, the potential of the base region 2 is greater than that of the grid 8; when the grid 8 is connected with voltage, the potential of the grid 8 is larger than that of the base region 2.
It should be noted that the grid electrode and the base electrode common connection leading-out terminal shown in the drawing is a topological schematic, and in an actual product, the base electrode and the grid electrode are connected and then led out, and the base electrode and the grid electrode can be directly led out from the base electrode or directly led out from the grid electrode. There is a difference in the potential of the gate electrode and the base electrode due to the difference in the resistance between the base electrode and the gate electrode and the position of the extraction electrode.
when the gate-controlled bipolar-field effect composite gallium nitride transverse double-diffusion metal oxide semiconductor transistor works in an off state, the breakdown characteristic of the device is consistent with that of a gallium nitride device. The grid electrode, the base region and the source electrode of the device are grounded, and the drain electrode is connected with a high potential, so that a parasitic bipolar transistor does not work among the source region, the base region and the drift region when the device works in an off state, secondary breakdown is prevented, and the breakdown characteristic of the device is the same as that of the traditional device. When the grid electrode is in an on state, the grid electrode is connected with the base region electrode, and when the grid electrode is connected with grid voltage, the base region is also connected with certain voltage. A new conductive channel B is added by starting a parasitic bipolar transistor among the source region, the base region and the drift region. At the same time, the channel of the device can also be normally turned on for conduction. The on-state current of the device is greatly increased, and the on-state resistance of the device is greatly reduced.
Compared with the gallium nitride device, the conduction current density of the invention is greatly improved, and the conduction current density of the two devices is improved by one to three orders of magnitude under the condition that the drift regions of the two devices are the same and the breakdown voltage of the two devices is the same.
Of course, the LDMOS of the present invention may also be a P-channel LDMOS, and the structure thereof is the same as that of an N-channel LDMOS, which is not described herein again.
the above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions also fall into the protection scope of the present invention.
Claims (9)
1. A gated bipolar-field effect composite gan ldmos transistor comprising:
A substrate of silicon material;
generating an epitaxial layer of gallium nitride material on the substrate;
A base region and a drift region formed on the epitaxial layer;
A source region and a corresponding channel are formed in the middle area of the upper part of the base region;
a drain region formed on one end of the drift region far away from the base region;
The gate insulating layer covers the channel and the part of the drift region adjacent to the channel;
The grid electrode is positioned on the surface of the grid insulation layer above the channel;
The base electrode is positioned on the surface of the base region far away from one end of the channel;
The source electrode is positioned on the surface of the source region;
The drain electrode is positioned on the surface of the drain region;
The base electrode is isolated from the source electrode and is electrically connected with the grid electrode, and the requirements of: when the grid is connected with voltage, the voltage obtained by the base region enables the parasitic bipolar transistor of the device to be started.
2. the gated bipolar-field effect composite gallium nitride lateral double diffused metal oxide semiconductor transistor of claim 1, wherein: the connecting material between the base electrode and the grid electrode is a conductor material, so that the base electrode and the grid electrode are consistent in potential when the grid electrode is connected with voltage.
3. the gated bipolar-field effect composite gallium nitride lateral double diffused metal oxide semiconductor transistor of claim 2, wherein: the conductor material is copper or aluminum.
4. the gated bipolar-field effect composite gallium nitride lateral double diffused metal oxide semiconductor transistor of claim 1, wherein: the connecting material between the base electrode and the grid electrode is a semiconductor material, so that the potential of the base electrode is greater than the potential of the grid electrode when the base electrode is connected with voltage, and the potential of the grid electrode is greater than the potential of the base electrode when the grid electrode is connected with voltage.
5. the gated bipolar-field effect composite gallium nitride lateral double diffused metal oxide semiconductor transistor of claim 4, wherein: the semiconductor material is semi-insulating polysilicon.
6. The gated bipolar-field effect composite gallium nitride lateral double diffused metal oxide semiconductor transistor of claim 1, wherein: the silicon substrate is an undoped monocrystalline silicon material.
7. The gated bipolar-field effect composite gallium nitride lateral double diffused metal oxide semiconductor transistor of claim 1, wherein: the length of the base region is 4-6 microns, the thickness of the base region is 1-3 microns, and the magnesium doping concentration of the base region is 1 x 1018 cm-3-2 x 1018 cm-3; the length of the source region is 1-2 mu m, and the silicon doping concentration of the source region is 1 x 1018 cm-3-2 x 1018 cm-3; the length of the drain region is 1-2 mu m, and the silicon doping concentration of the drain region is 1 x 1018 cm-3-2 x 1018 cm-3; the length of the drift region is 10-90 μm, the thickness of the drift region is 1-3 μm, and the silicon doping concentration of the drift region is 1 × 1016 cm-3-2 × 1016 cm-3.
8. The gated bipolar-field effect composite gallium nitride lateral double diffused metal oxide semiconductor transistor of claim 1, wherein: the source region and the source electrode are in ohmic contact, the drain region and the drain electrode are in Schottky contact, and the base electrode and the base region are in ohmic contact.
9. The gated bipolar-field effect composite gallium nitride lateral double diffused metal oxide semiconductor transistor of claim 1, wherein: the thickness of the epitaxial layer is 10-50 mu m.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910749636.9A CN110544722A (en) | 2019-08-14 | 2019-08-14 | gate-controlled bipolar-field effect composite gallium nitride transverse double-diffusion metal oxide semiconductor transistor |
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| CN201910749636.9A CN110544722A (en) | 2019-08-14 | 2019-08-14 | gate-controlled bipolar-field effect composite gallium nitride transverse double-diffusion metal oxide semiconductor transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755524A (en) * | 2020-07-20 | 2020-10-09 | 西安电子科技大学 | Schottky accumulation layer silicon carbide transverse field effect transistor and manufacturing method thereof |
| CN115084232A (en) * | 2022-07-21 | 2022-09-20 | 北京芯可鉴科技有限公司 | Heterojunction transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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| US6303947B1 (en) * | 1999-01-20 | 2001-10-16 | Fuji Electric Co., Ltd. | Silicon carbide vertical FET and method for manufacturing the same |
| US20030001206A1 (en) * | 2001-06-27 | 2003-01-02 | Takaaki Negoro | Semiconductor device and method for fabricating such device |
| US20090267146A1 (en) * | 2008-04-24 | 2009-10-29 | James Pan | Structure and method for semiconductor power devices |
| US20140027849A1 (en) * | 2012-07-30 | 2014-01-30 | Freescale Semiconductor, Inc. | Ldmos device and method for improved soa |
| CN108172618A (en) * | 2017-12-26 | 2018-06-15 | 西安电子科技大学 | High K dielectric channel lateral bilateral diffusion metal oxide wide band gap semiconducter field-effect tube and preparation method thereof |
-
2019
- 2019-08-14 CN CN201910749636.9A patent/CN110544722A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6303947B1 (en) * | 1999-01-20 | 2001-10-16 | Fuji Electric Co., Ltd. | Silicon carbide vertical FET and method for manufacturing the same |
| US20030001206A1 (en) * | 2001-06-27 | 2003-01-02 | Takaaki Negoro | Semiconductor device and method for fabricating such device |
| US20090267146A1 (en) * | 2008-04-24 | 2009-10-29 | James Pan | Structure and method for semiconductor power devices |
| US20140027849A1 (en) * | 2012-07-30 | 2014-01-30 | Freescale Semiconductor, Inc. | Ldmos device and method for improved soa |
| CN108172618A (en) * | 2017-12-26 | 2018-06-15 | 西安电子科技大学 | High K dielectric channel lateral bilateral diffusion metal oxide wide band gap semiconducter field-effect tube and preparation method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755524A (en) * | 2020-07-20 | 2020-10-09 | 西安电子科技大学 | Schottky accumulation layer silicon carbide transverse field effect transistor and manufacturing method thereof |
| CN111755524B (en) * | 2020-07-20 | 2022-06-07 | 西安电子科技大学 | Schottky accumulation layer silicon carbide transverse field effect transistor and manufacturing method thereof |
| CN115084232A (en) * | 2022-07-21 | 2022-09-20 | 北京芯可鉴科技有限公司 | Heterojunction transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN115084232B (en) * | 2022-07-21 | 2023-01-17 | 北京芯可鉴科技有限公司 | Heterojunction transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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