CN110518010B - PMOS device with embedded silicon controlled rectifier and implementation method thereof - Google Patents
PMOS device with embedded silicon controlled rectifier and implementation method thereof Download PDFInfo
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- CN110518010B CN110518010B CN201910808797.0A CN201910808797A CN110518010B CN 110518010 B CN110518010 B CN 110518010B CN 201910808797 A CN201910808797 A CN 201910808797A CN 110518010 B CN110518010 B CN 110518010B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 19
- 239000010703 silicon Substances 0.000 title claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 26
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000000694 effects Effects 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 description 22
- 230000015556 catabolic process Effects 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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Abstract
The invention discloses a PMOS device with an embedded silicon controlled rectifier and an implementation method thereof, wherein the high-concentration N-type doping of the connecting cathode of the PMOS device with the embedded silicon controlled rectifier is replaced by low-concentration N-type light doping (30), metal silicide is formed on the upper surface of the low-concentration N-type light doping (30), a leading-out electrode is used as the cathode of the PMOS device, and the P-type ESD doping below the high-concentration P-type doping (20) and the high-concentration P-type doping (26) is removed at the same time.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit technology, and in particular, to a PMOS device with an embedded scr for Electro-Static Discharge (ESD) and a method for implementing the same.
Background
In the field of esd protection design for integrated circuits, the esd protection design window generally depends on the operating voltage and the thickness of the gate oxide layer of the internal protected circuit. Taking a conventional 28nm high-K/Metal Gate process platform in the industry as an example, the thickness of a Gate oxide layer of an IO device is about 40A, and the operating voltage is 1.8V, so the anti-static protection design window of the 28nm high-K/Metal Gate process platform is usually between 2.2V and 8V.
A PMOS device with a built-in silicon controlled rectifier is provided in 2015 because the second breakdown current It2 of the hysteresis effect of the PMOS device is lower due to the fact that the mobility ratio of a carrier hole in the PMOS device is lower, and in order to improve the second breakdown current of the PMOS in a 28nm High-K/Metal Gate process platform, as shown in FIG. 1, a High-concentration N-type doping (N +)30 is inserted into a drain of the PMOS device, P-type ESD doping (P-ESD IMP) 10-12 is added below a source drain, then the High-concentration N-type doping (N +)30 is connected with a cathode, and at the moment, a parasitic PNPN (High-concentration P-type doping (P +)20/N Well (N-Well) 60/P-type ESD IMP) 10/High-concentration N-type doping (N +)30 or High-concentration P-type doping (P +)26/N Well (N-Well) 60/P-type ESD (P-ESD IMP) 60/P-ESD) ESD IMP) 10/high-concentration N-type doped (N +)30) silicon controlled rectifier, the secondary breakdown current of the PMOS of the embedded silicon controlled rectifier is greatly improved, as shown in the following Table 1:
TABLE 1
Table 1 shows a hysteresis effect parameter comparison table of the PMOS of the existing embedded scr and the conventional GGNMOS and GDPMOS under the 28nm High-K/Metal Gate process, which can find that the existing embedded scr PMOS can greatly increase the secondary breakdown current of the conventional PMOS, even exceed the secondary breakdown current of the conventional GGNMOS, but the retention voltage is only about 1.7V, which is less than the working voltage 1.8V, and the latch-up effect is easily triggered when the external disturbance occurs, so that it is seen that the existing embedded scr PMOS is not suitable for the anti-static protection design, so that the existing embedded scr PMOS device needs to be further improved to increase the retention voltage Vh, so that the existing embedded scr PMOS device is suitable for the anti-static protection design.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a PMOS device with an embedded scr and an implementation method thereof, so as to increase the secondary breakdown current of the PMOS device and simultaneously increase the holding voltage of the PMOS device to be higher than the working voltage of the PMOS device, and thus the PMOS device is suitable for the anti-static protection design.
To achieve the above and other objects, the present invention provides a PMOS device with embedded scr, the PMOS device comprising:
a semiconductor substrate (80);
an N-well (60) created in the semiconductor substrate (80);
high-concentration N-type doping (32) and high-concentration P-type doping (20) are arranged on the left side of the N well (60), high-concentration P-type doping (22), low-concentration N-type light doping (30) and high-concentration P-type doping (24) are arranged in the middle of the N well (60), high-concentration N-type doping (34) and high-concentration P-type doping (26) are arranged on the right side of the N well (60), and a layer of P-type ESD doping (10) is arranged below the bottom of the high-concentration P-type doping (22), the bottom of the low-concentration N-type light doping (30), the bottom of the high-concentration P-type doping (24) and a middle interval part of the high-concentration P-type doping (24;
a first P-type gate (40) is arranged above the space between the high-concentration P-type doping (20) and the high-concentration P-type doping (22), and a second P-type gate (42) is arranged above the space between the high-concentration N-type doping (24) and the high-concentration P-type doping (26);
and metal silicide is generated above the high-concentration N-type doping (32) and above the high-concentration P-type doping (20) and is connected with the first P-type gate (40) to form an anode of the PMOS device, a metal silicide leading-out electrode is generated above the low-concentration N-type light doping (30) and is used as a cathode of the PMOS device, and metal silicide is generated above the high-concentration N-type doping (34) and above the high-concentration P-type doping (26) and is connected with the second P-type gate (42) to form an anode of the PMOS device.
Preferably, the high concentration P-type doping (20), the N-well (60), and the P-type ESD doping (10) constitute an equivalent PNP triode structure.
Preferably, the N well (60), the P type ESD doping (10) and the low concentration N type light doping (30) form an equivalent NPN triode structure.
Preferably, the high concentration P-type doping (26), the N-well (60), and the P-type ESD doping (10) form an equivalent PNP triode structure.
Preferably, the high-concentration N-type doping (32) and the high-concentration P-type doping (20) are isolated by a shallow trench isolation layer, and a part of the N well (60) is arranged between the right side of the high-concentration P-type doping (20) and the high-concentration P-type doping (22).
Preferably, a part of the N well (60) is arranged between the high-concentration N-type doping (24) and the high-concentration P-type doping (26), and the high-concentration P-type doping (26) and the high-concentration N-type doping (34) are isolated by a shallow trench isolation layer.
Preferably, hysteresis effect characteristic of the PMOS device is determined by width A of the high-concentration P-type doping (22) and the high-concentration P-type doping (24), width B of the low-concentration N-type light doping (30), interval between the high-concentration P-type doping (22) and the low-concentration N-type light doping (30), interval S between the low-concentration N-type light doping (30) and the high-concentration P-type doping (24), and doping concentration of the low-concentration N-type light doping (30), wherein A is 0.1-1 um, B is 0.1-2 um, S is 0-2 um, and the range of doping concentration is 1E 12-1E 15/cm2。
In order to achieve the purpose, the invention also provides a method for realizing the PMOS device with the embedded silicon controlled rectifier, the method connects the PMOS device with the existing embedded silicon controlled rectifier with high-concentration N-type doping of a cathode to replace low-concentration N-type light doping (30), forms metal silicide on the upper surface of the low-concentration N-type light doping (30), leads an electrode to be used as the cathode of the PMOS device, and removes P-type ESD doping below the high-concentration P-type doping (20) and the high-concentration P-type doping (26).
Preferably, the method comprises the steps of:
step S1, providing a semiconductor substrate (80), and generating an N well (60) in the semiconductor substrate (80);
step S2, high-concentration N-type doping (32) and high-concentration P-type doping (20) are arranged on the left side of the N well (60), high-concentration P-type doping (22), low-concentration N-type light doping (30) and high-concentration P-type doping (24) are arranged in the middle of the N well (60), high-concentration N-type doping (34) and high-concentration P-type doping (26) are arranged on the right side of the N well (60), a layer of P-type ESD doping (10) is arranged below the bottom of the high-concentration P-type doping (22), the bottom of the low-concentration N-type light doping (30), the bottom of the high-concentration P-type doping (24) and the middle spacing part of the high-concentration P-type doping (24), a first P-type grid (40) is arranged above the space between the high-concentration P-type doping (20) and the high-concentration P-type doping (22), a second P-type gate (42) is arranged above the space between the high-concentration N-type doping (24) and the high-concentration P-type doping (26);
and step S3, generating metal silicide above the high-concentration N-type doping (32) and above the high-concentration P-type doping (20) and connecting the metal silicide with the first P-type gate (40) to form an anode of the PMOS device, generating a metal silicide leading-out electrode above the low-concentration N-type light doping (30) to serve as a cathode of the PMOS device, and generating metal silicide above the high-concentration N-type doping (34) and above the high-concentration P-type doping (26) and connecting the metal silicide with the second P-type gate (42) to form an anode of the PMOS device.
Preferably, hysteresis effect characteristic of the PMOS device is determined by width A of the high-concentration P-type doping (22) and the high-concentration P-type doping (24), width B of the low-concentration N-type light doping (30), interval between the high-concentration P-type doping (22) and the low-concentration N-type light doping (30), interval S between the low-concentration N-type light doping (30) and the high-concentration P-type doping (24), and doping concentration of the low-concentration N-type light doping (30), wherein A is 0.1-1 um, B is 0.1-2 um, S is 0-2 um, and the range of doping concentration is 1E 12-1E 15/cm2。
Compared with the prior art, the PMOS device with the embedded silicon controlled rectifier and the implementation method thereof have the advantages that the high-concentration N-type doping connected with the cathode in the existing PMOS device with the embedded silicon controlled rectifier is replaced by the light-doped N-type light doping (NLDD), the P-ESD IMP doping below the high-concentration P-type doping connected with the anode is removed, the secondary breakdown current of the PMOS device can be increased, meanwhile, the maintaining voltage is increased to be higher than the working voltage of the PMOS device, and the PMOS device is suitable for anti-static protection design.
Drawings
FIG. 1 is a schematic diagram of a prior art SCR embedded PMOS device;
FIG. 2 is a diagram of a device structure of a preferred embodiment of a PMOS device with embedded SCR according to the present invention;
FIG. 3 is a flowchart illustrating a method for implementing a PMOS device with embedded SCR according to a preferred embodiment of the present invention;
fig. 4 is a schematic view of an application scenario of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
FIG. 2 is a diagram of a preferred embodiment of a SCR embedded PMOS device according to the present invention. As shown in fig. 2, a PMOS device with embedded scr of the present invention includes: a plurality of Shallow Trench Isolation (STI) layers 70, a high concentration N-type dopant (N +)32, a high concentration P-type dopant (P +)20, a high concentration P-type dopant (P +)22, a low concentration N-type light dopant (NLDD)30, a high concentration P-type dopant (P +)24, a P-type ESD dopant (P-ESD IMP)10, a high concentration P-type dopant (P +)26, a high concentration N-type dopant (N +)34, an N-Well (N-Well)60, a P-type substrate (P-Sub)80, a first P-type Gate (P-Gate)40, a second P-type Gate (P-Gate)42, and a plurality of metal silicides (Silicide)50 connecting the doped regions and the electrodes.
The whole ESD device is arranged on a P-type substrate (P-Sub)80, an N-Well (N-Well)60 is generated in the P-type substrate (P-Sub)80, high-concentration N-type doping (N +)32 and high-concentration P-type doping (P +)20 are arranged at the upper left part of the N-Well (N-Well)60, high-concentration P-type doping (P +)20, the N-Well (N-Well)60 and P-type ESD doping (P-ESD IMP)10 form an equivalent PNP triode structure, high-concentration P-type doping (P +)22, low-concentration N-type light doping (NLDD)30 and high-concentration P-type doping (P +)24 are arranged at the upper middle part of the N-Well (N-Well)60, the P-type ESD doping (P-ESD IMP)10 and the low-concentration N-type light doping (NLDD)30 form an equivalent NPN triode structure, and high-concentration N-type doping (N34 +)34, The high-concentration P-type doping (P +)26 is arranged at the upper right part of the N-Well (N-Well)60, and the high-concentration P-type doping (P +)26, the N-Well (N-Well)60 and the P-type ESD doping (P-ESD IMP)10 form an equivalent PNP triode structure;
the high-concentration N-type doping (N +)32 and the high-concentration P-type doping (P +)20 are isolated by a Shallow Trench Isolation (STI) 70, a part of an N-Well (N-Well)60 is arranged between the right side of the high-concentration P-type doping (P +)20 and the high-concentration P-type doping (P +)22, and a first P-type Gate (P-Gate)40 is arranged above the part of the N-Well; a part of an N Well (N-Well)60 is arranged among the high-concentration P type doping (P +)22, the low-concentration N type light doping (NLDD)30 and the high-concentration P type doping (P +)24, a layer of P type ESD doping (P-ESD IMP)10 is arranged right below the bottom of the high-concentration P type doping (P +)22 and the bottom of the high-concentration P type doping (P +)24, namely a layer of P type ESD doping (P-ESD IMP)10 is arranged below the bottom of the high-concentration P type doping (P +)22, the bottom of the low-concentration N type light doping (NLDD)30, the bottom of the high-concentration P type doping (P +)24 and a space part between the bottom and the bottom of the high-concentration P type doping (P +) 24; a part of an N Well (N-Well)60 is arranged between the high-concentration N-type doping (N +)24 and the high-concentration P-type doping (P +)26, a second P-type Gate (P-Gate)42 is arranged above the part of the N Well, and a Shallow Trench Isolation (STI) 70 is used for isolating the high-concentration P-type doping (P +)26 and the high-concentration N-type doping (N +) 34; the interval between the high-concentration P-type doping (P +)22 and the low-concentration N-type lightly doping (NLDD)30 is S, the interval between the low-concentration N-type lightly doping (NLDD)30 and the high-concentration P-type doping (P +)24 is S, the width of the high-concentration P-type doping (P +)22 and the high-concentration P-type doping (P +)24 is a, and the width of the low-concentration N-type lightly doping (NLDD)30 is B;
2 metal silicides 50 are generated above the high-concentration N-type doping (N +)32 and above the high-concentration P-type doping (P +)20 and are connected with a first P-type Gate (P-Gate)40 to form an Anode Antode of the PMOS device, a metal silicide 50 extraction electrode is generated above the low-concentration N-type light doping (NLDD)30 to be used as a Cathode Catode of the PMOS device, and 2 metal silicides 50 are generated above the high-concentration N-type doping (N +)34 and above the high-concentration P-type doping (P +)26 and are connected with a second P-type Gate (P-Gate)42 to form an Anode Antode of the PMOS device.
The PMOS device of the embedded scr for ESD proposed by the present invention is actually to replace the high concentration N-type doping connected to the cathode in the existing PMOS device of the embedded scr as shown in figure 1 with the low concentration N-type lightly doped (NLDD)30, the low-concentration N-type lightly doped (NLDD)30 is used as an emitter of a parasitic NPN (low-concentration N-type lightly doped (NLDD) 30/P-type ESD doped (P-ESD IMP)10/N Well (N-Well)60) triode inside a PMOS device embedded with a silicon controlled rectifier, the efficiency of emitting electrons is reduced due to the reduction of the N-type doping concentration, and the current gain (beta) of a parasitic NPN (low-concentration N-type light doping (NLDD) 30/P-type ESD doping (P-ESD IMP)10/N Well (N-Well)60) triode in the novel PMOS device is reduced.NPN) (ii) a On the other hand, the efficiency of emitting holes to an N Well (N-Well)60 by the high-concentration P-type doping (P +)20 and the high-concentration P-type doping (P +)26 can be reduced to a certain degree by removing the high-concentration P-type doping (P +)20 connected with the anode and the P-ESD doping (P-ESD IMP)11-12 below the high-concentration P-type doping (P +)26, so that the current gain (beta) of a PNP (high-concentration P-type doping (P +)20 or 26/N Well (N-Well) 60/P-type ESD doping (P-ESD IMP)10) triode parasitic in the PMOS device is reduced to a certain degreePNP) And the combination of the two can improve the holding voltage of the hysteresis effect of the PMOS device of the embedded silicon controlled rectifier to be more than 2.2V, so the PMOS device of the embedded silicon controlled rectifier is more suitable for the anti-static protection design of a 28nm High-K/Metal Gate process platform.
In the invention, the size A, B, S of the PMOS device of the embedded silicon controlled rectifier for ESD and the NLDD doping concentration determine the hysteresis effect characteristic thereof, wherein A is 0.1-1 um, B is 0.1-2 um, S is 0-2 um, and the doping concentration dose range is 1E 12-1E 15/cm2。
FIG. 3 is a flowchart illustrating a method for implementing a PMOS device with embedded SCR according to a preferred embodiment of the present invention. As shown in fig. 3, the method for implementing a PMOS device with an embedded scr of the present invention includes the following steps:
in step S1, a semiconductor substrate is provided, and in one embodiment of the present invention, a P-type substrate (P-Sub)80 is provided, and an N-Well (N-Well)60 is formed in the P-type substrate (P-Sub) 80.
Step S2, forming an equivalent PNP triode structure on the upper left portion of the N-Well (N-Well)60 by using the high-concentration P-type dopant (P +)20, the N-Well (N-Well)60 and the P-type ESD dopant (P-ESD IMP)10, forming an equivalent PNP triode structure on the upper middle portion of the N-Well (N-Well)60 by using the N-Well (N-Well)60, the P-type ESD dopant (P-ESD IMP)10 and the low-concentration N-type lightly dopant (NLDD)30, forming an equivalent PNP triode structure on the upper right portion of the N-Well (N-Well)60 by using the high-concentration P-type dopant (P +)26, the N-Well (N-Well)60 and the P-type ESD dopant (P-ESD IMP)10, specifically, placing the high-concentration N-type dopant (N +)32, the high-concentration P-type dopant (P +)20 on the upper left portion of the N-Well (N-Well)60, and placing the high-concentration P-type dopant (P +)20, The N Well (N-Well)60 and the P type ESD doping (P-ESD IMP)10 form an equivalent PNP triode structure, the high-concentration P type doping (P +)22, the low-concentration N type light doping (NLDD)30 and the high-concentration P type doping (P +)24 are arranged on the middle upper portion of the N Well (N-Well)60, the P type ESD doping (P-ESD IMP)10 and the low-concentration N type light doping (NLDD)30 form an equivalent NPN triode structure, the high-concentration N type doping (N +)34 and the high-concentration P type doping (P +)26 are arranged on the right upper portion of the N Well (N-Well)60, and the high-concentration P type doping (P +)26, the N Well (N-Well)60 and the P type ESD doping (P-ESD IMP)10 form the equivalent PNP triode structure.
Wherein, the high concentration N-type doping (N +)32 and the high concentration P-type doping (P +)20 are isolated by a Shallow Trench Isolation (STI) 70, the right side of the high concentration P-type doping (P +)20 and the high concentration P-type doping (P +)22 are a part of an N-Well (N-Well)60, and a first P-type Gate (P-Gate)40 is arranged above the part of the N-Well; a part of an N Well (N-Well)60 is arranged among the high-concentration P type doping (P +)22, the low-concentration N type light doping (NLDD)30 and the high-concentration P type doping (P +)24, a layer of P type ESD doping (P-ESD IMP)10 is arranged right below the bottom of the high-concentration P type doping (P +)22 and the bottom of the high-concentration P type doping (P +)24, namely a layer of P type ESD doping (P-ESD IMP)10 is arranged below the bottom of the high-concentration P type doping (P +)22, the bottom of the low-concentration N type light doping (NLDD)30, the bottom of the high-concentration P type doping (P +)24 and a space part between the bottom and the bottom of the high-concentration P type doping (P +) 24; a part of an N Well (N-Well)60 is arranged between the high-concentration N-type doping (N +)24 and the high-concentration P-type doping (P +)26, a second P-type Gate (P-Gate)42 is arranged above the part of the N Well, and a Shallow Trench Isolation layer (STI) 70 is used for isolating the part between the high-concentration P-type doping (P +)26 and the high-concentration N-type doping (N +) 34; the interval between the high concentration P type doping (P +)22 and the low concentration N type lightly doping (NLDD)30 is S, the interval between the low concentration N type lightly doping (NLDD)30 and the high concentration P type doping (P +)24 is S, the width of the high concentration P type doping (P +)22 and the high concentration P type doping (P +)24 is a, and the width of the low concentration N type lightly doping (NLDD)30 is B.
Step S3, 2 metal silicides 50 are formed above the high concentration N-type dopant (N +)32 and above the high concentration P-type dopant (P +)20 and connected to the first P-Gate (P-Gate)40 to form an Anode of the PMOS device of the present invention, a metal silicide 50 extraction electrode is formed above the low concentration N-type light dopant (NLDD)30 to serve as a Cathode of the PMOS device of the present invention, and 2 metal silicides 50 are formed above the high concentration N-type dopant (N +)34 and above the high concentration P-type dopant (P +)26 and connected to the second P-Gate (P-Gate)42 to form an Anode of the PMOS device of the present invention.
When in application, in order to protect an IO port, the Cathode of a PMOS device of the silicon controlled rectifier is connected with an external IO (input/output end) and is internally connected with an internal circuit, the PMOS device is grounded Vss through some ESD protection device, the Anode of the PMOS device is connected with a power supply voltage Vdd, and the Anode of the PMOS device is connected with an Anode Anode; in order to protect the power supply, some other ESD protection device may be connected after the PMOS device of the embedded scr to obtain the required characteristics, as shown in fig. 4.
In summary, according to the PMOS device with embedded silicon controlled rectifier and the implementation method thereof, the High-concentration N-type doping connected to the cathode in the existing PMOS device with embedded silicon controlled rectifier is replaced by the lightly doped N-type lightly doped (NLDD), and the P-ESD doping below the High-concentration P-type doping connected to the anode is removed, so that the secondary breakdown current of the PMOS device can be increased while the holding voltage is increased to be higher than the working voltage thereof.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (7)
1. A PMOS device with embedded scr, the PMOS device comprising:
a semiconductor substrate;
an N well generated in the semiconductor substrate;
a thirty-second high-concentration N-type doping and a twenty-fourth high-concentration P-type doping are arranged on the left side of the N well, a twenty-second high-concentration P-type doping, a thirty-low concentration N-type light doping and a twenty-fourth high-concentration P-type doping are arranged in the middle of the N well, a thirty-fourth high-concentration N-type doping and a twenty-sixth high-concentration P-type doping are arranged on the right side of the N well, and a layer of P-type ESD doping is arranged below the bottom of the twenty-second high-concentration P-type doping, the bottom of the thirty-low concentration N-type light doping, the bottom of the twenty-fourth high-concentration P-type doping and the middle interval part of the bottom of;
a first P-type gate is arranged above the twenty-second high-concentration P-type doping room, and a second P-type gate is arranged above the twenty-fourth high-concentration P-type doping room and the twenty-sixth high-concentration P-type doping room;
metal silicide is generated above the thirty-second high-concentration N-type doping and above the twenty-second high-concentration P-type doping and is connected with the first P-type grid to form the anode of the PMOS device, a metal silicide leading-out electrode is generated above the thirty-second low-concentration N-type light doping and is used as the cathode of the PMOS device, and metal silicide is generated above the thirty-fourth high-concentration N-type doping and above the twenty-sixth high-concentration P-type doping and is connected with the second P-type grid to form the anode of the PMOS deviceAn anode of the PMOS device; the hysteresis effect characteristic of the PMOS device is determined by the width A of the twenty-second high-concentration P-type doping and the twenty-fourth high-concentration P-type doping, the width B of the thirty-low-concentration N-type light doping, the interval between the twenty-second high-concentration P-type doping and the thirty-low-concentration N-type light doping, the interval S between the thirty-low-concentration N-type light doping and the twenty-fourth high-concentration P-type doping and the doping concentration of the thirty-low-concentration N-type light doping, wherein A is 0.1-1 um, B is 0.1-2 um, S is 0-2 um, and the dosage range of the doping concentration is 1E 12-1E 15/cm2。
2. The scr embedded PMOS device of claim 1, wherein: the twenty-high concentration P-type doping, the N-well and the P-type ESD doping form an equivalent PNP triode structure.
3. The scr embedded PMOS device of claim 1, wherein: and the N well, the P-type ESD doping and the thirty-low-concentration N-type light doping form an equivalent NPN triode structure.
4. The scr embedded PMOS device of claim 2, wherein: and the twenty-sixth high-concentration P-type doping, the N well and the P-type ESD doping form an equivalent PNP triode structure.
5. The scr embedded PMOS device of claim 1, wherein: the thirty-second high-concentration N-type doping and the twenty-second high-concentration P-type doping are isolated by a shallow trench isolation layer, and a part of the N well is arranged between the right side of the twenty-second high-concentration P-type doping and the twenty-second high-concentration P-type doping.
6. The scr embedded PMOS device of claim 1, wherein: and a part of the N well is arranged between the twenty-fourth high-concentration P-type doping and the twenty-sixth high-concentration P-type doping, and the twenty-sixth high-concentration P-type doping and the thirty-fourth high-concentration N-type doping are isolated by a shallow trench isolation layer.
7. A method for realizing a PMOS device with a built-in silicon controlled rectifier is characterized by comprising the following steps:
step S1, providing a semiconductor substrate, and forming an N-well in the semiconductor substrate;
step S2, placing the thirty-second high-concentration N-type doping and the twenty-second high-concentration P-type doping on the left side of the N well, placing the twenty-second high-concentration P-type doping, the thirty-low concentration N-type light doping and the twenty-fourth high-concentration P-type doping in the middle of the N well, placing the thirty-fourth high-concentration N-type doping and the twenty-sixth high-concentration P-type doping on the right side of the N well, a layer of P-type ESD doping is arranged below the bottom of the twenty-second high-concentration P-type doping, the bottom of the thirty-low-concentration N-type light doping, the bottom of the twenty-fourth high-concentration P-type doping and the middle spacing part of the bottom, a first P-type grid is arranged above the space between the twenty-second high-concentration P-type doping and the twenty-second high-concentration P-type doping, a second P-type gate is arranged above the twenty-fourth high-concentration P-type doping and the twenty-sixth high-concentration P-type doping;
step S3, forming metal silicide above the thirty-second high-concentration N-type doping and above the twenty-second high-concentration P-type doping and connecting the metal silicide with the first P-type gate to form an anode of the PMOS device, forming a metal silicide extraction electrode above the thirty-second low-concentration N-type lightly doped region as a cathode of the PMOS device, and forming metal silicide above the thirty-fourth high-concentration N-type doping and above the twenty-sixth high-concentration P-type doping and connecting the metal silicide with the second P-type gate to form an anode of the PMOS device; the hysteresis effect characteristic of the PMOS device is determined by the width A of the twenty-second high-concentration P-type doping and the twenty-fourth high-concentration P-type doping, the width B of the thirty-low-concentration N-type light doping, the interval between the twenty-second high-concentration P-type doping and the thirty-low-concentration N-type light doping, the interval S between the thirty-low-concentration N-type light doping and the twenty-fourth high-concentration P-type doping and the doping concentration of the thirty-low-concentration N-type light doping, wherein A is 0.1-1 um, B is 0.1-2 um, S is 0-2 um, and the dosage range of the doping concentration is 1E 12-1E 15/cm 2.
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| CN107516657A (en) * | 2017-07-31 | 2017-12-26 | 上海华力微电子有限公司 | A kind of new E SD protection structures and its implementation |
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