CN110504314B - Groove-type insulated gate bipolar transistor and preparation method thereof - Google Patents
Groove-type insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
A trench-type insulated gate bipolar transistor and a preparation method thereof belong to the technical field of power semiconductors. According to the invention, the first conductive type channel MOSFET is introduced into the second conductive type floating area of the trench type insulated gate bipolar transistor, wherein the gate electrode of the MOSFET is in short circuit with the current conversion metal, so that when the device is conducted in the forward direction, the MOSFET is in a turn-off state due to the lower potential of the floating area, and the electron current converted by the conversion metal cannot flow out of the drain electrode through the MOSFET, so that the forward conduction voltage drop cannot be increased; when the device is turned off, because the potential of the floating space area is very high, the channel electron on the surface of the MOSFET is inverted, and an electron circulation path is formed, so that the electron current converted by the hole current through the conversion metal can flow out of the drain electrode through the MOSFET, the extraction speed of the surplus current carrier is accelerated, the turn-off time and the turn-off loss are reduced, and the compromise characteristic of the forward conduction and the turn-off loss is improved. In addition, the invention also relates to a preparation method of the trench type insulated gate bipolar transistor.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a groove type insulated gate bipolar transistor and a preparation method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) is used as an IGBT (Insulated Gate Bipolar Transistor) controlled Bipolar device, and the higher the concentration of non-equilibrium carriers in the body, the more significant the conductivity modulation effect, and the higher the current density. Fig. 1 shows a half-cell structure of a conventional trench IGBT device, when the device is turned on in the forward direction, due to the existence of the second conductive type floating area 15, the carrier concentration on the emitter side is increased during the forward direction conduction, so that the conduction voltage drop is reduced, but when the IGBT is turned off, a large amount of excess carriers cannot be extracted through the second conductive type floating area 15, so that the turn-off time is increased, the turn-off loss Eoff is increased, and the compromise characteristic between Vce and Eoff is deteriorated. As shown in fig. 2, in order to accelerate the extraction of the excess carriers in the first conductivity type semiconductor drift region 8 during turn-off, the second conductivity type floating empty region 15 is connected to the emitter metal 4 of the device, so that during turn-off, the excess carriers can be extracted through the second conductivity type floating empty region 15, thereby reducing the turn-off time and reducing the turn-off loss Eoff, but when the device is turned on in the forward direction, a part of holes flow into the second conductivity type floating empty region 15 and flow out from the emitter metal 4 on the upper portion of the second conductivity type floating empty region, so that the conductance modulation of the drift region is weakened, vce is increased, and the compromise characteristic between Vce and Eoff is also deteriorated. Therefore, a new IGBT cell structure is needed, which has a significant conductance modulation effect when conducting in the forward direction to ensure that no conduction voltage drop is increased, and can extract excess carriers in the first conductivity type semiconductor drift region 8 when the device is turned off, so as to reduce the turn-off time and turn-off loss, so that the compromise characteristic of the forward conduction and turn-off loss is better improved, and the electrical characteristics of the device are improved.
Disclosure of Invention
The invention provides a trench-type insulated gate bipolar transistor and a preparation method thereof, aiming at solving the problems in the prior art.
To solve the above technical problem, the present invention provides a trench type insulated gate bipolar transistor, including: the device comprises a metalized collector, a second conductive type collector region, a first conductive type semiconductor field stop layer, a first conductive type semiconductor drift region, a second conductive type semiconductor base region, a second conductive type semiconductor emitter region, a first conductive type semiconductor emitter region, a trench gate structure, emitter metal and a second conductive type floating space region;
the metallized collector is positioned below the second conductive type collector region, and the first conductive type semiconductor field stop layer and the first conductive type semiconductor drift region are sequentially positioned on the second conductive type collector region; the second conductive type semiconductor base region is positioned at one end above the first conductive type semiconductor drift region, the second conductive type semiconductor emitter region and the first conductive type semiconductor emitter region are positioned on the second conductive type semiconductor base region side by side, and the side surfaces of the second conductive type semiconductor emitter region and the first conductive type semiconductor emitter region are mutually contacted;
the second conductive type floating space region is positioned at the other end above the first conductive type semiconductor drift region; the trench gate structure is positioned on the first conductive type semiconductor drift region between the second conductive type semiconductor base region and the second conductive type floating region, one side surface of the trench gate structure is contacted with one side surfaces of the first conductive type semiconductor drift region, the second conductive type semiconductor base region and the first conductive type semiconductor emitter region, and the other side surface of the trench gate structure is contacted with one side surface of the second conductive type floating region; emitter metal is located on the second conductive type semiconductor emitting region and a part of the first conductive type semiconductor emitting region;
introducing a first conductive type channel MOSFET, a medium isolation layer and current conversion metal into a second conductive type floating empty region, wherein the first conductive type channel MOSFET comprises a second base region of a second conductive type semiconductor, a first conductive type source region, a first conductive type drain region, a planar gate structure and drain metal;
the dielectric isolation layer and the second conductive type semiconductor second base region are arranged on one side above the second conductive type floating space region side by side, and the side surfaces of the dielectric isolation layer and the second conductive type semiconductor second base region are mutually contacted; the first conduction type source region and the first conduction type drain region are arranged on the second conduction type semiconductor base region at intervals (in the second conduction type semiconductor base region, one side surface of the medium isolation layer is contacted with one side surface of the first conduction type source region;
the planar gate structure is positioned on a first part of the first conduction type source region, a first part of the second conduction type semiconductor second base region and a first part of the first conduction type drain region; the drain electrode metal is positioned on the second part of the first conduction type drain region and the second part of the second conduction type semiconductor second base region; the current conversion metal is positioned on part of the second conductive type floating area, the medium isolation layer and the second part of the first conductive type source area; the planar gate structure comprises a first gate dielectric layer and a first gate electrode on the first gate dielectric layer, the first gate electrode is in short circuit with current conversion metal, and the doping concentration of a second base region of the second conductive type semiconductor is greater than that of the second conductive type floating region.
The beneficial effects of the invention are: the circulation path of excess carriers in the working process of the IGBT is controlled by introducing a first conductive type channel MOSFET into the second conductive type floating space region, and when the device is conducted, the carrier concentration on one side of an emitter is enhanced, the conductance modulation effect is enhanced, and the conduction voltage drop is reduced; when the device is turned off, the extraction speed of the excess carriers is accelerated, and the turn-off time and the turn-off loss are reduced. Therefore, the advantages of the IGBT and the IGBT are combined, and the compromise relation between the turn-on voltage drop and the turn-off loss of the IGBT is improved.
On the basis of the technical scheme, the invention can be further improved as follows.
The semiconductor device further comprises at least one first-conductivity-type floating buried layer, wherein the at least one first-conductivity-type floating buried layer is located between the second-conductivity-type floating area and the second-conductivity-type semiconductor second base region, one side face of the first-conductivity-type floating buried layer is in contact with the other side face of the second-conductivity-type floating area, and the depth of the first-conductivity-type floating buried layer is smaller than or equal to that of the second-conductivity-type floating area.
The beneficial effect of adopting the further scheme is that: at least one first conductive type floating buried layer is introduced, so that a cavity is prevented from flowing into a drain electrode from the right half part of the second conductive type floating area, the conductivity modulation effect is further enhanced, the conduction voltage drop of the device is greatly reduced, and the compromise relation between the conduction voltage drop and the turn-off loss is further optimized.
Furthermore, a part of the second conduction type floating area is arranged between the trench gate structure and the first conduction type semiconductor drift area.
The beneficial effect of adopting the further scheme is that: the second conductive type floating empty area surrounds the top end of the bottom of the trench gate structure, so that the electric field of a gate oxide layer at the bottom of the trench gate is reduced, the reliability of the device is improved, the capacitance of a collector of the gate is shielded, the reverse transmission capacitance of the device is reduced, and the switching speed of the device is improved.
Furthermore, part of gate electrodes of the groove gate structure are short-circuited with the emitter metal to form a split gate structure.
The beneficial effect of adopting the above further scheme is: the capacitance of a grid collector/grid emitter on the right side of the trench grid structure is shielded, the reverse transmission capacitance of the device is reduced, and the switching speed of the device is improved.
The semiconductor drift region is arranged between the second conduction type semiconductor base region and the first conduction type semiconductor drift region, and the doping concentration of the first conduction type semiconductor carrier storage layer is larger than that of the first conduction type semiconductor drift region.
The beneficial effect of adopting the further scheme is that: the first conduction type carrier storage layer enhances the conductance modulation effect in the device, reduces the conduction voltage drop, and further improves the compromise relation between the conduction voltage drop and the turn-off loss.
Furthermore, the emitter metal extends downwards through the second conduction type semiconductor emitter region, and the depth of the emitter metal is smaller than the junction depth of the second conduction type semiconductor base region (6).
The beneficial effect of adopting the above further scheme is: the emitter metal extends downwards into the device, so that the latch-up resistance of the device is enhanced, and the reliability of the device is improved.
Further, the emitter metal further comprises a second conductivity type semiconductor layer, the second conductivity type semiconductor layer is arranged between the second conductivity type semiconductor emitter region and the emitter metal, and the forbidden bandwidth of the second conductivity type semiconductor layer is smaller than that of the second conductivity type semiconductor emitter region.
The beneficial effect of adopting the further scheme is that: the second conduction type semiconductor layer and the second conduction type semiconductor emitting region form a heterojunction, and the heterojunction is used as a hole barrier when the heterojunction is conducted in the forward direction, so that the carrier concentration on one side of the emitting electrode of the device is enhanced, and the conduction voltage drop is reduced.
Further, the semiconductor device further comprises a second conductivity type semiconductor layer, the second conductivity type semiconductor layer is arranged in the second conductivity type semiconductor emitter region, and the forbidden bandwidth of the second conductivity type semiconductor layer is smaller than that of the second conductivity type semiconductor base region.
The beneficial effect of adopting the above further scheme is: the second conductive type semiconductor layer and the second conductive type semiconductor base region form a heterojunction, and the heterojunction is used as a hole barrier when conducting in the forward direction, so that the conductivity modulation effect in the device is enhanced, the conduction voltage drop is reduced, the latch-up resistance of the device is enhanced, and the reliability of the device is improved.
In order to solve the above technical problem, the present invention further provides a method for manufacturing a trench type insulated gate bipolar transistor, including the following steps:
selecting a second conductive type semiconductor substrate as a second conductive type collector region of the device, and sequentially forming a first conductive type semiconductor field stop layer and a first conductive type semiconductor drift region above the semiconductor substrate;
forming a second conductive type semiconductor base region at one end above the first conductive type semiconductor drift region, forming a second conductive type semiconductor emitter region and a first conductive type semiconductor emitter region above the second conductive type semiconductor base region, wherein one side surface of the second conductive type semiconductor emitter region is contacted with one side surface of the first conductive type semiconductor emitter region;
forming a second conductive type floating space area at the other end above the first conductive type semiconductor drift area; forming a dielectric isolation layer and a second conductive type semiconductor second base region on one side above the second conductive type floating space region, wherein one side surface of the dielectric isolation layer is mutually contacted with one side surface of the second conductive type semiconductor second base region; the other side surface of the medium isolation layer is in contact with one side surface of the second conductive type floating empty area; forming a first conductive type source region and a first conductive type drain region in a second conductive type semiconductor second base region at intervals, wherein one side surface of the first conductive type source region is contacted with one side surface of the medium isolation layer;
forming a trench gate structure on the first conductive type semiconductor drift region between the second conductive type semiconductor base region and the second conductive type floating region, wherein one side surface of the trench gate structure is contacted with one side surfaces of the first conductive type semiconductor drift region, the second conductive type semiconductor base region and the first conductive type semiconductor emitter region, and the other side surface of the trench gate structure is contacted with the other side surface of the second conductive type floating region;
forming an emitter metal on the second conductive type semiconductor emitter region and a portion of the first conductive type semiconductor emitter region; sequentially forming a first gate dielectric layer and a first gate electrode on a first part of the first conductive type source region, a first part of the second conductive type semiconductor second base region and a first part of the first conductive type drain region; forming a drain metal on a second portion of the first conductive type drain region and a second portion of the second conductive type semiconductor second base region; forming a current conversion metal on part of the second conductive type floating area, the dielectric isolation layer and a second part of the first conductive type source area; the first gate electrode is in short circuit with the current conversion metal, and the doping concentration of the second base region of the second conductive type semiconductor is greater than that of the second conductive type floating region;
a metallized collector is formed under the second conductivity type collector region.
The invention has the beneficial effects that: the circulation path of excess carriers in the working process of the IGBT is controlled by introducing a first conductive type channel MOSFET into the second conductive type floating space region, and when the device is conducted, the carrier concentration on one side of an emitter is enhanced, the conductance modulation effect is enhanced, and the conduction voltage drop is reduced; when the device is turned off, the extraction speed of the excess carriers is accelerated, and the turn-off time and the turn-off loss are reduced. Therefore, the advantages of the IGBT and the IGBT are combined, and the compromise relation between the turn-on voltage drop and the turn-off loss of the IGBT is improved.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the method also comprises the following steps: before forming the emitter metal, a second conductive type semiconductor layer is formed on the second conductive type semiconductor emitter region, and the emitter metal is formed on a portion of the first conductive type semiconductor emitter region and the second conductive type semiconductor layer, and a forbidden bandwidth of the second conductive type semiconductor layer is smaller than that of the second conductive type semiconductor emitter region.
The beneficial effect of adopting the further scheme is that: the second conduction type semiconductor layer and the second conduction type semiconductor emitting region form a heterojunction, and the heterojunction is used as a hole barrier when the heterojunction is conducted in the forward direction, so that the carrier concentration on one side of the emitting electrode of the device is enhanced, and the conduction voltage drop is reduced.
Drawings
Fig. 1 is a schematic diagram of a half-cell structure of a conventional trench IGBT;
fig. 2 is a schematic diagram of a half-cell structure of another conventional trench IGBT device;
fig. 3 is a schematic diagram of a half-cell structure of a trench IGBT according to a first embodiment of the present invention;
fig. 4 is a schematic diagram of a half-cell structure of a trench IGBT according to a second embodiment of the present invention;
fig. 5 is a schematic diagram of a half-cell structure of a trench IGBT according to a third embodiment of the present invention;
fig. 6 is a schematic diagram of a half-cell structure of a trench IGBT according to a fourth embodiment of the present invention;
fig. 7 is a schematic diagram of a half-cell structure of a trench IGBT according to a fifth embodiment of the present invention;
fig. 8 is a schematic diagram of a half-cell structure of a trench IGBT according to a sixth embodiment of the present invention;
fig. 9 is a schematic diagram of a half-cell structure of a trench IGBT according to a seventh embodiment of the present invention;
fig. 10 is a schematic diagram of a half-cell structure of a trench IGBT according to an eighth embodiment of the present invention;
FIG. 11 is an energy band diagram after the formation of a GeSi/Si heterojunction according to the present invention.
In the drawings, the components represented by the respective reference numerals are listed below:
1. a second gate electrode, 2, a second gate dielectric layer, 3, a first conductivity type semiconductor emitter region, 4, an emitter metal, 5, a second conductivity type semiconductor emitter region, 6, a second conductivity type semiconductor base region, 8, a first conductivity type semiconductor drift region, 9, a first conductivity type semiconductor field stop layer, 10, a second conductivity type collector region, 11, a metalized collector, 12, a first conductivity type floating buried layer, 13, a second conductivity type semiconductor second base region, 14, a first gate electrode, 15, a second conductivity type floating region, 17, a first conductivity type drain region, 18, a first conductivity type source region, 19, a current converting metal, 20, a drain metal, 21, a first conductivity type semiconductor carrier storage layer, 22, a second conductivity type semiconductor layer, 23, a first gate dielectric layer, 25, a dielectric isolation layer.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 3, a first embodiment of the present invention provides a trench type insulated gate bipolar transistor, including: a metallized collector 11, a second conductive type collector region 10, a first conductive type semiconductor field stop layer 9, a first conductive type semiconductor drift region 8, a second conductive type semiconductor base region 6, a second conductive type semiconductor emitter region 5, a first conductive type semiconductor emitter region 3, a trench gate structure, emitter metal 4, a first conductive type floating buried layer 12, a second conductive type semiconductor second base region 13, a first conductive type source region 18, a first conductive type drain region 17, a planar gate structure, drain metal 20, current conversion metal 19, a dielectric isolation layer 25 and a second conductive type floating region 15;
the metallized collector 11 is positioned below the second conductive type collector region 10, and the first conductive type semiconductor field stop layer 9 and the first conductive type semiconductor drift region 8 are sequentially positioned on the second conductive type collector region 10; the second conductive type semiconductor base region 6 is positioned at one end above the first conductive type semiconductor drift region 8, the second conductive type semiconductor emitter region 5 and the first conductive type semiconductor emitter region 3 are positioned on the second conductive type semiconductor base region 6 side by side, and the side surfaces are mutually contacted;
the second conductivity type floating region 15 is located at the other end above the first conductivity type semiconductor drift region 8; the first-conductivity-type floating buried layer 12 is located on one side above the second-conductivity-type floating empty region 15; the dielectric isolation layer 25 and the second conductive type semiconductor second base region 13 are arranged on the first conductive type floating buried layer 12 side by side, and the side surfaces of the dielectric isolation layer and the second conductive type semiconductor second base region are in contact with each other; one side surfaces of the dielectric isolation layer 25 and the first conductive type floating buried layer 12 are in contact with one side surface of the second conductive type floating area 15; the first conduction type source region 18 and the first conduction type drain region 17 are positioned in the second conduction type semiconductor second base region 13 at intervals, and one side face of the first conduction type source region 18 is in contact with the other side face of the medium isolation layer 25;
the trench gate structure is positioned on the first conduction type semiconductor drift region 8 between the second conduction type semiconductor base region 6 and the second conduction type floating empty region 15, one side surface of the trench gate structure is contacted with the first conduction type semiconductor drift region 8, the second conduction type semiconductor base region 6 and one side surface of the first conduction type semiconductor emitter region 3, and the other side surface of the trench gate structure is contacted with the other side surface of the second conduction type floating empty region 15;
In the above embodiment, the trench gate structure includes the second gate electrode 1, and the second gate dielectric layers 2 disposed on two side surfaces and a bottom surface of the second gate electrode 1; the first gate electrode 14 and the second gate electrode 1 may be metal gate electrodes or polysilicon gate electrodes, and the first gate dielectric layer 23 and the second gate dielectric layer 2 may be gate oxide layers; the first conductive type floating buried layer 12 can also be other dielectric layers.
The depth of the second conductive type floating area 15 is greater than or equal to that of the trench gate structure, and the thickness of the dielectric isolation layer 25 is equal to that of the second conductive type semiconductor second base area 13; the depth of the first-conductivity-type floating buried layer 12 is less than or equal to that of the second-conductivity-type floating area 15; the second conductivity type semiconductor second base region 13, the first conductivity type source region 18, the first conductivity type drain region 17, the planar gate structure, and the drain metal 20 together constitute a first conductivity type channel MOSFET.
In addition, the first conduction type is an N type, the second conduction type is a P type, or the second conduction type is a P type, and the first conduction type is an N type. The first conductivity type semiconductor emitter region 3 is, for example, an N + silicon emitter region, the second conductivity type semiconductor emitter region 5 is, for example, a P + silicon emitter region, the second conductivity type semiconductor base region 6 is, for example, a P-type silicon base region, the first conductivity type semiconductor drift region 8 is, for example, an N-silicon drift region, the first conductivity type semiconductor field stop layer 9 is, for example, an N-type silicon field stop layer, the second conductivity type collector region 10 is, for example, a P-type silicon collector region, the first conductivity type semiconductor carrier storage layer 21 is, for example, an N-type silicon carrier storage layer, the first conductivity type floating buried layer 12 is, for example, an N + silicon buried layer, the second conductivity type semiconductor second base region 13 is, for example, a P-type silicon second base region, the second conductivity type floating region 15 is, for example, a silicon floating P-region, the second conductivity type semiconductor layer 22 is, for example, a P-type germanium silicon layer, the first conductivity type drain region 17 is, for example, an N-type silicon drain region, and the first conductivity type source region 18 is, for example, an N-type silicon source region. The semiconductor used by the device can be a single crystal material or a polycrystalline material, and the semiconductor material used by the device is silicon carbide, silicon, gallium arsenide, gallium nitride, gallium sesquioxide or diamond.
In addition, in the present embodiment, the doping concentration of the second conductivity type semiconductor base region 6 is 3 × 10 16 cm -3 ～2×10 17 cm -3 Thickness of 02-2 μm; the doping concentration of the second conductivity type semiconductor emitter region 5 is 5 × 10 18 cm -3 ～1×10 20 cm -3 The thickness is 0.2-0.5 μm; the second conductive type floating region 15 has a doping concentration of 3 × 10 16 cm -3 ～2×10 17 cm -3 The depth is 1-7 mu m; the doping concentration of the second conductivity type semiconductor second base region 13 is 5 × 10 16 cm -3 ～5×10 17 cm -3 The thickness is 0.2-2 μm; the doping concentration of the first conductivity type semiconductor emitter region 3 is 5 × 10 18 cm -3 ～1×10 20 cm -3 0.2-0.5 μm thick, and a doping concentration of the first conductivity type buried floating layer 12 of 5 × 10 18 cm -3 ～1×10 20 cm -3 The thickness is 1-2 μm; the thickness of the gate oxide layer is 20-100 nm; the doping concentration of the first conductive type source region 18 is 5 × 10 18 cm -3 ～1×10 20 cm -3 The thickness is 0.2-0.5 μm; the doping concentration of the first conductive type drain region 17 is 5 × 10 18 cm -3 ～1×10 20 cm -3 The thickness is 0.2-0.5 μm; the depth of the second gate electrode 1 is 1 to 10 μm; the thickness of the first gate electrode 14 is 0.2 to 1.5 μm; the first conductivity type semiconductor drift region 8 has a doping concentration of 7 × 10 13 cm -3 ～8×10 14 cm -3 The thickness is 60-150 μm; the doping concentration of the first conductivity type semiconductor field stop layer 9 is 5 × 10 15 cm -3 ～5×10 17 cm -3 The thickness is 1-5 μm; the doping concentration of the second conductive type collector region 10 is 1 × 10 17 cm -3 ～1×10 19 cm -3 The thickness is 1-5 μm; the width of the unit cell is 1-10 μm.
The following explains the principle of the present invention in detail by taking an N-channel IGBT as an example, and the specific principle is as follows:
introducing a cell structure of an N-channel MOSFET into a second conductive type floating area 15 of the trench type insulated gate bipolar transistor, wherein a first gate electrode 14 of the N-channel MOSFET is in short circuit with a current conversion metal 19, and the concentration of a second conductive type semiconductor second base area 13 is greater than that of the second conductive type floating area 15 so as to ensure that the threshold voltage of the N-channel MOSFET is higher than the potential of the second conductive type floating area 15 during forward conduction, so that when the device is in forward conduction, the potential of the second conductive type floating area 15 is lower and is not enough to turn on the N-channel MOSFET, and an electronic current converted by the current conversion metal 19 cannot flow out of a drain metal 20 through the N-channel MOSFET, thereby not weakening the electric field modulation effect in the IGBT and not increasing the forward conduction voltage drop; when the device is turned off, because the potential of the second conductive type floating space region 15 is raised, the current conversion metal 19 positioned in the second conductive type floating space region 15 is in short circuit with the first gate electrode 14, so that channel electrons on the surface of the N-channel MOSFET are inverted, and an electron circulation path is formed, so that electron current converted by hole current through the current conversion metal 19 can flow out of the drain metal 20 through the N-channel MOSFET, the extraction speed of surplus carriers is increased, the turn-off time is reduced, the turn-off loss is reduced, and the compromise characteristic of forward conduction and turn-off loss is improved, wherein the second conductive type floating space region 15 is a floating P region, and the second conductive type semiconductor second base region 13 is a P-type second base region.
As shown in fig. 4, a second embodiment of the present invention provides a trench-type insulated gate bipolar transistor, and this embodiment is based on the first embodiment, and a plurality of first-conductivity-type floating buried layers 12 are provided, and the depth of each first-conductivity-type floating buried layer is smaller than the depth of each second-conductivity-type floating area 15.
In the above embodiment, the plurality of first conductivity type floating buried layers 12 are introduced, so that holes are prevented from flowing into the drain from the right half portion of the second conductivity type floating region 15, the conductance modulation effect is further enhanced, the on-state voltage drop of the device is greatly reduced, and the compromise relationship between the on-state voltage drop and the turn-off loss is further optimized. The thicknesses of the plurality of first-conductivity-type floating buried layers 12 may be the same or different, and the pitches thereof may be the same or different, and the depth of the first-conductivity-type floating buried layer 12 located at the lowermost position is not more than the depth of the second-conductivity-type floating area 15.
As shown in fig. 5, a third embodiment of the present invention provides a trench-type insulated gate bipolar transistor, and in this embodiment, on the basis of the second embodiment, a part of the second-conductivity-type floating region 15 is further disposed between the trench gate structure and the first-conductivity-type semiconductor drift region 8.
In the above embodiment, the second conductive type floating space region 15 is L-shaped along the longitudinal section of the device and extends to the lower region of the bottom of the first trench gate structure to surround the top end of the bottom of the trench gate structure, so that the electric field of the gate oxide layer at the bottom of the trench gate is reduced, the reliability of the device is improved, the collector capacitance of the gate is shielded, the reverse transmission capacitance of the device is reduced, and the switching speed of the device is improved.
As shown in fig. 6, a trench-type insulated gate bipolar transistor is provided in a fourth embodiment of the present invention, and in this embodiment, based on the third embodiment, a part of the gate electrode of the trench-gate structure is shorted with the emitter metal 4, so as to form a split-gate structure.
The embodiment further shields the capacitance of the grid collector/grid emitter on the right side of the trench grid structure, reduces the reverse transmission capacitance of the device and improves the switching speed of the device. At this time, the trench gate structure is divided into two parts, one part is used as a gate electrode, and the other part is in short circuit with the emitter metal 4 to be used as an emitter, so that a split gate structure is formed.
As shown in fig. 7, a fifth embodiment of the present invention provides a trench-type insulated gate bipolar transistor, and in this embodiment, on the basis of the fourth embodiment, a first conductivity type semiconductor carrier storage layer 21 is further provided, the first conductivity type semiconductor carrier storage layer 21 is provided between the second conductivity type semiconductor base region 6 and the first conductivity type semiconductor drift region 8, and the doping concentration of the first conductivity type semiconductor carrier storage layer 21 is greater than that of the first conductivity type semiconductor drift region 8.
In the above embodiment, the first conductivity type carrier storage layer 21 is arranged to enhance the conductivity modulation effect inside the device, reduce the on-state voltage drop, and further improve the compromise relationship between the on-state voltage drop and the turn-off loss.
As shown in fig. 8, a sixth embodiment of the present invention provides a trench-type igbt, and in this embodiment, based on the fifth embodiment, the emitter metal 4 extends downward through the second conductivity type semiconductor emitter region 5, and the depth thereof is smaller than the junction depth of the second conductivity type semiconductor base region 6.
In the embodiment, the emitter metal extends downwards into the device, so that the latch-up resistance of the device is enhanced, and the reliability of the device is improved.
As shown in fig. 9, a seventh embodiment of the present invention provides a trench type insulated gate bipolar transistor, and in this embodiment, on the basis of the fifth embodiment, a second conductivity type semiconductor layer 22 is further provided, the second conductivity type semiconductor layer 22 is provided between the second conductivity type semiconductor emission region 5 and the emitter metal 4, and the energy gap width of the second conductivity type semiconductor layer 22 is smaller than the energy gap width of the second conductivity type semiconductor emission region 5.
In the above embodiment, the forbidden bandwidth of the second conductivity type semiconductor layer 22 is smaller than the forbidden bandwidth of the second conductivity type semiconductor emission region 5, so that the second conductivity type semiconductor layer 22 and the second conductivity type semiconductor emission region 5 form a heterojunction on their contact surfaces, as shown in fig. 11, which is a hole barrier when conducting in the forward direction, and thus the carrier concentration on the emitter side of the device is increased, and the conduction voltage drop is reduced.
As shown in fig. 10, an eighth embodiment of the present invention provides a trench-type insulated gate bipolar transistor, and in this embodiment, on the basis of the fifth embodiment, a second conductivity type semiconductor layer 22 is further provided, the second conductivity type semiconductor layer 22 is provided in the second conductivity type semiconductor emitter region 5, and the forbidden bandwidth of the second conductivity type semiconductor layer 22 is smaller than the forbidden bandwidth of the second conductivity type semiconductor base region 6.
In the above embodiment, the forbidden bandwidth of the second conductivity type semiconductor layer 22 is smaller than the forbidden bandwidth of the second conductivity type semiconductor base region 6, so that a heterojunction is formed between the second conductivity type semiconductor layer 22 and the second conductivity type semiconductor base region 6 on the contact surface thereof, as shown in fig. 11, the heterojunction is used as a hole barrier when conducting in the forward direction, which enhances the conductance modulation effect inside the device, reduces the conduction voltage drop, enhances the latch-up resistance of the device, and improves the reliability of the device. The depth of the second conductivity type semiconductor layer 22 is equal to or less than the depth of the second conductivity type semiconductor base region 6.
A ninth embodiment of the present invention provides a method for manufacturing a trench-type insulated gate bipolar transistor, including the steps of:
selecting a second conductive type semiconductor substrate as a second conductive type collector region 10 of the device, and sequentially forming a first conductive type semiconductor field stop layer 9 and a first conductive type semiconductor drift region 8 above the semiconductor substrate;
forming a second conductivity type semiconductor base region 6 at one end above the first conductivity type semiconductor drift region 8, forming a second conductivity type semiconductor emitter region 5 and a first conductivity type semiconductor emitter region 3 above the second conductivity type semiconductor base region 6, wherein the side surface of the second conductivity type semiconductor emitter region 5 and the side surface of the first conductivity type semiconductor emitter region 3 are in contact with each other;
a second conductivity type floating-out region 15 is formed at the other end above the first conductivity type semiconductor drift region 8; forming a first conductive-type floating buried layer 12 on one side above the second conductive-type floating empty region 15; forming a dielectric isolation layer 25 and a second conductive type semiconductor second base region 13 on the first conductive type floating buried layer 12, wherein one side surface of the dielectric isolation layer 25 is contacted with one side surface of the second conductive type semiconductor second base region 13; the other side surface of the dielectric isolation layer 25 and one side surface of the first-conductivity-type floating buried layer 12 are in contact with one side surface of the second-conductivity-type floating area 15; forming a first conductive type source region 18 and a first conductive type drain region 17 in the second conductive type semiconductor second base region 13 at intervals, wherein one side surface of the first conductive type source region 18 is in contact with one side surface of the medium isolation layer 25;
forming a trench gate structure on the first conductive type semiconductor drift region 8 between the second conductive type semiconductor base region 6 and the second conductive type floating region 15, wherein one side surface of the trench gate structure is contacted with the first conductive type semiconductor drift region 8, the second conductive type semiconductor base region 6 and one side surface of the first conductive type semiconductor emitter region 3, and the other side surface of the trench gate structure is contacted with the other side surface of the second conductive type floating region 15;
forming an emitter metal 4 on the second conductive type semiconductor emitter region 5 and a part of the first conductive type semiconductor emitter region 3; forming a first gate dielectric layer 23 and a first gate electrode 14 on a first portion of the first conductive type source region 18, a first portion of the second conductive type semiconductor second base region 13, and a first portion of the first conductive type drain region 17 in this order; forming a drain metal 20 on a second portion of the first conductive-type drain region 17 and a second portion of the second conductive-type semiconductor second base region 13; forming a current-converting metal 19 on a portion of the second-conductivity-type floating gate region 15, the dielectric isolation layer 25, and a second portion of the first-conductivity-type source region 18; the first gate electrode 14 is in short circuit with the current conversion metal 19, and the doping concentration of the second conductive type semiconductor second base region 13 is greater than that of the second conductive type floating region 15;
a metallized collector 11 is formed below the second conductivity type collector region 10.
In the above embodiment, a second conductive type semiconductor impurity is ion-implanted into the first conductive type semiconductor drift region 8 through a photolithography process, and then an annealing process is performed to form the second conductive type semiconductor base region 6 at one end above the first conductive type semiconductor drift region 8;
through a photoetching process, second conductive type semiconductor impurities are implanted into the first conductive type semiconductor drift region 8 in an ion implantation mode, then annealing treatment is carried out, and a second conductive type semiconductor floating region 15 is formed at the other end above the first conductive type semiconductor drift region 8;
through a photoetching process, first conductive type semiconductor impurities are ion-implanted into the second conductive type semiconductor floating empty region 15 or the second conductive type semiconductor base region 6, and then annealing treatment is carried out to form a first conductive type floating buried layer 12 and a first conductive type semiconductor emitter region 3;
through a photoetching process, second conductive type semiconductor type impurities are implanted into the second conductive type semiconductor floating space region 15 or the second conductive type semiconductor base region 6 in an ion implantation mode, and then annealing treatment is carried out to form a second conductive type semiconductor second base region 13 and a second conductive type semiconductor emitter region 5;
through a photoetching process, first conductive type semiconductor type impurities are implanted into the second conductive type semiconductor second base region 13 in an ion implantation mode, and then annealing treatment is carried out to form a first conductive type source region 18 and a first conductive type drain region 17;
etching a groove in the first conductive type semiconductor drift region 8 between the second conductive type semiconductor base region 6 and the second conductive type floating region 15 through a photoetching process to etch a grid groove, wherein the depth of the groove exceeds the junction depth of the second conductive type semiconductor base region 6, rinsing TEOS on the surface through HF solution after the groove is etched, and then growing a second grid dielectric layer 2 and a second grid electrode 1 in the grid groove through oxidation and deposition processes in sequence to form a groove grid structure;
forming a first gate dielectric layer 23 and a first gate electrode 14 of a planar gate structure through a photoetching process;
forming an emitter metal 4 and a drain metal 20 through an evaporation or sputtering process and then an etching process;
the metallized collector 11 is formed by an evaporation or sputtering process, and the thickness of the semiconductor substrate is reduced before the metallized collector 11 is formed.
The preparation process is simple and controllable, and has strong compatibility with the existing process.
Optionally, the method further comprises the steps of: before forming the emitter metal 4, a second conductivity type semiconductor layer 22 is formed on the second conductivity type semiconductor emitter region 5, the emitter metal 4 is formed on a portion of the first conductivity type semiconductor emitter region 3 and the second conductivity type semiconductor layer 22, and an energy gap width of the second conductivity type semiconductor layer 22 is smaller than that of the second conductivity type semiconductor emitter region 5.
In the above-described embodiment, the second conductivity type semiconductor layer 22 is epitaxially formed on the second conductivity type semiconductor emitter region 5 by the photolithography process.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the second feature or the first and second features may be indirectly contacting each other through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature "under," "beneath," and "under" a second feature may be directly under or obliquely under the second feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A trench-type insulated gate bipolar transistor comprising: the field emission type semiconductor device comprises a metalized collector (11), a second conductive type collector region (10), a first conductive type semiconductor field stop layer (9), a first conductive type semiconductor drift region (8), a second conductive type semiconductor base region (6), a second conductive type semiconductor emitter region (5), a first conductive type semiconductor emitter region (3), a trench gate structure, emitter metal (4) and a second conductive type floating region (15);
the metallized collector (11) is positioned below the second conductive type collector region (10), and the first conductive type semiconductor field stop layer (9) and the first conductive type semiconductor drift region (8) are sequentially positioned on the second conductive type collector region (10); the second conduction type semiconductor base region (6) is positioned at one end above the first conduction type semiconductor drift region (8), the second conduction type semiconductor emitter region (5) and the first conduction type semiconductor emitter region (3) are positioned on the second conduction type semiconductor base region (6) side by side, and the side faces of the second conduction type semiconductor emitter region and the side faces of the first conduction type semiconductor emitter region are mutually contacted;
the second conductive type floating-space region (15) is positioned at the other end above the first conductive type semiconductor drift region (8); the trench gate structure is positioned on the first conductive type semiconductor drift region (8) between the second conductive type semiconductor base region (6) and the second conductive type floating region (15), one side surface of the trench gate structure is in contact with one side surfaces of the first conductive type semiconductor drift region (8), the second conductive type semiconductor base region (6) and the first conductive type semiconductor emitter region (3), and the other side surface of the trench gate structure is in contact with one side surface of the second conductive type floating region (15); emitter metal (4) is located on the second conductivity type semiconductor emitter region (5) and a portion of the first conductivity type semiconductor emitter region (3);
the method is characterized in that a first conduction type channel MOSFET, a medium isolation layer (25) and a current conversion metal (19) are introduced into a second conduction type floating space region (15), wherein the first conduction type channel MOSFET comprises a second conduction type semiconductor second base region (13), a first conduction type source region (18), a first conduction type drain region (17), a planar gate structure and a drain metal (20);
the dielectric isolation layer (25) and the second conductive type semiconductor second base region (13) are arranged on one side above the second conductive type floating space region (15) side by side, and the side surfaces are mutually contacted; a first conduction type source region (18) and a first conduction type drain region (17) are arranged in the second conduction type semiconductor second base region (13) at intervals, and one side face of the medium isolation layer (25) is in contact with one side face of the first conduction type source region (18); the other side surface of the medium isolation layer (25) is contacted with the other side surface of the second conductive type floating space area (15);
a planar gate structure is located on a first portion of the first conductivity type source region (18), a first portion of the second conductivity type semiconductor second base region (13) and a first portion of the first conductivity type drain region (17); a drain metal (20) is located on a second portion of the first conductivity type drain region (17) and a second portion of the second conductivity type semiconductor second base region (13); a current conversion metal (19) is positioned on a part of the second conductive type floating space region (15), the dielectric isolation layer (25) and a second part of the first conductive type source region (18); the planar gate structure comprises a first gate dielectric layer (23) and a first gate electrode (14) arranged on the first gate dielectric layer, the first gate electrode (14) is in short circuit with a current conversion metal (19), and the doping concentration of a second conductive type semiconductor second base region (13) is larger than that of a second conductive type floating region (15).
2. The trench-type insulated gate bipolar transistor according to claim 1, wherein: the buried layer structure is characterized by further comprising at least one first-conductivity-type floating buried layer (12), wherein the at least one first-conductivity-type floating buried layer (12) is located between the second-conductivity-type floating space region (15) and the second-conductivity-type semiconductor second base region (13), one side face of the first-conductivity-type floating buried layer (12) is in contact with the other side face of the second-conductivity-type floating space region (15), and the depth of the first-conductivity-type floating buried layer (12) is smaller than or equal to that of the second-conductivity-type floating space region (15).
3. The trench-type insulated gate bipolar transistor according to claim 2, wherein: and a part of the second conductive type floating area (15) is also arranged between the trench gate structure and the first conductive type semiconductor drift area (8).
4. A trench type igbt according to claim 3, wherein: and part of gate electrodes of the groove gate structures are short-circuited with the emitter metal (4) to form the split gate structure.
5. A trench type insulated gate bipolar transistor according to any one of claims 1 to 4, wherein: the semiconductor drift region structure further comprises a first conduction type semiconductor carrier storage layer (21), the first conduction type semiconductor carrier storage layer (21) is arranged between the second conduction type semiconductor base region (6) and the first conduction type semiconductor drift region (8), and the doping concentration of the first conduction type semiconductor carrier storage layer (21) is larger than that of the first conduction type semiconductor drift region (8).
6. A trench type insulated gate bipolar transistor according to any one of claims 1 to 4, wherein: the emitter metal (4) extends downwards through the second conduction type semiconductor emitter region (5), and the depth of the emitter metal is smaller than the junction depth of the second conduction type semiconductor base region (6).
7. A trench type insulated gate bipolar transistor according to any one of claims 1 to 4, wherein: the semiconductor device further comprises a second conductivity type semiconductor layer (22), wherein the second conductivity type semiconductor layer (22) is arranged between the second conductivity type semiconductor emitter region (5) and the emitter metal (4), and the forbidden bandwidth of the second conductivity type semiconductor layer (22) is smaller than that of the second conductivity type semiconductor emitter region (5).
8. The trench insulated gate bipolar transistor according to any of claims 1 to 4, wherein: the semiconductor device further comprises a second conduction type semiconductor layer (22), the second conduction type semiconductor layer (22) is arranged in the second conduction type semiconductor emitter region (5), and the forbidden bandwidth of the second conduction type semiconductor layer (22) is smaller than that of the second conduction type semiconductor base region (6).
9. A preparation method of a groove type insulated gate bipolar transistor is characterized by comprising the following steps:
selecting a second conductive type semiconductor substrate as a second conductive type collector region (10) of the device, and sequentially forming a first conductive type semiconductor field stop layer (9) and a first conductive type semiconductor drift region (8) above the semiconductor substrate;
forming a second conductive type semiconductor base region (6) at one end above the first conductive type semiconductor drift region (8), forming a second conductive type semiconductor emitter region (5) and a first conductive type semiconductor emitter region (3) above the second conductive type semiconductor base region (6), wherein one side surface of the second conductive type semiconductor emitter region (5) and one side surface of the first conductive type semiconductor emitter region (3) are mutually contacted;
forming a second conductive type floating area (15) at the other end above the first conductive type semiconductor drift area (8); a dielectric isolation layer (25) and a second conductive type semiconductor second base region (13) are formed on one side above the second conductive type floating empty region (15), and one side face of the dielectric isolation layer (25) is contacted with one side face of the second conductive type semiconductor second base region (13); the other side surface of the medium isolation layer (25) is in contact with one side surface of the second conductive type floating space region (15); forming a first conduction type source region (18) and a first conduction type drain region (17) in a second conduction type semiconductor second base region (13) at intervals, wherein one side face of the first conduction type source region (18) is in contact with one side face of a medium isolation layer (25);
forming a trench gate structure on the first conduction type semiconductor drift region (8) between the second conduction type semiconductor base region (6) and the second conduction type floating empty region (15), wherein one side surface of the trench gate structure is contacted with the first conduction type semiconductor drift region (8), the second conduction type semiconductor base region (6) and the other side surface of the first conduction type semiconductor emitter region (3), and the other side surface of the trench gate structure is contacted with the other side surface of the second conduction type floating empty region (15);
forming an emitter metal (4) on the second conductivity type semiconductor emitter region (5) and a portion of the first conductivity type semiconductor emitter region (3); forming a first gate dielectric layer (23) and a first gate electrode (14) on a first part of a first conduction type source region (18), a first part of a second conduction type semiconductor second base region (13) and a first part of a first conduction type drain region (17) in sequence; forming a drain metal (20) on a second portion of the first conductivity type drain region (17) and a second portion of the second conductivity type semiconductor second base region (13); forming a current-converting metal (19) on a portion of the second-conductivity-type floating region (15), the dielectric isolation layer (25) and a second portion of the first-conductivity-type source region (18); the first gate electrode (14) is in short circuit with the current conversion metal (19), and the doping concentration of the second conductive type semiconductor second base region (13) is greater than that of the second conductive type floating region (15); a metallized collector (11) is formed under the second conductivity type collector region (10).
10. The method according to claim 9, wherein the step of forming the trench type insulated gate bipolar transistor comprises the steps of:
further comprising the steps of: before forming the emitter metal (4), a second conductivity type semiconductor layer (22) is formed on the second conductivity type semiconductor emitter region (5), the emitter metal (4) is formed on a portion of the first conductivity type semiconductor emitter region (3) and the second conductivity type semiconductor layer (22), and the forbidden bandwidth of the second conductivity type semiconductor layer (22) is smaller than that of the second conductivity type semiconductor emitter region (5).
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