CN110493551B - Display device, main board and control method - Google Patents
Display device, main board and control method Download PDFInfo
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- CN110493551B CN110493551B CN201910867342.6A CN201910867342A CN110493551B CN 110493551 B CN110493551 B CN 110493551B CN 201910867342 A CN201910867342 A CN 201910867342A CN 110493551 B CN110493551 B CN 110493551B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
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Abstract
The invention discloses a display device, a mainboard and a control method, wherein the mainboard comprises: the port detection circuit and the main chip; the port detection circuit includes: a control circuit, a first voltage dividing circuit and a second voltage dividing circuit; the control circuit can conduct or cut off the first signal end and the grounding end under the control of the signal of the chip pin; the first voltage division circuit can adjust the signal of the first signal end according to the signal of the second signal end; the second voltage division circuit can adjust the signal of the chip pin according to the signal of the second signal end, and the main chip is used for detecting or adjusting the signal of the chip pin. Through the mutual cooperation of the modules and the elements, whether the external equipment is inserted or not can be detected. In addition, only one chip pin of the main chip is multiplexed, so that the number of the chip pins is reduced, and the number of the main chip pins can be reduced or the chip pins originally used for detecting whether the external equipment is inserted can be used as other functions.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display device, a mainboard and a control method.
Background
A High Definition Multimedia Interface (HDMI) for transmitting signals is widely used. The general Source (sending) end and Sink (receiving) end usually adopt HDMI interfaces to realize signal transmission. In practical application, the Source terminal needs to be inserted into the Sink terminal for signal transmission. Then, in order to determine whether the external device as the Source terminal is plugged into the Sink terminal and works, two pins are usually provided on the chip at the Sink terminal: +5V Power and Hot Plug Detect. And determines whether the external device is plugged in and works by detecting the level change of the two pins +5V Power and Hot Plug Detect. According to the design, at least two special pins need to be arranged on the chip at the Sink end, and even another pin needs to be additionally arranged under some special conditions, so that the problems that the number of pins of the chip is large and the wiring of the pins is complex are caused.
Disclosure of Invention
The embodiment of the invention provides a display device, a mainboard and a control method, which are used for reducing pins arranged on a chip. An embodiment of the present invention provides a display device, including: a motherboard, the motherboard comprising: the port detection circuit and the main chip; the port detection circuit includes: a control circuit, a first voltage dividing circuit and a second voltage dividing circuit; wherein,
the control circuit is respectively and electrically connected with the first signal terminal, the chip pin of the main chip and the grounding terminal; the control circuit is used for switching on or off the first signal end and the grounding end under the control of the signal of the chip pin;
the first voltage division circuit is respectively and electrically connected with the first signal end and the second signal end; the first voltage division circuit is used for adjusting the signal of the first signal end according to the signal of the second signal end;
the second voltage division circuit is respectively and electrically connected with the chip pin and the second signal end; the second voltage division circuit is used for adjusting the signal of the chip pin according to the signal of the second signal end;
the main chip is used for detecting or adjusting signals of the chip pins.
Optionally, the control circuit comprises: a switching tube and a first resistor; the first end of the switching tube is electrically connected with the first signal end, the control end of the switching tube is electrically connected with the first end of the first resistor, and the second end of the switching tube is electrically connected with the grounding end; and the second end of the first resistor is electrically connected with the chip pin.
Optionally, the switching tube comprises: a triode; the collector of the triode is used as the first end of the switch tube, the emitter of the triode is used as the second end of the switch tube, and the base of the triode is used as the control end of the switch tube.
Optionally, the first voltage dividing circuit includes: a second resistor; the first end of the second resistor is electrically connected with the second signal end, and the second end of the second resistor is electrically connected with the first signal end.
Optionally, the second voltage dividing circuit includes: a third resistor; the first end of the third resistor is electrically connected with the second signal end, and the second end of the third resistor is electrically connected with the chip pin.
Optionally, the first signal terminal is a first input signal terminal (_ hot plug) of the HDMI interface;
the second signal end is a second input signal end (HDMI _ +5V) of the HDMI interface;
the chip pin is a universal input/output pin of the main chip.
Optionally, the display device is a television.
Accordingly, an embodiment of the present invention provides a motherboard, including: the port detection circuit and the main chip; the port detection circuit includes: a control circuit, a first voltage dividing circuit and a second voltage dividing circuit; wherein,
the control circuit is respectively and electrically connected with the first signal terminal, the chip pin of the main chip and the grounding terminal; the control circuit is used for switching on or off the first signal end and the grounding end under the control of the signal of the chip pin;
the first voltage division circuit is respectively and electrically connected with the first signal end and the second signal end; the first voltage division circuit is used for adjusting the signal of the first signal end according to the signal of the second signal end;
the second voltage division circuit is respectively and electrically connected with the chip pin and the second signal end; the second voltage division circuit is used for adjusting the signal of the chip pin according to the signal of the second signal end;
the main chip is used for detecting or adjusting signals of the chip pins.
Correspondingly, an embodiment of the present invention provides a method for controlling a motherboard, including: a first stage, a second stage, and a third stage;
in the first stage, configuring the chip pin as an input mode;
in the second stage, a high level is loaded on the second signal end, the first voltage division circuit adjusts the signal of the first signal end according to the high level of the second signal end, and the second voltage division circuit adjusts the signal of the chip pin according to the high level of the second signal end;
the main chip changes the low level into the high level according to the signal of the chip pin, and configures the chip pin into an output mode;
the main chip pulls down the level of the signal of the chip pin, and the control circuit cuts off the first signal end and the grounding end under the control of the low level of the chip pin; the first voltage division circuit adjusts the signal of the first signal end according to the high level of the second signal end, so that the first signal end is at the high level;
after first preset time, pulling up the level of a signal of the chip pin, and configuring the chip pin into an input mode;
in the third stage, a low level is loaded on the second signal end, the first voltage divider circuit adjusts the signal of the first signal end according to the low level of the second signal end, and the second voltage divider circuit adjusts the signal of the chip pin according to the low level of the second signal end;
the main chip changes the high level into the low level according to the signal of the chip pin, and configures the chip pin into an output mode;
the main chip pulls up the level of a signal of a chip pin, and the control circuit conducts the first signal end with a grounding end under the control of the high level of the chip pin; the first voltage division circuit adjusts the signal of the first signal end according to the low level of the grounding end to enable the first signal end to be at the low level;
and after the second preset time, configuring the chip pin into an input mode.
Optionally, the loading a high level to the second signal terminal specifically includes:
electrically connecting an external device with the mainboard so as to load a high level on the second signal end through the external device;
and in the second stage, in the first preset time, the external equipment performs data interaction with the control signal in the mainboard.
The invention has the following beneficial effects:
the embodiment of the invention provides a display device, a mainboard and a control method, wherein the mainboard comprises: the port detection circuit and the main chip; the port detection circuit includes: a control circuit, a first voltage dividing circuit and a second voltage dividing circuit; the control circuit can conduct or cut off the first signal end and the grounding end under the control of the signal of the chip pin; the first voltage division circuit can adjust the signal of the first signal end according to the signal of the second signal end; the second voltage division circuit can adjust the signal of the chip pin according to the signal of the second signal end, and the main chip is used for detecting or adjusting the signal of the chip pin. According to the main board and the display device provided by the embodiment of the invention, through the mutual matching of the circuits and the elements, only the chip pin of one main chip can be multiplexed, and the signal of the first signal end is adjusted through the signal of the second signal end. Therefore, when the external equipment is inserted into the mainboard, whether the external equipment is inserted or not can be detected. In addition, only one chip pin of the main chip is multiplexed, so that the number of the chip pins is reduced, and the number of the main chip pins can be reduced or the chip pins originally used for detecting whether the external equipment is inserted can be used as other functions.
Drawings
FIG. 1 is a schematic diagram of a display device according to the related art;
FIG. 2 is a schematic diagram of a motherboard according to the related art;
fig. 3 is a schematic structural diagram of a motherboard according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a specific circuit structure of a motherboard according to an embodiment of the present invention;
fig. 5 is a flowchart of a control method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
As shown in fig. 1, a general display device includes a panel 1, a backlight assembly 2, a main board 3, a power supply board 4, a rear case 5, and a chassis 6. Wherein, the panel 1 is used for presenting pictures for users; the backlight assembly 2 is disposed under the panel 1, and is generally an optical assembly for providing sufficient light source with uniform brightness and distribution to enable the panel 1 to normally display images, the backlight assembly 2 further includes a back plate 20, and the main plate 3 and the power board 4 are disposed on the back plate 20. Wherein the power board is used to supply power to the components in the main board 3. Moreover, a plurality of convex hull structures are usually formed on the back plate 20 by stamping, so that the main board 3 and the power supply board 4 can be fixed on the convex hulls by screws or hooks; the rear shell 5 is covered on the panel 1 and is used for hiding parts of the display device such as the backlight assembly 2, the main board 3, the power panel 4 and the like, so that the attractive effect can be achieved; and a base 6 for supporting the display device.
Referring to fig. 1 and 2, a main chip 40 for controlling the operation of the display device and a receiving port 100 for transmitting signals are disposed on the main board 3. In practice, the receiving port 100 typically extends through the port area 7 of the rear housing 5 to the outside of the rear housing 5. So that it can be electrically connected to an external device through the receiving port 100 to transmit signals.
The embodiment of the invention provides a display device. The display device includes: a main board. In a specific implementation, the display device may be a television. Of course, in practical implementation, the display device may also be: any product or component with a display function, such as a mobile phone, a tablet computer, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.
The mainboard provided by the embodiment of the invention comprises: as shown in fig. 3, the port detection circuit 50 includes: a control circuit 10, a first voltage dividing circuit 20, and a second voltage dividing circuit 30; wherein,
the control circuit 10 is electrically connected to the first signal terminal V1, the chip pin S1 of the main chip 40, and the ground GND, respectively; the control circuit 10 is used for turning on or off the first signal terminal V1 and the ground terminal GND under the control of the signal of the chip pin S1;
the first voltage divider circuit 20 is electrically connected to the first signal terminal V1 and the second signal terminal V2, respectively; the first voltage divider circuit 20 is used for adjusting the signal of the first signal terminal V1 according to the signal of the second signal terminal V2;
the second voltage divider circuit 30 is electrically connected to the chip pin S1 and the second signal terminal V2; the second voltage divider 30 is used for adjusting the signal of the chip pin S1 according to the signal of the second signal terminal V2, and the main chip 40 is used for detecting or adjusting the signal of the chip pin S1.
In a specific implementation, the power board 4 may be disposed on a motherboard, or may not be disposed on the motherboard, and is not limited herein.
The motherboard provided by the embodiment of the invention can multiplex only the chip pin S1 of one main chip 40 through the mutual matching of the modules and the elements, and adjust the signal of the first signal terminal V1 through the signal of the second signal terminal. Therefore, when the external equipment is inserted into the mainboard of the display device, whether the external equipment is inserted or not can be detected. In addition, since only the chip pin S1 of one main chip 40 is multiplexed, the number of the chip pins S1 is reduced, so that the number of the pins of the main chip 40 can be reduced or the chip pin S1 originally used for detecting whether an external device is inserted can be used as another function.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.
As shown in fig. 4, in a specific implementation, in the main board provided in the embodiment of the present invention, the control circuit 10 includes: a switching tube Q and a first resistor R1; the first end of the switching tube Q is electrically connected with the first signal end V1, the control end of the switching tube Q is electrically connected with the first end of the first resistor R1, and the second end of the switching tube Q is electrically connected with the ground GND; the second end of the first resistor R1 is electrically connected to the chip pin S1.
In an implementation, the switching tube Q may include a transistor, as shown in fig. 4, a collector of the transistor serves as a first end of the switching tube Q, an emitter of the transistor serves as a second end of the switching tube Q, and a base of the transistor serves as a control end of the switching tube Q.
In specific implementation, when the base voltage of the triode is greater than 0.7V, the triode is in a conducting state; when the base voltage of the transistor is 0V, the transistor is in an off state, and of course, in specific implementation, specific parameters of the transistor are not limited thereto, and are not limited herein.
Of course, in practical implementation, the switching tube Q may also be a Thin Film Transistor (TFT), a Metal Oxide semiconductor field effect Transistor (MOS), or another device having the same function as the switching tube Q, and is not limited herein.
In a specific implementation, in the main board provided in the embodiment of the present invention, the first voltage dividing circuit 20 includes: a second resistor R2; wherein a first terminal of the second resistor R2 is electrically connected to the second signal terminal V2, and a second terminal of the second resistor R2 is electrically connected to the first signal terminal V1.
In a specific implementation, in the main board provided in the embodiment of the present invention, the second voltage dividing circuit 30 includes: a third resistor R3; the first end of the third resistor R3 is electrically connected to the second signal terminal V2, and the second end of the third resistor R3 is electrically connected to the chip pin S1.
In practical application, the external device has an HDMI output port, and the motherboard has an HDMI receiving port. When the external equipment is inserted into the mainboard, the HDMI output port and the HDMI receiving port are electrically connected with each other. The HDMI _ HOTPLUG output pin of the HDMI output port is electrically connected with the HDMI _ HOTPLUG input pin of the HDMI receiving port, and the HDMI _ +5V output pin of the HDMI output port is electrically connected with the HDMI _ +5V input pin of the HDMI receiving port. The electrical connection of the other pins can be the same as that in the prior art, and is not described herein.
In a specific implementation, in the main board provided in the embodiment of the present invention, the first signal terminal V1 is a first input signal terminal of the HDMI receiving port. Illustratively, the first input signal terminal of the HDMI receiving port may be an HDMI _ hot plug input pin of the HDMI receiving port.
The second signal terminal V2 is a second input signal terminal of the HDMI receiving port. Illustratively, the second input signal terminal of the HDMI receiving port may be an HDMI _ +5V input pin of the HDMI receiving port.
The chip pin S1 is a general-purpose input/output pin of the main chip 40.
In a specific implementation, in the main board provided in the embodiment of the present invention, the materials and the resistances of the first resistor R1, the second resistor R2, and the third resistor R3 should be set according to actual requirements, which is not limited herein.
In a specific implementation, in the main board provided in the embodiment of the present invention, the main Chip 40 is an SOC (system on Chip) Chip, that is, a system on Chip, and a model of the main Chip 40 should be set according to an actual situation, which is not limited herein.
In particular, in the motherboard provided by the embodiment of the present invention, the chip pin S1 may be configured to be in an input mode in which the main chip 40 can detect the level change of the chip pin S1, or in an output mode in which the main chip 40 can control the level change of the main chip 40 pin.
In specific implementation, in the motherboard provided in the embodiment of the present invention, any chip pin S1 that meets the requirements may be selected as long as the chip pin S1 can be configured in the input mode or the output mode as described above.
The specific structure of each module in the motherboard provided by the embodiment of the present invention is merely illustrated, and in the specific implementation, the specific structure of each module is not limited to the structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Based on the same inventive concept, an embodiment of the present invention further provides a method for controlling the display device, as shown in fig. 5, including: a first stage, a second stage, and a third stage; wherein:
s110, in the first stage, the chip pin S1 is configured to be in an input mode.
S120, in the second stage, a high level is loaded to the second signal terminal V2, the first voltage divider circuit 20 adjusts the signal of the first signal terminal V1 according to the high level of the second signal terminal V2, and the second voltage divider circuit 30 adjusts the signal of the chip pin S1 according to the high level of the second signal terminal V2;
s130, the main chip 40 changes the low level into the high level according to the signal of the chip pin S1, and the chip pin S1 is configured to be in an output mode;
s140, the main chip 40 pulls down the level of the signal at the chip pin S1, and the control circuit 10 cuts off the first signal terminal V1 from the ground GND under the control of the low level at the chip pin S1; the first voltage divider circuit 20 adjusts the signal of the first signal terminal V1 according to the high level of the second signal terminal V2 to make the first signal terminal V1 be at a high level;
s150, after the first preset time, the level of the chip pin S1 is pulled high, and the chip pin S1 is configured to be in an input mode.
S160, in the third stage, a low level is applied to the second signal terminal V2, the first voltage divider circuit 20 adjusts the signal of the first signal terminal V1 according to the low level of the second signal terminal V2, and the second voltage divider circuit 30 adjusts the signal of the chip pin S1 according to the low level of the second signal terminal V2;
s170, the main chip 40 changes from high level to low level according to the signal of the chip pin S1, and the chip pin S1 is configured to be in an output mode;
s180, the main chip 40 pulls up the level of the signal at the chip pin S1, and the control circuit 10 makes the first signal terminal V1 conduct with the ground GND under the control of the high level at the chip pin S1; the first voltage divider circuit 20 adjusts the signal of the first signal terminal V1 according to the low level of the ground GND, so that the first signal terminal V1 is at a low level;
and S190, after the second preset time, configuring the chip pin S1 into an input mode.
The following describes the working process of the motherboard provided in the embodiment of the present invention by taking the motherboard shown in fig. 4 as an example and combining the control method of the motherboard shown in fig. 5: specifically, the working process may include:
(1) in the first stage, the chip pin S1 is configured in input mode. Specifically, in the system starting process, the HDMIRx driver is initialized, Extended Display Identification Data (EDID) or high bandwidth digital content protection (HDCP) is loaded, and HDMIRx register information is initialized.
(2) In the second stage, the external device is electrically connected to the motherboard, the external device loads a high level to the HDMI _ +5V input pin of the HDMI receiving port, the second resistor R2 transmits the high level to the HDMI _ hot stick input pin of the HDMI receiving port, and the third resistor R3 transmits the high level to the chip pin S1.
(3) The main chip 40 changes from low to high according to the signal of the chip pin S1, and configures the chip pin S1 to output mode.
(4) The main chip 40 pulls down the level of the chip pin S1, and the first resistor R1 transmits the low level of the chip pin S1 to the base electrode of the triode, so that the triode is cut off; the HDMI _ hot patch input pin of the HDMI reception port changes to high level according to the high level transmitted from the second resistor R2.
(5) And the external equipment detects that the level of an HDMI _ HOTPLUG input pin of the HDMI receiving port is pulled high, starts to initiate EDID/HDCP interaction, and starts to output a signal after the interaction is finished. After the main chip 40 pulls up the chip pin S1 after the first preset time and starts outputting the signal, the main chip 40 configures the chip pin S1 to be in the input mode. The first preset time may be a time length used for initiating the EDID/HDCP interaction and transmitting the completion signal after the interaction is completed. Of course, the present invention includes, but is not limited to, this.
(6) In the third phase, the external device loads a low level to the HDMI _ +5V input pin of the HDMI sink port, the second resistor R2 transmits the low level to the HDMI _ hot plug input pin of the HDMI sink port, and the third resistor R3 transmits the low level to the chip pin S1.
(7) The main chip 40 changes from high to low according to the signal of the chip pin S1, and configures the chip pin S1 to output mode.
(8) The main chip 40 pulls up the level of the signal of the chip pin S1, and the first resistor R1 transmits the high level of the chip pin S1 to the base electrode of the triode, so that the triode is conducted; the HDMI _ hot plug input pin of the HDMI sink port is connected to the ground GND through a transistor, so that the signal level of the HDMI _ hot plug input pin of the HDMI sink port is pulled low.
(9) After a second predetermined time, the main chip 40 configures the chip pin S1 to be in the input mode. The second preset time may be designed and determined according to an actual application environment, and is not limited herein.
In the third stage, the external device loads a low level to the HDMI _ +5V input pin of the HDMI receiving port, which may be disconnecting the external device from the HDMI _ +5V input pin of the HDMI receiving port, or may be powered off, or may be in other possible situations, which is not limited herein.
When the chip pin S1 is in the input mode, the main chip 40 monitors the level change of the chip pin S1 in real time, and when an external device is plugged in or unplugged from the chip pin S1, the level of the HDMI _ +5V input pin of the HDMI input interface changes, and correspondingly, the level of the chip pin S1 also changes. When the level changes, corresponding processing is carried out, specifically, when the level of the chip pin S1 changes from low level to high level, the working process (3) is started; when the level of the chip pin S1 changes from high level to low level, the working process (7) is started; if the level has not changed, the main chip 40 loops and detects nothing.
The embodiment of the invention provides a display device, a mainboard and a control method, wherein the mainboard comprises: the port detection circuit and the main chip; the port detection circuit includes: a control circuit, a first voltage dividing circuit and a second voltage dividing circuit; the control circuit can conduct or cut off the first signal end and the grounding end under the control of the signal of the chip pin; the first voltage division circuit can adjust the signal of the first signal end according to the signal of the second signal end; the second voltage division circuit can adjust the signal of the chip pin according to the signal of the second signal end, and the main chip is used for detecting or adjusting the signal of the chip pin. According to the main board and the display device provided by the embodiment of the invention, through the mutual matching of the circuits and the elements, only the chip pin of one main chip can be multiplexed, and the signal of the first signal end is adjusted through the signal of the second signal end. Therefore, when the external equipment is inserted into the mainboard, whether the external equipment is inserted or not can be detected. In addition, only one chip pin of the main chip is multiplexed, so that the number of the chip pins is reduced, and the number of the main chip pins can be reduced or the chip pins originally used for detecting whether the external equipment is inserted can be used as other functions.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (6)
1. A display device, comprising: a motherboard, wherein the motherboard comprises: the port detection circuit and the main chip; the port detection circuit includes: a control circuit, a first voltage dividing circuit and a second voltage dividing circuit; wherein,
the control circuit is respectively and electrically connected with the first signal terminal, the chip pin of the main chip and the grounding terminal; the control circuit is used for switching on or off the first signal end and the grounding end under the control of the signal of the chip pin;
the first voltage division circuit is respectively and electrically connected with the first signal end and the second signal end; the first voltage division circuit is used for adjusting the signal of the first signal end according to the signal of the second signal end;
the second voltage division circuit is respectively and electrically connected with the chip pin and the second signal end; the second voltage division circuit is used for adjusting the signal of the chip pin according to the signal of the second signal end;
the main chip is used for detecting or adjusting signals of the chip pins;
the control circuit includes: a switching tube and a first resistor; the first end of the switching tube is electrically connected with the first signal end, the control end of the switching tube is electrically connected with the first end of the first resistor, and the second end of the switching tube is electrically connected with the grounding end; the second end of the first resistor is electrically connected with the chip pin;
the main chip is specifically used for configuring the chip pins as an input mode in a first stage;
if the second signal end loads a high level in the second stage, so that the first voltage division circuit adjusts the signal of the first signal end according to the high level of the second signal end, and the second voltage division circuit adjusts the signal of the chip pin according to the high level of the second signal end, the chip pin is configured to be in an output mode according to the fact that the signal of the chip pin is changed from a low level to a high level;
pulling down the level of the signal of the chip pin so that the control circuit can cut off the first signal end from a ground end under the control of the low level of the chip pin, and the first voltage division circuit adjusts the signal of the first signal end according to the high level of the second signal end so that the first signal end is at a high level;
after first preset time, pulling up the level of a signal of the chip pin, and configuring the chip pin into an input mode;
if a low level is loaded on the second signal end in a third stage, so that the first voltage division circuit adjusts the signal of the first signal end according to the low level of the second signal end, and the second voltage division circuit adjusts the signal of the chip pin according to the low level of the second signal end, the signal of the chip pin is changed from a high level to a low level according to the signal of the chip pin, and the chip pin is configured to be in an output mode;
pulling up the level of a signal of a chip pin so that the control circuit can conduct the first signal end with a ground end under the control of the high level of the chip pin, and the first voltage division circuit adjusts the signal of the first signal end according to the low level of the ground end so that the first signal end is at a low level;
and after the second preset time, configuring the chip pin into an input mode.
2. The display device of claim 1, wherein the switching tube comprises: a triode; the collector of the triode is used as the first end of the switch tube, the emitter of the triode is used as the second end of the switch tube, and the base of the triode is used as the control end of the switch tube.
3. The display device according to claim 1, wherein the first voltage dividing circuit includes: a second resistor; the first end of the second resistor is electrically connected with the second signal end, and the second end of the second resistor is electrically connected with the first signal end.
4. The display device according to claim 1, wherein the second voltage division circuit includes: a third resistor; the first end of the third resistor is electrically connected with the second signal end, and the second end of the third resistor is electrically connected with the chip pin.
5. The display device according to claim 1, wherein the first signal terminal is a first input signal terminal of an HDMI interface;
the second signal end is a second input signal end of the HDMI;
the chip pin is a universal input/output pin of the main chip.
6. A display device as claimed in any one of claims 1 to 5, characterized in that the display device is a television set.
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| CN115580549A (en) * | 2022-09-29 | 2023-01-06 | 重庆长安新能源汽车科技有限公司 | UART communication-based plug detection circuit and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN201215981Y (en) * | 2008-06-16 | 2009-04-01 | 青岛海信电器股份有限公司 | Control circuit and television having the control circuit |
| CN103259999A (en) * | 2012-02-20 | 2013-08-21 | 联发科技（新加坡）私人有限公司 | Hot plug detection (HPD) signal output control method and high definition multimedia interface (HDMI) receiving end device and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201215981Y (en) * | 2008-06-16 | 2009-04-01 | 青岛海信电器股份有限公司 | Control circuit and television having the control circuit |
| CN103259999A (en) * | 2012-02-20 | 2013-08-21 | 联发科技（新加坡）私人有限公司 | Hot plug detection (HPD) signal output control method and high definition multimedia interface (HDMI) receiving end device and system |
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