CN110491907A - Array substrate and preparation method thereof, display panel - Google Patents
Array substrate and preparation method thereof, display panel Download PDFInfo
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- CN110491907A CN110491907A CN201910680052.0A CN201910680052A CN110491907A CN 110491907 A CN110491907 A CN 110491907A CN 201910680052 A CN201910680052 A CN 201910680052A CN 110491907 A CN110491907 A CN 110491907A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of array substrate and preparation method thereof, display panel, wherein array substrate includes substrate, inorganic insulation layer and organic insulator.Thin film transistor (TFT) is set in the substrate, and the thin film transistor (TFT) includes the first metal layer, second metal layer, interlayer dielectric layer and third metal layer.The first metal layer is arranged on the substrate.Second metal layer is arranged on the first metal layer, and the second metal layer is source-drain electrode layer.Interlayer dielectric layer is set between the first metal layer and the second metal layer.Third metal layer is arranged in the second metal layer.Inorganic insulation layer is set between the second metal layer and the third metal layer.Organic insulator is arranged on the inorganic insulation layer.When the organic insulator partially or fully removes, the second metal layer, the third metal layer and the inorganic insulation layer constitute capacitor.Whereby, the size of the thin film transistor (TFT) is effectively reduced, pixel density is improved.
Description
Technical field
The present invention relates to field of display technology, espespecially a kind of array substrate and preparation method thereof, display panel.
Background technique
In existing Organic Light Emitting Diode (OLED) flexible array substrate 1, stored with 7 thin film transistor (TFT)s and 1
Capacitor drives a sub-pixel (7T1C circuit).As shown in Figure 1, using first grid layer 11 (capacitor bottom crown), second gate
Pole 12 (capacitor top crown) of layer and gate insulating layer 13 form storage capacitance to drive the sub-pixel.At 12 layers of second grid layer
Upper interlayer dielectric layer 14 (ILD) is used as insulating layer, and redeposited source-drain electrode layer 15 is using as data line (data line)
With power supply line (power line), and then constitutes and 7T1C circuit and control pixel circuit (pixel circuit).In source-drain electrode layer
Coating flat layer 16 on 15, pixel deposition electrode layer 17 is coated organic material as anode on anode on flatness layer 16
As pixel defining layer 18 (pixel defined layer).
In existing 7T1C circuit structure, due to using first grid layer 11, gate insulating layer 13 and second grid layer
12 are used as storage capacitance, make the first grid layer 1 of the thin film transistor (TFT) and capacitor bottom crown same layer and Chong Die placement, cause the
The face that the capacity area that one grid layer 11 and second grid layer 12 are constituted is 25x50 microns (μm) or the thin film transistor (TFT) occupies
Product is larger, therefore is unfavorable for the promotion of pixel density (PPI, pixel per inch), and display quality is caused also can not effectively to be promoted.
In view of this, it is necessary to provide a kind of array substrate and preparation method thereof, display panel, to solve prior art institute
There are the problem of.
Summary of the invention
The main object of the present invention is to provide a kind of array substrate and preparation method thereof, display panel, can effectively contract
The size of the small thin film transistor (TFT), improving pixel density, (i.e. PPI refers to contain how many in the screen size of each inch (inch)
Pixel (pixel)), achieve the effect that promoted display quality.
To reach foregoing purpose of the invention, the present invention provides a kind of array substrate, including substrate, inorganic insulation layer and has
Machine insulating layer.Thin film transistor (TFT) is set in the substrate, and the thin film transistor (TFT) includes the first metal layer, second metal layer, layer
Between dielectric layer and third metal layer.The first metal layer is arranged on the substrate.Second metal layer is arranged in first metal
On layer, the second metal layer is source-drain electrode layer.Interlayer dielectric layer is set to the first metal layer and the second metal layer
Between.Third metal layer is arranged in the second metal layer.Inorganic insulation layer is set to the second metal layer and the third
Between metal layer.Organic insulator is arranged on the inorganic insulation layer, wherein when the organic insulator is partially or fully gone
Except when, the second metal layer, the third metal layer and the inorganic insulation layer constitute capacitor.
In one embodiment of this invention, the first metal layer, the second metal layer and the third metal layer that
This is corresponded to and different layer is arranged.
In one embodiment of this invention, the thin film transistor (TFT) further includes the electricity with second metal layer same layer setting
Pole plate is held, the capacitor bottom crown corresponds to the third metal layer setting, and the third metal layer is capacitor top crown and sets
It sets on the thin film transistor (TFT).
In one embodiment of this invention, further include setting barrier layer on the substrate and be arranged in the barrier layer
Buffer layer, the thin film transistor (TFT) includes the active layer being stacked, gate insulating layer, the first metal layer and the layer
Between dielectric layer, wherein the active layer is arranged on the buffer layer, the gate insulating layer is arranged in the active layer and institute
It states between the first metal layer, the third metal layer is then arranged on the inorganic insulation layer.
In one embodiment of this invention, the inorganic insulation layer is gate insulating layer, and the organic insulator is first
Flatness layer is additionally provided with one second flatness layer on first flatness layer, the pixel deposition electrode on second flatness layer
Layer and pixel confining layer, the pixel confining layer expose the pixel electrode layer to the open air.
It in one embodiment of this invention, further include the first transistor, second transistor, third transistor, the 4th crystal
Pipe, the 5th transistor, the 6th transistor, the 7th transistor and the storage capacitance, the first transistor, second crystal
Pipe, the third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor
Same layer is laid, wherein the thin film transistor (TFT) is the first transistor, the capacitor is set to above the first transistor.
Furthermore the present invention also provides a kind of production methods of array substrate, comprising the following steps:
S10, substrate is provided, forms thin film transistor (TFT) on the substrate, the thin film transistor (TFT) includes:
S101, the first metal layer is formed on the substrate, the first metal layer is grid layer；
S102, second metal layer is formed above the first metal layer, the second metal layer is source-drain electrode layer；
S103, interlayer dielectric layer is formed between the first metal layer and the second metal layer；And S104, described
Third metal layer is formed above second metal layer；
S20, inorganic insulation layer is formed between the second metal layer and the third metal layer；And
S30, organic insulator is formed on the inorganic insulation layer, wherein when the organic insulator is partially or fully gone
Except when, the second metal layer, the third metal layer and the inorganic insulation layer can be constituted.
It in one embodiment of this invention, in step s 102, further include the electricity formed with the second metal layer same layer
Pole plate is held, the third metal layer is capacitor top crown and is formed on the thin film transistor (TFT), in step slo, is also wrapped
The barrier layer being formed on the substrate and the buffer layer for being formed in the barrier layer are included, the thin film transistor (TFT) includes sequentially shape
At active layer, gate insulating layer, the first metal layer and the interlayer dielectric layer, wherein the active layer be formed in it is described
On buffer layer, the gate insulating layer is formed between the active layer and the first metal layer, the third metal layer shape
At on the inorganic insulation layer.
In one embodiment of this invention, the organic insulator completely or can be removed partly by exposure, to expose to the open air
The third metal layer makes the organic insulator shape narrow wide cup-shaped under after the organic insulator exposure, described
One second flatness layer is also formed on organic insulator, pixel deposition electrode layer and pixel limit on second flatness layer
Layer, the pixel confining layer expose the pixel electrode layer to the open air.
The present invention also provides a kind of display panels, including array substrate described in embodiment as above.
The present invention also has effects that following, and inorganic insulation is arranged between the second metal layer and the third metal layer
Layer (gate insulating layer) and organic insulator (the first flatness layer) two kinds of film layers reduce data signal line (date signal
Line) the capacitive coupling (capacitive coupling) between power supply (Vdd) signal wire (power signal Line)
And the delay of data line signal transmission, to improve display effect.In addition, the second metal layer is as the described of capacitor bottom crown
Organic insulator leaves inorganic insulation layer, to form biggish storage capacitance, reaches increase dielectric coefficient by exposure, increases
Add storage capacitance, and whole display effect can be improved.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the cross-sectional view of existing array substrate；
Fig. 2 is the cross-sectional view of array substrate of the present invention and its display panel；
Fig. 3 is the block flow diagram of the production method of array substrate of the present invention；
Fig. 4 is the topology layout plan view of array substrate of the present invention and its display panel；And
Fig. 5 is the circuit diagram of array substrate of the present invention and its display panel.
Specific embodiment
Refer to that " embodiment " means that a particular feature, structure, or characteristic described in conjunction with the embodiments can in a specific embodiment
To be included at least one embodiment of the present invention.The identical term that different location in the description occurs not necessarily by
It is limited to identical embodiment, and should be understood as mutually being independent with other embodiments or alternative embodiment.At this
It invents under the enlightenment of technical solution disclosed in the embodiment provided, it should be appreciated by those skilled in the art that described in the invention
Embodiment can have other meet the technical solution of present inventive concept combine or variation.
Referring to figure 2., shown in Fig. 4 and Fig. 5, the present invention provides a kind of array substrate, including substrate 3, inorganic insulation layer 42
And organic insulator 41.Thin film transistor (TFT) M1 is set in the substrate 3, wherein the thin film transistor (TFT) M1 includes the first metal layer
21, second metal layer 22, interlayer dielectric layer 24 and third metal layer 23.The substrate 2 is preferably glass or polyimides
(Polyimide, PI), and apply the higher low temperature polycrystalline silicon of mobility (Low Temperature Poly-silicon,
LTPS) sub-pixel for emitting light is driven in the thin film transistor (TFT) (TFT) of type.
The first metal layer 21 is arranged in the substrate 3 of the thin film transistor (TFT) M1, and the first metal layer 21 is as scanning
Drive the grid layer of line (scan driving line) and the driving thin film transistor (TFT) M1.Second metal layer 22 is arranged in institute
It states on the first metal layer 21, the second metal layer 22 is as data signal line (date signal line), capacitor and reset
Signal wire (reset signal line) and source-drain electrode layer, wherein the first metal layer 21 and the second metal layer
Interlayer dielectric layer (ILD) 24 is provided between 22.
Third metal layer 23 is arranged in the second metal layer 22, and the third metal layer 23 is believed as power supply (Vdd)
Number line (power signal Line) and capacitor top crown, between the second metal layer 22 and the third metal layer 23
It is provided with inorganic insulation layer 42.Organic insulator 41 is arranged on the inorganic insulation layer 42, wherein when the organic insulator
41 when partially or fully removing, and the second metal layer 22, the third metal layer 23 and the inorganic insulation layer 42 constitute electricity
Hold 5.
As shown in Figures 2 and 4, the first metal layer 21, the second metal layer 22 and the third metal layer 23 that
This is corresponded to and different layer is arranged.The thin film transistor (TFT) M1 further includes the capacitor bottom crown with 22 same layer of second metal layer setting
27, the corresponding third metal layer 23 of the capacitor bottom crown 27 is arranged.The third metal layer 23 is capacitor top crown and sets
It sets on the thin film transistor (TFT) M1.
It in an embodiment as illustrated in figure 2, further include the barrier layer 31 being arranged in the substrate 3 and setting in the resistance
The buffer layer 32 of interlayer 31.Signified barrier layer is preferably the inorganic barrier layer (multi-barrier of multilayer lamination structure herein
structure).The thin film transistor (TFT) M1 includes the active layer 25, gate insulating layer 26, the first metal layer being stacked
21 (i.e. gate electrodes) and the interlayer dielectric layer 24.The active layer 25 is arranged on the buffer layer 32, the gate insulator
Layer 26 is arranged between the active layer 25 and the gate electrode 21, and the third metal layer 23 is then arranged in the inorganic insulation
Layer upper 42.
Specifically, the inorganic insulation layer 42 is arranged on the interlayer dielectric layer 24, and preferably gate insulating layer.
The organic insulator 41 is, for example, the first flatness layer.Therefore between the second metal layer 22 and the third metal layer 23
Inorganic insulation layer 42 (gate insulating layer) and organic insulator 41 (the first flatness layer) two kinds of film layers are set, data-signal can be reduced
Capacitive coupling between line (date signal line) and power supply (Vdd) signal wire (power signal Line)
The delay of (capacitive coupling) and data line signal transmission, to improve display effect.
The organic insulator 41 is by exposure or other suitable techniques can completely or part removes, to expose to the open air described
Third metal layer 23.After the organic insulator 41 exposes, the shape of the organic insulator 41 narrow wide cup-shaped under.Institute
It is inorganic between the third metal layer 23 (capacitor top crown) and capacitor bottom crown 27 after organic insulator 41 is stated by exposure
Insulating layer 42 forms biggish storage capacitance, reaches increase dielectric coefficient, increases storage capacitance, and whole display effect can be improved
Fruit.
In addition, being additionally provided with one second flatness layer 33 on the organic insulator 41 (the first flatness layer).Described second
Pixel deposition electrode layer 34 is used as anode and pixel confining layer 35 on flatness layer 33, wherein the pixel confining layer 35 can expose
Reveal the pixel electrode layer 34, and is shone by the pixel electrode layer 34.
It further include the first transistor M1, second transistor M2, third transistor M3, the 4th please with reference to Fig. 4 and Fig. 5
Transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7 and the storage capacitance Cst.The first crystal
It is pipe M1, the second transistor M2, the third transistor M3, the 4th transistor M4, the 5th transistor M5, described
6th transistor M6, the 7th transistor M7 same layer are laid, wherein the thin film transistor (TFT) M1 is the first transistor, institute
Capacitor Cst is stated to be set to above the first transistor M1.
Capacitor regions are collectively formed in the capacitor bottom crown 27 and the third metal layer 23 (capacitor top crown), by institute
State the first metal layer 21 of capacitor 5 and the unshared the first transistor M1, therefore the area of the first transistor M1/
Size can reduce, and the leakage current of the gate electrode of driving thin film transistor (TFT) M1 is effectively reduced, and then reduce 5 face of storage capacitance
Product, so that OLED flexible array substrate pixel density with higher (PPI), reaches the display quality for promoting display panel.
Please with reference to described in Fig. 3, the present invention also provides a kind of production methods of array substrate, comprising the following steps:
S10, substrate 3 is provided, forms thin film transistor (TFT) M1 in the substrate 3, the thin film transistor (TFT) M1 includes:
S101, the first metal layer 21 is formed in the substrate 3, the first metal layer 21 is grid layer；
S102, second metal layer 22 is formed above the first metal layer 21, the second metal layer 22 is source and drain electricity
Pole layer；
S103, interlayer dielectric layer 24 is formed between the first metal layer 21 and the second metal layer 22；And
S104, third metal layer 23 is formed above the second metal layer 22；
S20, inorganic insulation layer 42 is formed between the second metal layer 22 and the third metal layer 23；And
S30, organic insulator 41 is formed on the inorganic insulation layer 42, wherein when 41 part of the organic insulator or
When completely removing, the second metal layer 22, the third metal layer 23 and the inorganic insulation layer 42 can constitute capacitor.
It in step s 102, further include the capacitor bottom crown 27 formed with 22 same layer of second metal layer.The third
Metal layer 23 is capacitor top crown and is formed on the thin film transistor (TFT) M1.It in step slo, further include being formed in the base
Barrier layer 31 on bottom 3 and the buffer layer 32 for being formed in the barrier layer 31.
The thin film transistor (TFT) M1 includes the active layer 25, gate insulating layer 26, the first metal layer 21 sequentially formed
With the interlayer dielectric layer 24.The active layer 25 is formed on the buffer layer 32, and the gate insulating layer 26 is formed in institute
It states between active layer 25 and the first metal layer 21, the third metal layer 23 is formed on the inorganic insulation layer 42.
In the present embodiment, the inorganic insulation layer 42 is preferably gate insulating layer, and the organic insulator 41 is then the
One flatness layer.The organic insulator 41 can completely by exposure or part removes, to expose the third metal layer 23, institute to the open air
After organic insulator 41 is stated by exposure, make 41 shape of organic insulator narrow wide cup-shaped under.In addition, described organic
One second flatness layer 33 is also formed on insulating layer 41, pixel deposition electrode layer 34 and pixel on second flatness layer 33
Confining layers 35, the pixel confining layer 35 expose the pixel electrode layer 34 to the open air.
The present invention also provides a kind of display panels, including array substrate described in embodiment as above.Signified display herein
Panel is preferably the display devices such as mobile phone, tablet computer, TV.Dependency structure in relation to display panel please join previous embodiment institute
It states, then this is repeated no more.
In conclusion although the present invention is described in conjunction with its specific embodiment, it should be understood that many substitutions are repaired
Changing and changing will be apparent those skilled in the art.Therefore, it is intended to want comprising falling into appended right
Ask all substitutions, modification and the variation in the range of book.
Claims (10)
1. a kind of array substrate, comprising:
Thin film transistor (TFT) is arranged in the substrate, wherein the thin film transistor (TFT) includes: in substrate
The first metal layer, on the substrate, the first metal layer is grid layer for setting；
Second metal layer is arranged on the first metal layer, and the second metal layer is source-drain electrode layer；
Interlayer dielectric layer is set between the first metal layer and the second metal layer；
Third metal layer is arranged in the second metal layer；
Inorganic insulation layer is set between the second metal layer and the third metal layer；And
Organic insulator is arranged on the inorganic insulation layer, wherein when the organic insulator partially or fully removes, institute
It states second metal layer, the third metal layer and the inorganic insulation layer and constitutes capacitor.
2. array substrate as described in claim 1, which is characterized in that the first metal layer, the second metal layer and institute
State third metal layer correspond to each other and different layer be arranged.
3. array substrate as described in claim 1, which is characterized in that the thin film transistor (TFT) further includes and second metal
The capacitor bottom crown of layer same layer setting, the capacitor bottom crown correspond to the third metal layer setting, and the third metal layer is
Capacitor top crown and be arranged on the thin film transistor (TFT).
4. array substrate as described in claim 1, which is characterized in that further include setting barrier layer on the substrate and set
The buffer layer in the barrier layer is set, the thin film transistor (TFT) includes the active layer being stacked, gate insulating layer, described first
Metal layer and the interlayer dielectric layer, wherein the active layer is arranged on the buffer layer, the gate insulating layer setting exists
Between the active layer and the first metal layer, the third metal layer is arranged on the inorganic insulation layer.
5. array substrate as claimed in claim 4, which is characterized in that the inorganic insulation layer is gate insulating layer, described to have
Machine insulating layer is the first flatness layer, one second flatness layer is additionally provided on first flatness layer, in second flatness layer
Upper pixel deposition electrode layer and pixel confining layer, the pixel confining layer expose the pixel electrode layer to the open air.
6. array substrate as described in claim 1, which is characterized in that further include the first transistor, second transistor, third crystalline substance
Body pipe, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor and the storage capacitance, the first crystal
Pipe, the second transistor, the third transistor, the 4th transistor, the 5th transistor, the 6th crystal
Pipe, the 7th transistor same layer are laid, wherein the thin film transistor (TFT) is the first transistor, the capacitor is set to institute
It states above the first transistor.
7. a kind of production method of array substrate, comprising the following steps:
S10, substrate is provided, forms thin film transistor (TFT) on the substrate, the thin film transistor (TFT) includes:
S101, the first metal layer is formed on the substrate, the first metal layer is grid layer；
S102, second metal layer is formed above the first metal layer, the second metal layer is source-drain electrode layer；
S103, interlayer dielectric layer is formed between the first metal layer and the second metal layer；And
S104, third metal layer is formed above the second metal layer；
S20, inorganic insulation layer is formed between the second metal layer and the third metal layer；And
S30, organic insulator is formed on the inorganic insulation layer, wherein when the organic insulator partially or fully removes
When, the second metal layer, the third metal layer and the inorganic insulation layer can constitute capacitor.
8. the production method of array substrate as claimed in claim 7, which is characterized in that in step s 102, further include and institute
The capacitor bottom crown of second metal layer same layer formation is stated, the third metal layer is capacitor top crown and is formed in the film crystalline substance
It further include the barrier layer being formed on the substrate and the buffer layer for being formed in the barrier layer in step slo on body pipe,
The thin film transistor (TFT) includes the active layer sequentially formed, gate insulating layer, the first metal layer and the interlayer dielectric layer,
Wherein the active layer is formed on the buffer layer, and the gate insulating layer is formed in the active layer and first metal
Between layer, the third metal layer is formed on the inorganic insulation layer.
9. the production method of array substrate as claimed in claim 8, which is characterized in that the organic insulator passes through exposure meeting
Completely or part removes, to expose the third metal layer to the open air, after the organic insulator exposure, makes the organic insulator shape
Shape narrow wide cup-shaped under is also formed with one second flatness layer on the organic insulator, sinks on second flatness layer
Product pixel electrode layer and pixel confining layer, the pixel confining layer expose the pixel electrode layer to the open air.
10. a kind of display panel, including such as array substrate described in any one of claims 1 to 6.
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| CN201910680052.0A CN110491907A (en) | 2019-07-26 | 2019-07-26 | Array substrate and preparation method thereof, display panel |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111627386A (en) * | 2020-06-10 | 2020-09-04 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and display device |
| CN112180629A (en) * | 2020-10-16 | 2021-01-05 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN112838051A (en) * | 2021-01-05 | 2021-05-25 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of driving circuit board |
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| CN109166896A (en) * | 2018-09-03 | 2019-01-08 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN109378326A (en) * | 2018-09-21 | 2019-02-22 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN109860259A (en) * | 2019-02-28 | 2019-06-07 | 武汉华星光电半导体显示技术有限公司 | A kind of OLED array and OLED display |
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| CN109166896A (en) * | 2018-09-03 | 2019-01-08 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN109378326A (en) * | 2018-09-21 | 2019-02-22 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN109860259A (en) * | 2019-02-28 | 2019-06-07 | 武汉华星光电半导体显示技术有限公司 | A kind of OLED array and OLED display |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111627386A (en) * | 2020-06-10 | 2020-09-04 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and display device |
| CN112180629A (en) * | 2020-10-16 | 2021-01-05 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN112838051A (en) * | 2021-01-05 | 2021-05-25 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of driving circuit board |
| CN112838051B (en) * | 2021-01-05 | 2024-04-05 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of driving circuit board |
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