CN110400591B - Erasing method for flash memory - Google Patents
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- CN110400591B CN110400591B CN201810372672.3A CN201810372672A CN110400591B CN 110400591 B CN110400591 B CN 110400591B CN 201810372672 A CN201810372672 A CN 201810372672A CN 110400591 B CN110400591 B CN 110400591B
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- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000012795 verification Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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Abstract
An exemplary erase method for a flash memory is as follows, wherein the flash memory comprises at least one memory block, and the memory block is divided into a plurality of memory sectors. Verifying whether a memory block or a memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enabling signal, wherein the sector enabling signal is determined according to whether the memory block has at least one over-erased transistor memory cell. And if the memory block or the memory segment corresponding to the address has the transistor memory cells with insufficient erasing, erasing the transistor memory cells of the memory block or the memory segment according to the segment enabling signal.
Description
Technical Field
The present invention relates to a flash memory, and more particularly, to an erasing method for a flash memory.
Background
Flash memory includes a plurality of individual Metal Oxide Semiconductor (MOS) field effect transistor memory cells, each transistor memory cell including a source, a drain, a floating gate, and a control gate. The electrodes of the transistor memory cells can be applied with various voltages to program (i.e., write) the transistor memory cells to binary 1's or 0's, erase all the transistor memory cells as a memory block, read the transistor memory cells, verify that the transistor memory cells are erased, or verify that the transistor memory cells are not over-erased.
The adverse effects of the leakage current of an over-erased transistor memory cell are described below. In a typical flash memory, the drains of a large number of transistor memory cells, for example 512 transistor memory cells, are connected to each bit line. If a large number of transistor memory cells on a bit line are drawing background leakage current, the total leakage current on the bit line may exceed the cell read current. This makes the state of any transistor memory cell on the bit line unreadable and, therefore, renders the flash memory inoperable.
Referring to FIG. 1, FIG. 1 is a flowchart illustrating a conventional erasing method. The flash memory comprises a memory module and a memory management device electrically connected with the memory module, wherein the memory module is provided with a plurality of memory banks (memory banks), each memory bank comprises a plurality of memory blocks, and the memory management device is used for executing an erasing method on the memory blocks of the memory banks.
In step S11, verify and pre-write operations are performed on all transistor memory cells of the memory module by the memory management device. Next, in step S12, the memory management device verifies and erases all the transistor memory cells as a memory block, that is, the unit of erasing is a memory block. Finally, in order to avoid the flash memory from being disabled due to the leakage current of the over-erased transistor memory cell, in step S13, the memory management device verifies all of the plurality of transistor memory cells of the memory module, and performs the over-erase correction on the over-erased transistor memory cell of the memory module when the verification result indicates that at least one over-erased transistor memory cell exists in the memory block.
In detail, step S12 includes steps S121 to S124. In step S121, the memory management device verifies the transistor memory cells of the memory block corresponding to an address. Then, in step S122, if the verification result shows that at least one transistor memory cell of the memory block is under-erased (i.e., the verification result shows that the erase verification of the memory block fails), the memory management device will execute step S124; otherwise, the storage management device performs step S123.
Next, since at least one transistor memory cell of the memory block is under-erased, in step S124, the memory management device injects an erase shot into the transistor memory cell of the memory block (i.e., erases the transistor memory cell of the memory block) to change the threshold voltage of the transistor memory cell of the memory block (i.e., erase the transistor memory cell of the memory block). Then, step S121 is executed again. Then, if it is determined in step S122 that the transistor memory cells of the memory block are erased, step S123 is performed. In step S123, the memory management device checks whether the address is the maximum address (i.e. the transistor memory cells of all memory blocks are erased). If the address is not the maximum address, step S125 is executed; otherwise, step S13 is executed. In step S125, the storage management device adds an increment to the address, and then step S121 is executed.
It is noted that when the bit line of the transistor memory cell with slower erase has larger bit line leakage current, the erase threshold voltage will become higher after the bit line leakage current is recovered in step S13. At the same time, more overerased transistor memory cells will suffer from long overerasing correction times.
Unlike the above-described method of verifying and erasing all the transistor memory cells in a memory block, another known erase method can erase only the transistor memory cells having insufficient erase among the transistor memory cells of a memory sector for each memory block. Referring to FIG. 2, FIG. 2 is a schematic diagram of another conventional erase method performed on a memory block. The memory block 2 is divided into several memory segments G1-G15, and a plurality of flag registers are used for the memory segments G1-G15 respectively to record whether all the transistor memory cells in the memory segments G1-G15 are erased.
As shown in FIG. 2, all of the memory segments G1 through G15 initially have transistor memory cells with under-erase, and thus erase shots are injected into the transistor memory cells of the memory segments G1 through G15 (i.e., the transistor memory cells of the memory block 2 are erased). Then, all the transistor memory cells 2 of the memory block 2, for example, the transistor memory cells of the memory sector G3 without under-erase are verified, and the flag register corresponding to the memory sector G3 records the status as erased status. Thus, erase shots are injected into the transistor memory cells of the memory segments G1, G2, G4 through G15 (i.e., the transistor memory cells of the memory segments G1, G2, G4 through G15 are erased).
Next, all the transistor memory cells of the memory block 2, such as the memory segments G1, G3, G4 through G15, are verified again without under-erase transistor memory cells, and the flag registers corresponding to the memory segments G1, G3, G4 through G15 record their states as erased states. Therefore, erase shots are injected into the transistor memory cells of the memory segment G2 (i.e., the transistor memory cells of the memory segment G2 are erased). This known erasure method requires multiple additional flag registers and consumes more erase verification time.
Disclosure of Invention
An object of the present disclosure is to provide an erasing method for a flash memory, which does not require additional flag registers and does not consume more erase verification time.
Another objective of the present disclosure is to provide a flash memory for performing the above erasing method.
To achieve at least the above objects, the present disclosure provides an erasing method for a flash memory. The flash memory comprises at least one memory block, and the memory block is divided into a plurality of memory sectors. The erasing method is exemplified as follows. Verifying whether a memory block or a memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enabling signal, wherein the sector enabling signal is determined according to whether the memory block has at least one over-erased transistor memory cell. And if the memory block or the memory segment corresponding to the address has the transistor memory cells with insufficient erasing, erasing the transistor memory cells of the memory block or the memory segment according to the segment enabling signal.
To achieve at least the above objects, the present disclosure provides a flash memory, comprising: a storage module and a storage management device. The memory module comprises at least one memory block, and the memory block is divided into a plurality of memory sections. The storage management device is electrically connected to the storage module. The memory management device verifies whether a memory block or a memory segment corresponding to an address has at least one transistor memory cell with insufficient erase according to a segment enable signal, wherein the segment enable signal is determined according to whether the memory block has at least one transistor memory cell with excessive erase. If the memory block or the memory sector corresponding to the address has the transistor memory cells with insufficient erasing, the memory management device erases the transistor memory cells of the memory block or the memory sector according to the sector enabling signal.
In one embodiment of the present disclosure, if the sector enable signal is set to the active state (asserted) and the memory sector corresponding to the address has under-erased transistor memory cells, the transistor memory cells of the memory sector will be injected into the erase shot at least once until the memory sector has no under-erased transistor memory cells.
In one embodiment of the present disclosure, if a memory sector does not have under-erased transistor memory cells, the address is incremented, and then if another memory sector corresponding to the address has at least one under-erased transistor memory cell, the transistor memory cells of the other memory sector are injection-erase-fired at least once until the other memory sector does not have under-erased transistor memory cells.
In one embodiment of the present disclosure, when the address reaches the maximum address, it is verified whether the memory block has the transistor memory cells that are over-erased, and if there are transistor memory cells that are over-erased in the memory block, the transistor memory cells that are over-erased are corrected for over-erase.
In one embodiment of the present disclosure, a pre-programming operation is performed on the transistor memory cells of the memory block before verifying and erasing the transistor memory cells of the memory block.
In one embodiment of the present disclosure, the segment enable signal is initially set to an inactive state (de-asserted), and if the memory block corresponding to the address has under-erased transistor memory cells, the transistor memory cells of the memory block will be injection-erased at least once until the memory block is verified to have over-erased transistor memory cells.
In one embodiment of the present disclosure, when a memory block is verified to have transistor memory cells with over-erase, an over-erased correction shot is injected into the over-erased transistor memory cells, and the segment enable signal is set to the active state.
In summary, the erasing method provided by the embodiment of the invention does not need to use additional flag registers to record the status of the memory sectors, and does not need to consume more erasing verification time.
Drawings
FIG. 1 is a flowchart illustrating a conventional erasing method.
FIG. 2 is a diagram of another conventional erase method performed on a memory block.
FIG. 3 is a flowchart of an erasing method for a flash memory according to an embodiment of the present disclosure.
Detailed Description
For a fuller understanding of the objects, features and advantages of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings.
In the verification and erase steps, after erase shot is injected into all transistor memory cells of the memory block (i.e., all transistor memory cells of the memory block are erased), the provided erase method verifies whether the memory block has at least one over-erased transistor memory cell. When the memory block has at least one transistor memory cell with over-erasing, the provided erasing method injects the erasing to a plurality of transistor memory cells of the memory segment (i.e. all transistor memory cells of the memory segment are erased), and then, the provided erasing method verifies whether all transistor memory cells of the memory segment are erased. The provided erase method erases a plurality of transistor memory cells of a memory sector at least once until all transistor memory cells of the memory sector are erased. Then, the provided erasing method erases the plurality of transistor memory cells of another memory segment in the same memory block at least once until the plurality of transistor memory cells of the another memory segment are erased. When all transistor memory cells in this other memory sector in the memory block are erased, a similar erase scheme will be performed for yet another memory block. Therefore, the provided erasing method does not need additional multiple mark registers to record the state of the memory sector, and does not need to consume more erasing verification time.
Referring to fig. 3, fig. 3 is a flowchart illustrating an erasing method for a flash memory according to an embodiment of the disclosure. The flash memory (not shown in the drawings) includes a memory module and a memory management device electrically connected to the memory module. The memory module comprises a plurality of memory groups, each memory group comprises a plurality of memory blocks, and each memory block is divided into a plurality of memory sections. For example, a memory block has 64 kbytes (i.e., 64 x 8K bits), and a memory segment has 4 kbytes (i.e., 4 x 8K bits). However, the present disclosure is not limited by the above examples.
In step S31, the memory management device performs verify and pre-write operations on the transistor memory cells of the memory module. Then, in step S32 (i.e., the erasing and verifying step), the memory management device verifies and erases the transistor memory cells of the memory module. It should be noted that in step S32, the erasing method provided herein can erase the transistor memory cells of the memory block or the memory segment based on whether the over-erased correction shot is injected into the transistor memory cells of the memory block (i.e., whether the memory block has at least one over-erased transistor memory cell). Finally, in order to avoid the flash memory from being disabled due to the leakage current of the over-erased transistor memory cell, the memory management device verifies all the transistor memory cells of the memory module and corrects the over-erased transistor memory cells of the memory module in step S33.
In detail, step S32 includes steps S321 to S329. In step S321, the memory management device verifies whether the transistor memory cells of the memory block or the memory segment corresponding to an address are erased to generate a verification result. When the segment enable signal SEC _ EN corresponding to the memory block is set to the active state, the transistor memory cells of the memory segment are verified; and verifying the transistor memory cells of the memory block when the segment enable signal SEC _ EN corresponding to the memory block is set to be in an inactive state, wherein the segment enable signal SEC _ EN corresponding to the memory block is determined according to whether the memory block has at least one transistor memory cell which is over-erased. If the memory block or the memory segment has at least one transistor memory cell with insufficient erasing, the memory management device determines that the verification result is failure; and if the memory block or the memory sector does not have at least one transistor memory cell with insufficient erasing, the memory management device determines that the verification result is passed.
In step S322, the storage management device checks whether the verification result is a failure or a pass. If the verification result is failure, step S323 will be executed; otherwise, step S328 is performed. In step S323, the memory management device injects the erase shot into the plurality of transistor memory cells of the memory block or the memory segment according to the segment enable signal SEC _ EN corresponding to the memory block. If the segment enable signal SEC _ EN corresponding to the memory block is set to be in an active state, the memory management device injects the erasing trigger into a plurality of transistor memory cells of the memory block; otherwise, the memory management device erases the plurality of transistor memory cells injected into the memory sector.
In step S324, the memory management device checks whether the segment enable signal SEC _ EN corresponding to the memory block is set to the active state. If the segment enable signal SEC _ EN corresponding to the block is set to the active state, step S321 is executed; otherwise, step S325 is executed. In step S325, the memory management device verifies whether the memory block has at least one transistor memory cell that is over-erased, and corrects the transistor memory cell of the memory block for over-erase when the memory block has at least one transistor memory cell that is over-erased.
Next, in step S326, the memory management device checks whether an over-erase correction is performed (i.e., whether the memory block has at least one over-erased transistor memory cell or whether an over-erased correction (OEC) triggers an over-erased transistor memory cell injected into the memory block. if an over-erase correction is performed, step S327 is performed, otherwise, step S321 is performed. in step S327, the memory management device sets the segment enable signal SEC _ EN corresponding to the memory block to an active state. in step S328, the memory management device checks whether the address reaches a maximum address. in step S329, the memory management device increments the address by an increment corresponding to the size of the memory segment.
Initially, when the provided erase method first erases the transistor memory cells of the memory block, the segment enable signal SEC _ EN corresponding to the memory block is set to an inactive state. For example, in step S321, a plurality of transistor memory cells of the memory block are verified; the memory block has transistor memory cells with under-erase, so in step S323, the plurality of transistor memory cells injected into the memory block are erase-programmed. Next, since the segment enable signal SEC _ EN corresponding to the memory block is set to the inactive state, it is checked whether the memory block has at least one transistor memory cell with over-erase in step S325. Generally, after the provided erase method erases the transistor memory cells of the memory block one or more times, there are transistor memory cells that are over-erased in the memory block, so that the segment enable signal SEC _ EN corresponding to the memory block is set to an active state in step S327.
Then, in step S321, the transistor memory cells of the memory sector corresponding to the address are verified, and in step S323, the erase shot is injected into the transistor memory cells of the memory sector corresponding to the address until the transistor memory cells of the memory sector are erased, and steps S321 and S323 are repeatedly performed. If all the transistor memory cells of the memory sector corresponding to the address are erased, the address is incremented in step S329, the transistor memory cells of another memory sector corresponding to the address in the same memory block are verified in step S321 and the erase is injected into the transistor memory cells of another memory sector corresponding to the address in the same memory block in step S323, and steps S321 and S323 are repeatedly performed until the transistor memory cells of the another memory sector are erased. Therefore, after the transistor memory cells of all the memory sectors in the memory block are erased, the provided erasing method will perform a similar erasing scheme on the next memory block.
In summary, in the verification and erase steps, according to an embodiment of the present disclosure, an erase method for a flash memory is provided, in which a memory sector or a transistor memory cell of a memory block is erased according to whether the memory block has at least one transistor memory cell that is over-erased, so that the erase method does not need an additional plurality of flag registers to record the state of the memory sector. In addition, compared to the conventional method of fig. 2 in which erase shot is injected to erase and verify the entire memory block (e.g., the unit of verification is 8 or more bits), the erase method in the present disclosure performs erase shot injection to perform OEC verification on bit lines of the entire memory block (e.g., the unit of verification is 8 or more bits), so that the erase method of the present disclosure can save more time. Furthermore, the slower and faster erased transistor memory cells in the memory sector have a low probability of being connected to the same bit line, and the erase method of the present disclosure achieves a small erase threshold voltage distribution, as obtained by the known method of fig. 2, so that the problem of the over-erased transistor memory cells masking the under-erased transistor memory cells can be avoided, and the over-erased transistor memory cells do not suffer from long over-erased correction time (over-erased correction time) and post-over-erased correction time (post-over-erased correction time).
While the invention has been described in terms of preferred embodiments, it will be understood by those skilled in the art that the examples are intended in a descriptive sense only and not for purposes of limitation. It should be noted that equivalent variations and substitutions to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the protection scope of the present invention should be determined by the claims.
[ notation ] to show
S11-S13
S121 to S125
G1-G15 storage sector
S31-S33
S321 to S329
Claims (8)
1. An erasing method for a flash memory, the flash memory including at least one memory block, the memory block being divided into a plurality of memory sectors, the erasing method comprising:
verifying whether the memory block or the memory segment corresponding to an address has at least one under-erased transistor memory cell according to a segment enable signal, wherein the segment enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell; and
and if the memory block or the memory segment corresponding to the address has the transistor memory cells with the undererasure, erasing a plurality of transistor memory cells of the memory block or the memory segment according to the segment enabling signal.
2. The erase method of claim 1, wherein if the sector enable signal is set to an active state (asserted) and the memory sector corresponding to the address has the under-erased transistor memory cells, the transistor memory cells of the memory sector will be injected into an erase shot (erasing shot) at least once until the memory sector does not have the under-erased transistor memory cells.
3. The erase method of claim 2, wherein if the memory sector does not have the under-erased transistor memory cells, the address is incremented, and then if another memory sector corresponding to the address has at least one under-erased transistor memory cell, the plurality of transistor memory cells of the another memory sector are injected into the erase at least once until the another memory sector does not have the under-erased transistor memory cells.
4. The erasing method of claim 3, further comprising:
and when the address reaches the maximum address, verifying whether the storage block has the transistor memory cell which is over-erased, and if the transistor memory cell which is over-erased exists in the storage block, correcting the over-erased transistor memory cell.
5. The erasing method of claim 1, further comprising:
before verifying and erasing the transistor memory cells of the memory block, a pre-programming operation is performed on the transistor memory cells of the memory block.
6. The erase method of claim 1, wherein the sector enable signal is initially set to an inactive state (de-asserted) and if the memory block corresponding to the address has the under-erased transistor memory cells, the transistor memory cells of the memory block will be injection erased at least once until the memory block is verified to have the over-erased transistor memory cells.
7. The erase method of claim 6, wherein when the memory block is verified to have the over-erased transistor memory cells, an over-erased correction shot is injected into the over-erased transistor memory cells and the sector enable signal is set to an active state.
8. A flash memory, comprising:
a memory management device electrically connected to the memory module for executing the erasing method according to one of claims 1 to 7; and
the memory module comprises the memory block.
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