CN110391871B

CN110391871B - Data coding and decoding method and device, OLT, ONU and PON system

Info

Publication number: CN110391871B
Application number: CN201810355101.9A
Authority: CN
Inventors: 高波; 景磊; 聂世玮
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-04-19
Filing date: 2018-04-19
Publication date: 2021-11-19
Anticipated expiration: 2038-04-19
Also published as: CN110391871A; WO2019201316A1

Abstract

The application discloses a data coding and decoding method and device in a PON system. When the total length of the received first data blocks is smaller than the FEC payload length of the FEC code pattern, carrying out FEC encoding on the received first data blocks to generate shortened codes, wherein the payload length of the shortened codes is smaller than the FEC payload length of the FEC code pattern, the length of each first data block is M bits, and the FEC payload length and the non-payload part length of the shortened codes are integral multiples of M; when the total length is larger than or equal to the FEC payload length, the received first data blocks are expanded and then transcoded, a plurality of third data blocks are generated after transcoding, the length of each third data block is N bits, N is larger than M, then the third data blocks are FEC encoded, and non-shortened codes are generated.

Description

Data coding and decoding method and device, OLT, ONU and PON system

Technical Field

The present application relates to the field of optical communications, and more particularly, to a data encoding and decoding method, a data encoding and decoding apparatus, an optical line terminal, an optical network unit, and a PON system in the PON system.

Background

Passive Optical Network (PON) technology is a point-to-multipoint Optical fiber access technology. The PON system may include an Optical Line Terminal (OLT), an Optical Distribution Network (ODN), and at least one Optical Network Unit (ONU). The OLT is connected with the ODN, and the ODN is connected with the ONU.

EPON is a technology that uses passive optical transmission, and an Forward Error Correction (FEC) technology is introduced into an EPON system to improve the interference rejection of the system.

FEC refers to that a signal is processed in advance in a certain manner before being transmitted, and is decoded at a receiving end according to a corresponding algorithm to achieve the purpose of finding and correcting an error code. The basic working principle of FEC in an EPON system is: the FEC check parts are added on the basis of the information data transmitted by the transmitting end, the check parts and the checked information data are mutually associated (restrained) by a certain rule, the receiving end checks the relation between the information data and the check parts according to the established rule, and once errors occur in transmission, the relation is destroyed, so that the receiving end automatically discovers and corrects the wrong code words.

In the uplink transmission, the length of the uplink burst information data sent by the ONU to the OLT is variable, and when the length of the information data is too short, it is not enough to generate a complete codeword.

Disclosure of Invention

In view of the above, the present application provides a data encoding and decoding method, a data encoding and decoding apparatus, a precoding indication method and apparatus, an optical line terminal, an optical network unit and a PON system in a PON system, and aims to better support transmission of uplink data with an excessively short length.

In a first aspect, an implementation subject may be an ONU in a PON system, for example, the ONU sends upstream burst data to an OLT, and the ONU first encodes the burst data. One of the codeword structures is a shortened code, and the method includes: receiving S first data blocks in a physical coding sublayer, wherein the length of each first data block is M bits; m × S is smaller than the FEC payload length of one FEC code pattern, a shortened code may be generated. Specifically, FEC encoding is performed on S first data blocks according to an FEC code pattern to generate a first check portion, where the FEC payload length is an integral multiple of M; then generating a first codeword structure, wherein the first codeword structure comprises a first payload and a first non-payload part, the first payload comprises S first data blocks, and the length of the first payload is smaller than that of the FEC payload; the first non-payload portion includes a first check portion and a first synchronization flag, and the lengths of the first payload and the first non-payload portion are each an integer multiple of M. By adopting the coding mode, the shortening code can be suitable for the condition of inputting various numbers of first data blocks, can ensure the constant input and output rates, is simple to realize and can be suitable for shortening codes with various lengths.

Another codeword structure is a non-shortened code, which can be divided into two types, and for the first non-shortened code, the method includes: receiving Q1 first data blocks at a physical coding sublayer, wherein M is Q1> the FEC payload length, transcoding the Q1 first data blocks to generate Q2 second data blocks, wherein the length of each second data block is N bits, and N > M; transcoding every t of said first data blocks into 1 of said second data blocks, t >1, and Q1 ═ t × FEC payload length/N, Q1 ═ t × Q2; performing FEC encoding on the Q2 second data blocks according to the FEC code patterns to generate second check parts; generating a second codeword structure at the physical coding sublayer, the second codeword structure comprising a second payload and a second non-payload portion, the second payload comprising Q2 second data blocks, the length of the second payload being equal to the FEC payload length; the second non-payload portion includes a second parity portion and a second synchronization flag, and the length of the second non-payload portion is an integer multiple of M. The FEC payload length is also an integer multiple of M.

For a second non-shortened code, each third data block is generated by transcoding t × M bits of data, t >1, and each third data block has a length of N bits, the method comprising: receiving Q3 first data blocks at the physical coding sublayer, M x Q3 ≧ FEC payload length, and Q3< Q1; expanding the Q3 first data blocks in the physical coding sublayer to make the total length of the expanded data equal to Q1M; transcoding the expanded data to generate Q2 third data blocks; performing FEC encoding on the Q2 third data blocks according to the FEC code pattern to generate a third check part; generating a second codeword structure at the physical coding sublayer, the second codeword structure comprising a third payload and a third non-payload portion, the third payload comprising Q2 third data blocks, the length of the third payload being equal to the FEC payload length; the third non-payload portion includes a third check portion and a third synchronization flag, and the length of the third non-payload portion is an integer multiple of M. When the number of the input first data blocks cannot generate shortened codes and cannot generate non-shortened codes, an expansion mode can be adopted, so that the data length meets the condition of generating the non-shortened codes, and then the second codeword structure is generated, so that the coding mode can be further suitable for all conditions (namely, no matter how many the number of the first data blocks are, an applicable coding mode can be found in the above three coding modes), thereby ensuring that the FEC code type can not only be suitable for the shortened codes with various lengths, but also be suitable for the non-shortened codes at the same time, and improving the flexibility of coding. The combination of the three coding modes can effectively ensure the coding efficiency and improve the bandwidth efficiency to the maximum extent.

It will be appreciated that for both cases of non-shortened codes, each case can be used alone as an independent topic.

The synchronization mark (including the first synchronization mark, the second synchronization mark, and the third synchronization mark) may be located between the payload (including the first payload, the second payload, and the third payload) and the check part (including the first check part, the second check part, and the third check part), which is beneficial to identifying whether the codeword is a shortened code or a non-shortened code during the process of synchronizing the codeword by the OLT, and can further achieve fast synchronization.

At least two of the first synchronization mark, the second synchronization mark and the third synchronization mark have the same length. Therefore, when the shortened codes and the non-shortened codes are identified, a similar synchronization mechanism can be adopted, so that the synchronization is more convenient, and the quick synchronization is favorably realized. For example, the three synchronization marks may all have the same length.

At least two of the first synchronization mark, the second synchronization mark and the third synchronization mark have the same value. Therefore, when the shortened codes and the non-shortened codes are identified, the same synchronization mechanism can be adopted, the synchronization is more convenient, and the quick synchronization is more favorably realized. For example, the three synchronization identifiers may all have the same value.

At least two of the first check part, the second check part and the third check part can be the same in length, so that the same synchronization mechanism can be adopted when the shortened codes and the non-shortened codes are identified, the synchronization is more convenient, and the quick synchronization is more favorably realized. For example, the lengths of the three check portions may all be the same.

The length of the first payload is equal to the sum of the lengths of the S first data blocks, namely the first payload only consists of the S first data blocks; the length of the second payload is equal to the sum of the lengths of the Q2 second data blocks, i.e. the second payload consists of only Q2 second data blocks. The length of the third payload is equal to the sum of the lengths of the Q2 third data blocks, i.e. the third payload consists of only Q2 third data blocks.

The length of the first non-payload part is greater than or equal to the sum of the lengths of the first synchronization mark and the first check part, and the rest bits in the first non-payload part except the first synchronization mark and the first check part can be used for other indication purposes; the length of the second non-payload portion is greater than or equal to the sum of the lengths of the second synchronization mark and the second parity portion, and the remaining bits of the second non-payload portion, except for the second synchronization mark and the second parity portion, may be used for other indication purposes. The length of the third non-payload portion is greater than or equal to the sum of the lengths of the third sync mark and the third check portion, and the remaining bits of the third non-payload portion, except for the third sync mark and the third check portion, may be used for other indication purposes.

At least two of the first non-payload portion, the second non-payload portion and the third non-payload portion are equal in length, thereby facilitating fast synchronization. For example, the three non-payload portions are all the same length.

M equals 66 or 65, N equals 129 or 257; alternatively, M equals 129 and N equals 257.

The FEC code pattern is any one of LDPC (19789,16962), LDPC (20046,16962), LDPC (20303,16962), and LDPC (20560,16962).

In a second aspect, there is provided a data decoding method in a PON system, where an execution subject may be an OLT in the PON system, an ONU sends upstream burst data to the OLT, and the OLT decodes the upstream burst data, where the decoding method is executed by a physical coding sublayer, and when a codeword received by the OLT is a shortened code, the method includes: receiving a first codeword structure at a physical coding sublayer, wherein the first codeword structure comprises a first payload and a first non-payload part, the first non-payload part comprises a first check part and a first synchronization mark, the first payload comprises at least 1 first data block, the length of each first data block is M bits, the lengths of the first payload and the first non-payload part are both integer multiples of M, a forward error correction coding (FEC) code type is correspondingly provided with the length of an FEC payload, the length of the FEC payload is integer multiples of M, and the length of the first payload is smaller than the length of the FEC payload; identifying a first codeword structure at the physical coding sublayer according to the first synchronization mark; extracting a first payload and a first check part from a physical coding sublayer; and carrying out forward error correction decoding on the first payload according to the FEC code pattern and the first check part in the physical coding sublayer. By adopting the decoding mode, the shortening code can be suitable for the condition of inputting various numbers of first data blocks, can ensure the constant input and output rates, is simple to realize and can be suitable for shortening codes with various lengths.

When the received code word is a non-shortened code, the method further comprises: receiving a second codeword structure at the physical coding sublayer, wherein the second codeword structure comprises a second payload and a second non-payload portion, the second non-payload portion comprises a second check portion and a second synchronization flag, the second payload comprises a plurality of second data blocks, the length of each second data block is N bits, N > M, the length of the second payload is equal to the length of the FEC payload, and the second non-payload portion is an integer multiple of M; identifying a second codeword structure in the physical coding sublayer according to the second synchronization mark; extracting a second payload and a second check part from the physical coding sublayer; and performing forward error correction decoding on the second payload according to the FEC code pattern and the second check part in the physical coding sublayer. The FEC payload length is also integral multiple of M, thereby ensuring that the FEC code pattern not only can be suitable for the shortened codes, but also can be suitable for non-shortened codes, and improving the flexibility of decoding.

The OLT synchronizes the received code stream, and for the synchronization process of the shortened code, the receiving of the first code word structure comprises the following steps: receiving a code stream at a physical coding sublayer, wherein the code stream comprises a burst delimiter and a first code word structure, or the code stream comprises the burst delimiter, the first code word structure and a second code word structure; identifying the first codeword structure based on the first synchronization flag comprises: after the burst delimiter or the second check part, identifying whether a first synchronization mark exists at the current interval position once every M bits, and counting the current identification times or the total bit number of the current interval; and after the existence of the first synchronization mark is identified, if the product of the identification times and M counted currently is smaller than the length of the FEC payload, or if the total bit number counted currently is smaller than the length of the FEC payload, judging that the currently identified code word is the first code word structure. By adopting the synchronization mechanism, the OLT side can identify the shortened codes with various lengths.

In order to further improve the reliability of the identification of the shortened codes, after the existence of the first synchronization mark is identified, if the product of the identification frequency of the current statistics and M is smaller than the FEC payload length, or if the total bit number of the current statistics is smaller than the FEC payload length, identifying whether an end mark exists after P bits are spaced, wherein the difference between the first non-payload length and the first synchronization mark length is P bits; and if the end character exists, judging the currently identified code word as the first code word structure. If the end symbol does not exist, returning to the position where the first synchronization mark is identified, continuously executing M bits per interval, identifying whether the first synchronization mark exists at the current interval position once, and counting the current identification times or counting the total bit number of the current interval. Therefore, whether the code is the shortened code or not is determined through secondary judgment, and the reliability of the identification of the shortened code is further improved.

For synchronization procedures with non-shortened codes, receiving a second codeword structure comprises: receiving a code stream at a physical coding sublayer, wherein the code stream comprises a burst delimiter and a second code word structure, or the code stream comprises the burst delimiter, the first code word structure and the second code word structure; identifying the second codeword structure based on the second synchronization mark comprises: after identifying the burst delimiter or the second check part, identifying whether a second synchronization mark exists at the current interval position once every M bits, and counting the current identification times or counting the total bit number of the current interval; and after each second synchronization mark is identified, if the product of the identification times of the current statistics and M is equal to the FEC payload length, or if the total number of bits of the current statistics is equal to the FEC payload length, judging that the currently identified code word is a second code word structure. By adopting the synchronization mechanism, the OLT side can further identify the non-shortened codes.

After judging that the currently identified code word is in a second code word structure, clearing the currently counted identification times or the currently counted total bit number, so that the OLT can continue to identify a new round; after P bits are spaced after the currently identified second synchronization mark, continuously identifying the first code word structure or the second code word structure; wherein the difference between the first non-payload length and the length of the first synchronization flag is P bits.

In a third aspect, there is provided a data encoding apparatus in a PON system, the apparatus being applicable to an ONU and transmitting upstream special data to an OLT, the apparatus comprising: the receiving module, the FEC encoding module and the generating module can also comprise a transcoding module. An expansion module may also be included.

A receiving module, configured to receive S first data blocks, where the length of each first data block is M bits, and M × S is smaller than an FEC payload length of an FEC code pattern of forward error correction coding;

shortened codes may be generated. The FEC encoding module performs FEC encoding on the S first data blocks according to the FEC code patterns to generate first check parts, wherein the FEC payload length is integral multiple of M; then a generating module generates a first codeword structure, wherein the first codeword structure comprises a first payload and a first non-payload part, the first payload comprises S first data blocks, and the length of the first payload is smaller than that of the FEC payload; the first non-payload portion includes a first check portion and a first synchronization flag, and the lengths of the first payload and the first non-payload portion are each an integer multiple of M. By adopting the coding mode, the shortening code can be suitable for the condition of inputting various numbers of first data blocks, can ensure the constant input and output rates, is simple to realize and can be suitable for shortening codes with various lengths.

Non-shortened codes may also be generated. Non-shortened codes may also be referred to as full codes, or full codes. The non-shortened code may be divided into two cases, in one case, the receiving module is further configured to receive Q1 first data blocks, M × Q1> FEC payload length; the transcoding module transcodes the Q1 first data blocks to generate Q2 second data blocks, wherein the length of each second data block is N bits, and N > M; transcoding every t first data blocks into 1 second data block, t >1, and Q1 ═ t × FEC payload length/N, Q1 ═ t × Q2; the FEC encoding module performs FEC encoding on the Q2 second data blocks according to the FEC code patterns to generate second check parts; the generating module generates a second codeword structure, the second codeword structure comprising a second payload and a second non-payload portion, the second payload comprising Q2 second data blocks, the length of the second payload being equal to the FEC payload length; the second non-payload portion includes a second parity portion and a second synchronization flag, and the length of the second non-payload portion is an integer multiple of M. The FEC payload length is also an integer multiple of M. The FEC code pattern can be suitable for the condition of inputting any number of first data blocks, and an applicable coding mode can be correspondingly found no matter how many first data blocks are input, so that the FEC code pattern can be suitable for shortening codes with various lengths and non-shortening codes, and the coding flexibility is improved.

The non-shortened code is the other condition that the receiving module is also used for receiving Q3 first data blocks, M Q3 is more than or equal to the FEC payload length, and Q3 is less than Q1; the expanding module is used for expanding the Q3 first data blocks so that the total length of the expanded data is equal to Q1M; the transcoding module is further used for transcoding the expanded data to generate Q2 third data blocks; the forward error correction coding and decoding module is further configured to perform FEC coding on the Q2 third data blocks according to the FEC code patterns to generate third check portions; the generating module is further configured to generate a second codeword structure, where the second codeword structure includes a third payload and a third non-payload portion, the third payload includes Q2 third data blocks, and the length of the third payload is equal to the FEC payload length; the third non-payload portion includes a third check portion and a third synchronization flag, and the length of the third non-payload portion is an integer multiple of M. When the number of the input first data blocks cannot generate the shortened codes and cannot generate the non-shortened codes, an expansion mode can be adopted, so that the data length meets the condition of generating the non-shortened codes, and the second codeword structure is generated, so that the coding mode can be further suitable for all conditions (namely, no matter the number of the first data blocks is, an applicable coding mode can be found in the three coding modes), and the flexibility of coding is improved. The combination of the three coding modes can effectively ensure the coding efficiency and improve the bandwidth efficiency to the maximum extent.

In a fourth aspect, there is provided a data decoding apparatus in a PON system, the apparatus including, when a shortened code is received: a receiving module, configured to receive a first codeword structure, where the first codeword structure includes a first payload and a first non-payload portion, the first non-payload portion includes a first check portion and a first synchronization flag, the first payload includes at least 1 first data block, the length of each first data block is M bits, the lengths of the first payload and the first non-payload portion are both integer multiples of M, a forward error correction coding FEC code type is correspondingly provided with an FEC payload length, the FEC payload length is integer multiples of M, and the length of the first payload is smaller than the FEC payload length; a synchronization module for identifying a first codeword structure according to a first synchronization flag; the extraction module is used for extracting the first payload and the first check part; and the forward error correction coding and decoding module is used for carrying out forward error correction decoding on the first payload according to the FEC code pattern and the first check part. By adopting the decoding mode, the shortening code can be suitable for the condition of inputting various numbers of first data blocks, can ensure the constant input and output rates, is simple to realize and can be suitable for shortening codes with various lengths.

In a fifth aspect, an ONU is provided. The ONU may include a processing module, which may be a MAC (Media Access Control) chip, or a processor, or a DSP (digital signal processor), etc. The processing module receives S first data blocks at a physical coding sublayer, wherein the length of each first data block is M bits, and M × S is smaller than the FEC payload length of a forward error correction coding FEC code pattern; the FEC payload length is an integral multiple of M; FEC encoding is carried out on the S first data blocks on a physical encoding sub-layer according to FEC code patterns to generate first check parts; generating a first code word structure in a physical coding sublayer, wherein the first code word structure comprises a first payload and a first non-payload part, the first payload comprises S first data blocks, and the length of the first payload is smaller than that of an FEC payload; the first non-payload portion includes a first check portion and a first synchronization flag, and the lengths of the first payload and the first non-payload portion are each an integer multiple of M. By adopting the coding mode, the shortening code can be suitable for the condition of inputting various numbers of first data blocks, can ensure the constant input and output rates, is simple to realize and can be suitable for shortening codes with various lengths.

In a sixth aspect, an OLT is provided, which may include a processing module, where the processing module may be a MAC (Media Access Control) chip, or a processor, or a DSP (digital signal processor), etc. The processing module receives a first codeword structure at a physical coding sublayer, wherein the first codeword structure comprises a first payload and a first non-payload part, the first non-payload part comprises a first check part and a first synchronization mark, the first payload comprises at least 1 first data block, the length of each first data block is M bits, the lengths of the first payload and the first non-payload part are both integer multiples of M, a forward error correction coding (FEC) code type is correspondingly provided with the length of an FEC payload, the length of the FEC payload is integer multiples of M, and the length of the first payload is smaller than the length of the FEC payload; identifying a first codeword structure at the physical coding sublayer according to the first synchronization mark; extracting a first payload and a first check part from a physical coding sublayer; and carrying out forward error correction decoding on the first payload according to the FEC code pattern and the first check part in the physical coding sublayer. By adopting the decoding mode, the shortening code can be suitable for the condition of inputting various numbers of first data blocks, can ensure the constant input and output rates, is simple to realize and can be suitable for shortening codes with various lengths.

It is to be understood that the subject matter described above differs from one aspect to another, but specific implementation details may be mutually referenced, some subject matter may not be specifically described, and other subject matter may be referenced.

In a seventh aspect, an ONU is provided, where the ONU includes the apparatus of the third aspect.

In an eighth aspect, an OLT is provided, which includes the apparatus of the fourth aspect.

In another aspect of the present application, a codeword structure is provided, where the codeword structure is the first codeword structure.

In another aspect of the present application, a codeword structure is provided, where the codeword structure is the second codeword structure.

In another aspect of the present application, a codeword structure is provided, where the codeword structure is the third codeword structure.

The details of the synchronization flag, the details of the data block, the details of the FEC code pattern, the details of the codeword structure, and the like may refer to other aspects, and are not described herein again.

In another aspect of the present application, a MAC chip is provided, which includes the apparatus of the third or fourth aspect.

In a further aspect of the present application, a PON system is provided, which comprises the optical line terminal of the fifth aspect and the optical network unit of the sixth aspect.

In yet another aspect of the present application, a computer-readable storage medium is provided, in which computer software instructions for the apparatus of the third or fourth aspect, or for the ONU of the fifth aspect, or for the OLT of the sixth aspect, are stored, which, when run on a computer, cause the computer to perform the method of the above aspects.

Drawings

Fig. 1 is a schematic diagram of a PON system according to an embodiment of the present application;

FIG. 2 is a flowchart illustrating a method for encoding and decoding shortened data according to an embodiment of the present application;

FIG. 3 is a schematic diagram of shortened code generation according to an embodiment of the present application;

FIG. 4 is an exemplary flowchart of a method for encoding and decoding data for non-shortened codes according to an embodiment of the present application;

fig. 5(a) is a schematic diagram of block transcoding according to an embodiment of the present application;

fig. 5(b) is another schematic diagram of data block transcoding according to an embodiment of the present application;

fig. 5(c) is a further schematic diagram of data block transcoding according to an embodiment of the present application;

FIG. 5(d) is a further schematic diagram of transcoding a data block according to an embodiment of the present application;

FIG. 5(e) is a further schematic diagram of transcoding a data block according to an embodiment of the present application;

FIG. 5(f) is a further schematic diagram of transcoding a data block according to an embodiment of the present application;

FIG. 6 is a diagram illustrating generation of non-shortened codes according to an embodiment of the present application;

FIG. 7 is another exemplary flowchart of a method for encoding and decoding data for non-shortened codes according to an embodiment of the present application;

FIG. 8 is a schematic diagram illustrating another generation of non-shortened codes according to an embodiment of the present application;

fig. 9 is an exemplary flow chart of a synchronization mechanism of an OLT according to an embodiment of the present application;

fig. 10 is a schematic diagram of a hardware structure of an ONU according to an embodiment of the present application;

fig. 11 is a schematic hardware structure diagram of an OLT according to an embodiment of the present application;

FIG. 12 is a diagram illustrating exemplary functional blocks of a data encoding apparatus according to an embodiment of the present application;

FIG. 13 is a block diagram illustrating exemplary functional blocks of a data decoding apparatus according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, features and advantages of the present invention more apparent and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the embodiments described below are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The technical solution of the embodiment of the present application may be applied to various Ethernet Passive Optical Networks (EPONs), such as an EPON, a 10G EPON, a single-wave 25G EPON, a 2 × 25G EPON, a single-wave 50G EPON, a 2 × 50G EPON, and a 100G EPON. The method can also be used in various Gigabit Passive Optical Networks (GPON).

Fig. 1 is a schematic architecture diagram of a PON system to which various embodiments of the present invention are applied, and as shown in fig. 1, the PON system 100 includes at least one OLT110, at least one ODN120, and a plurality of ONUs 130. The OLT110 provides a network side interface for the PON system 100, and the ONU130 provides a user side interface for the PON system 100, and is connected to the ODN 120. If ONU130 directly provides the user port function, it is called Optical Network Terminal (ONT). For convenience of description, the ONU130 mentioned below refers to an ONT that can directly provide a user port function and an ONU that provides a user side interface. The ODN120 is a network composed of optical fibers and passive optical splitting devices, and is used for connecting the OLT110 device and the ONU130 device, and for distributing or multiplexing data signals between the OLT110 and the ONU 130.

In the PON system 100, a direction from the OLT110 to the ONUs 130 is defined as a downstream direction, and a direction from the ONUs 130 to the OLT110 is defined as an upstream direction. In the downlink direction, the OLT110 broadcasts downlink data to a plurality of ONUs 130 managed by the OLT110 in a Time Division Multiplexing (TDM) manner, and each ONU130 only receives data carrying its own identifier; in the uplink direction, the ONUs 130 communicate with the OLT110 in a Time Division Multiple Access (TDMA) manner, and each ONU130 transmits uplink data according to the Time domain resource allocated to it by the OLT 110. With the above mechanism, the downstream optical signal transmitted by the OLT110 is a continuous optical signal, and the upstream optical signal transmitted by the ONU130 is a burst optical signal.

The OLT110 is typically located in a Central Office (CO), and may collectively manage at least one ONU130 and transmit data between the ONU130 and an upper network. In particular, the OLT110 may act as an intermediary between the ONUs 130 and an upper Network (e.g., the Internet, a Public Switched Telephone Network (PSTN)), forwarding data received from the upper Network to the ONUs 130, and forwarding data received from the ONUs 130 to the upper Network, the specific configuration of the OLT110 may vary depending on the specific type of the PON system 100. for example, in one embodiment, the OLT110 may include a transmitter for transmitting downstream continuous optical signals to the ONUs 130 and a receiver for receiving upstream optical burst signals from the ONUs 130, wherein the downstream optical signals and the upstream optical signals may be transmitted through the ODN120, but the embodiments are not limited thereto.

The ONUs 130 may be distributively located at customer-side locations (e.g., customer premises). The ONU130 may be a network device for communicating with the OLT110 and a user, in particular, the ONU130 may act as an intermediary between the OLT110 and the user, e.g. the ONU130 may forward data received from the OLT110 to the user and forward data received from the user to the OLT 110.

The ODN120 may be a data distribution network and may include optical fibers, optical couplers, optical splitters, or other devices. In one embodiment, the optical fiber, optical coupler, optical splitter, or other device may be a passive optical component, and in particular, the optical fiber, optical coupler, optical splitter, or other device may be a component that does not require power support when distributing data signals between the OLT110 and the ONUs 130. Specifically, taking an optical splitter as an example, the optical splitter may be connected to the OLT110 through a trunk fiber and connected to the plurality of ONUs 130 through a plurality of branch fibers, respectively, so as to implement point-to-multipoint connection between the OLT110 and the ONUs 130. Additionally, in other embodiments, the ODN120 may also include one or more processing devices, such as optical amplifiers or relay devices. In addition, the ODN120 may specifically extend from the OLT110 to the plurality of ONUs 130, but may also be configured in any other point-to-multipoint structure, and the embodiment of the present application is not limited thereto.

The technical solution of the embodiment of the present application, which is described below, may be that the ONU130 performs FEC encoding to generate a codeword structure, and sends the codeword structure to the OLT110, and the OLT110 decodes the codeword structure.

The OLT and the ONU may include a processing module, which may be a MAC (Media Access Control) chip, or a processor, or a DSP (digital signal processor), etc. Operations at the Physical Coding Sublayer (PCS) are performed by the processing module. The following takes as an example the operation of the physical coding sublayer performed by the MAC chip.

In the following embodiments, the codeword structure sent by the ONU to the OLT may be divided into non-shortened codes and shortened codes. The ONU is provided with an FEC codeword length and an FEC payload length corresponding to the FEC code pattern adopted by the OLT, which indicates that in the codeword structure encoded by adopting the FEC code pattern, the length of the check part is equal to the FEC codeword length minus the FEC payload length. The FEC Code pattern may be Low Density Parity Check Code (LDPC), and may be any one of LDPC (19789,16962), LDPC (20046,16962), LDPC (20303,16962), and LDPC (20560,16962), and the FEC Code pattern is not limited to the above-listed ones, and is not limited to the LDPC Code pattern. It is to be understood that the FEC code pattern may also adopt other expression manners, and may indicate the FEC codeword length and the FEC payload length.

Taking LDPC (20560,16962) as an example of the FEC code type adopted by the ONU and the OLT, where the FEC code type indicates that the FEC payload length is 16962, the FEC codeword length is 20560, and indicates that after FEC encoding is performed on data with a length less than or equal to 16962 bits, check data with a length of 20560 and 16962 bits, that is, 3598 bits is generated. If the payload length in the codeword structure is equal to the FEC payload length (16962 bits), the check part length in the codeword structure is the difference between the FEC codeword length and the FEC payload length (3598 bits), and the total length of the payload and check part in the codeword structure is 20560 bits of the FEC codeword length, then the codeword structure is called a non-shortened code. If the payload length in the codeword structure is less than the FEC payload length (16962 bits), the check part length in the codeword structure is the difference between the FEC codeword length and the FEC payload length (3598 bits), and the total length of the codeword structure is less than the FEC codeword length 20560 bits, then the codeword structure is called a shortened code.

The physical coding sublayer receives an input data block (the length may be 66 bits or 65 bits), for example, the received data block length is 66 bits. In the present embodiment, the input data block refers to the data content that needs to be transmitted.

In one embodiment, when generating the non-shortened code, the data blocks with the length of 66 bits may be transcoded, for example, every 2 data blocks with the length of 66 bits may be transcoded into a data block with the length of 129 bits, or every 4 data blocks with the length of 66 bits may be transcoded into a data block with the length of 257 bits, and then the transcoded data blocks are FEC-encoded to generate the codeword structure. Taking the FEC code type as LDPC (20560,16962) and the transcoded data block length as 257 bits as an example, the number of data blocks with length of 257 bits required to form one non-shortened code is 16962/257-66, and therefore the number of data blocks with length of 66 bits input to form one non-shortened code is 66-4-264. In this application, the multiplication number is denoted by "". When generating the shortened code, the data block with the length of 66 bits may be FEC encoded directly from the data block with the length of 66 bits without performing transcoding processing, and the shortened code may be generated.

In a certain uplink transmission, the number of 66-bit data blocks sent by an ONU to an OLT may be exactly equal to 264, or exactly equal to an integral multiple of 264, at this time, transcoding is performed first, and then FEC encoding is performed to generate a codeword structure, where the codeword structures sent by the ONU to the OLT are all non-shortened codes.

However, the number of 66-bit data blocks sent by the ONU to the OLT may also be less than or equal to 256, and at this time, the total length of the 66-bit data blocks is less than 16962, at this time, the FEC encoding may be directly performed according to the 66-bit data blocks without performing the transcoding process, so as to generate 1 shortened code, and at this time, the ONU may send one shortened code to the OLT; or the total number of 66-bit data blocks sent by the ONU to the OLT is greater than 264, but a remainder of dividing the total number by 264 is less than or equal to 256, at this time, the ONU sends at least one non-shortened code and 1 shortened code to the OLT, for example, the total number is 364, the 264-bit data blocks may be transcoded, FEC-encoded to generate a non-shortened code, the remaining 100 data blocks of 66b are not transcoded, FEC-encoded to generate a shortened code, and the ONU may send one non-shortened code and one shortened code to the OLT.

The number of 66-bit data blocks sent by the ONU to the OLT may also be equal to 257, and at this time, the total length of the 66-bit data blocks is equal to 16962, in one embodiment, transcoding is performed first, then, the transcoded data blocks are extended, so that the total length of the extended data is equal to 16962, then, FEC encoding is performed, a non-shortened code is generated, and the ONU may send a non-shortened code to the OLT; another embodiment is that, without transcoding, FEC encoding is directly performed on the data block 66b to generate a non-shortened code, where the payload of the non-shortened code is the above data block of 257 bits, and the ONU may send a non-shortened code to the OLT. Or, the total number of 66-bit data blocks sent by the ONU to the OLT is greater than 264, but a remainder of dividing the total number by 264 is equal to 257, for example, the total number is 521, the 264-bit data blocks may be transcoded, FEC-encoded to generate a non-shortened code, the remaining 257 data blocks of 66 bits are transcoded, then extended, and FEC-encoded again to generate a non-shortened code, and the ONU may send 2 non-shortened codes to the OLT. It is understood that, in the above embodiment, the expansion process may be performed first (in this case, the total length after the expansion is 66 × 264 — 17424b), and then the transcoding process may be performed (the data length after the transcoding is 16962 b).

The number of 66-bit data blocks sent by the ONU to the OLT may be greater than 257 and less than 264, or the total number of 66-bit data blocks sent by the ONU to the OLT is greater than 264, but the remainder of dividing the total number by 264 is greater than 257 and less than 264, transcoding may be performed first, then expansion processing is performed, so that the total length of the expanded data is equal to 16962, and then FEC encoding is performed to generate a non-shortened code; or, the data may be expanded to have a total length of 66 × 264 — 17424b, then transcoded to have a total length of 16962b, and then FEC encoded to generate the non-shortened code. The details are the same as above, and are not repeated herein.

According to the above, there are three coding modes, the shortened code includes one coding mode, and the non-shortened code is specifically divided into two coding modes, which will be described in detail below with reference to the accompanying drawings. In the following embodiments, the first codeword structure refers to a shortened code. In order to distinguish between the non-shortened codes in the two encoding schemes, the following embodiments refer to the non-shortened codes in the two encoding schemes as the second codeword structure and the third codeword structure, respectively.

As shown in fig. 2, taking the shortened code as an example, a data encoding and decoding method is provided, which includes steps S200 to S206, and the specific implementation manner of each step is as follows:

s200, the ONU receives S first data blocks in a physical coding sublayer, wherein S is an integer. Each first data block is M bits long. And the total length of the S first data blocks is less than the FEC payload length, and the FEC payload length is an integral multiple of M.

The first data block may be a 64B/66B or 64B/65B data block.

The 64B/66B data block is characterized in that the total length of the data block is 66 bits, which contains 64 bits of data, and 2 bits of indication information for indicating whether the 64 bits of data in the data block are data information or control information. The 2-bit indication information may be located at the head or the tail of the data block.

Similarly, a 64B/65B data block refers to a data block with a total length of 65 bits, which contains 64 bits of data, and 1 bit of indication information for indicating whether the 64 bits of data in the data block are data information or control information. The 1-bit indication information may be located at the head or the tail of the data block.

The length of the first data block may be other lengths, and is not limited herein.

Similarly, the data blocks of 128B/129B and 256B/257B described in the following embodiments are similar to those described above, and are not repeated herein.

S201, the ONU performs FEC coding on S first data blocks in a physical coding sublayer according to FEC code patterns to generate a first check part;

in this embodiment, the total length of the S first data blocks is smaller than the FEC payload length, and the S first data blocks are not enough to form a non-shortened code and may form a shortened code. Before FEC encoding, the S first data blocks may not be transcoded, and FEC encoding may be directly performed on the S first data blocks, that is, the S first data blocks may be directly passed through to an FEC encoder.

In this embodiment, the FEC payload length is an integer multiple of M.

S202, the ONU generates a first code word structure in a physical coding sublayer, wherein the first code word structure comprises a first payload part and a first non-payload part. The first payload includes S first data blocks, and the length of the first payload is smaller than the length of the FEC payload, wherein the first payload may include only S first data blocks, or the first payload may further include S first data blocks and other portions (such as a precoding enable indication portion, etc.). The first non-payload portion includes a first check portion and a first synchronization flag, the first non-payload portion being an integer multiple of M. The first non-payload portion may only include the first check portion and the first synchronization flag, or the first non-payload portion may also include the first check portion and the first synchronization flag, and other portions for other purposes (e.g., a precoding enable indication portion, etc.).

Fig. 3 is a schematic diagram of generating a shortened code according to an embodiment of the present application. The FEC code pattern is LDPC (20560,16962) as an example. The first data block is a data block of length 66b for example. Assuming that S is 250, the total length of the first data block is 250 × 66 — 16500 b. Since the total length of the input data block is consistent with the total length of the output data block, some bit blocks can be added after the input data block. 3598/66 ═ 54.5, therefore, 55 occupied-bit blocks of 66b can be added, 55 × 66-3598 ═ 32b, the codeword structure includes the payload of 16500b, the first parity portion of 3598b, the remaining 32b can be used as the synchronization flag in its entirety, or the remaining 32b can be used as the synchronization flag in part, and the rest is used for other purposes (such as precoding enable indication). In addition, 56 or more placeholders of 66b may be added, and the remaining bits of the codeword structure, except for the payload of 16500b and the first parity portion of 3598b, may be used as a synchronization flag or for other purposes.

For other FEC code patterns, the principle is the same, and is not described herein again.

S203, the OLT receives the first codeword structure in the physical coding sublayer.

S204, the OLT identifies a first code word structure in the physical coding sublayer according to the first synchronization mark;

for example, the OLT may pre-store a synchronization sequence, traverse the pre-stored synchronization sequence in the received codeword structure, and complete the identification until the synchronization mark in the codeword structure matches the pre-stored synchronization sequence.

S205, extracting a first payload and a first check part from a physical coding sublayer;

s206, the physical coding sublayer carries out forward error correction decoding on the first payload according to the FEC code pattern and the first check part.

It is understood that the forward error correction decoding herein corresponds to the forward error correction coding described above, and the same expression may be adopted, for example, the forward error correction decoding method is any one of LDPC (19789,16962), LDPC (20046,16962), LDPC (20303,16962), and LDPC (20560,16962). Taking LDPC (20560,16962) as an example, the OLT forward error correction decodes the payload using a check data field of 3598 bits. For details, reference may be made to the above description of forward error correction coding, which is not described herein again.

In this embodiment, the first codeword structure is a shortened code, the first payload in the shortened code includes S first data blocks, which are integer multiples of M, and the first non-payload portion is also integer multiples of M. Therefore, the shortening code can be suitable for the condition of inputting various numbers of first data blocks, the number of the added occupied blocks can be constant, the input and output rates can be guaranteed to be unchanged, the realization is simple, and the shortening code can be suitable for shortening codes with various lengths.

As shown in fig. 4, taking the first coding and decoding method of non-shortened codes as an example, the method further includes steps S300 to S307, and the specific implementation manner of each step is as follows:

s300, the ONU receives Q1 first data blocks in the physical coding sublayer, and the total length of the Q1 first data blocks is greater than the FEC payload length;

s301, the ONU transcodes Q1 first data blocks in a physical coding sublayer to generate Q2 second data blocks, wherein Q1> Q2, the length of each second data block is N bits, and N > M;

s302, the ONU performs FEC encoding on the Q2 second data blocks in the physical encoding sublayer according to the FEC code type to generate a second check part;

s303, the ONU generates a second code word structure in the physical coding sublayer, the second code word structure comprises a second payload and a second non-payload part, the second payload comprises Q2 second data blocks, and the length of the second payload is equal to the length of the FEC payload; the second non-payload portion includes a second parity portion and a second synchronization flag, the second non-payload portion being an integer multiple of M.

The details of some steps in fig. 4 can refer to the description of related steps in fig. 2, and are not repeated here.

The data blocks of 64B/66B are transcoded into data blocks of 128B/129B as shown in FIGS. 5(a) to 5(d), and each 2 data blocks of 64B/66B are transcoded into one data block of 128B/129B.

The data blocks of 64B/66B are divided into two types, one is a data block carrying data information, and the other is a data block carrying control information. Taking fig. 5(a) to 5(d) as an example, the 2-bit indication information in the data block is "01", and 64 bits indicating the data block are data information; the 2-bit indication information in the data block is "10", indicating that 64 bits of the data block are control information.

FIG. 5(a) transcodes 2 data blocks of 64B/66B carrying data information into 1 data block of 128B/129B. The 2-bit indication information of the 2 64B/66B data blocks can be removed, and 1-bit indication information can be added to the data types (including two types of data information and control information) of 128 bits carried by the transcoded data blocks. As shown in fig. 5(a), DB1(64) and DB2(64) respectively represent 64-bit data information in two data blocks.

FIG. 5(B) transcodes 2 data blocks of 64B/66B carrying control information into 1 data block of 128B/129B. The 64B/66B data blocks carrying the control information include 4 bits of S1(4), and 4 bits of S1(4) in one of the data blocks can be deleted, 2 bits of indication information of 2 64B/66B data blocks can be reserved, and 1 bit can be additionally added. The arrangement rule of each information in the transcoded 129-bit data block can be set according to actual needs, so that intercommunication is realized. Taking fig. 5(B) as an example, 1 bit additionally added is placed in the head of the data block, followed by 2 bits of indication information of the data blocks of 2 64B/66B, respectively, then control information in the data blocks of 64B/66B of S1(4) from which 4 bits are removed, and then control information in the data blocks of 64B/66B of S1(4) from which 4 bits are not removed. It will be appreciated that other arrangements may be used.

FIG. 5(c) transcodes 1 data block of 64B/66B carrying control information and 1 data block of 64B/66B carrying data information into 1 data block of 128B/129B. The 64B/66B data block carrying the control information includes 4 bits of S1(4), and 4 bits of S1(4) in the data block can be deleted, and 2 bits of indication information of 2 64B/66B data blocks can be reserved, and 1 bit can be additionally added. The arrangement rule of each information in the transcoded 129-bit data block can be set according to actual needs, so that intercommunication is realized. Taking fig. 5(c) as an example, 1 bit additionally added is placed in the header of the data block, followed by 2-bit indication information of the data block of 64B/66B carrying control information and data information, respectively, then control information in the data block of 64B/66B of S1(4) with 4 bits removed, and then data information in the data block of 64B/66B carrying data information. It will be appreciated that other arrangements may be used.

FIG. 5(d) transcodes 1 data block of 64B/66B carrying data information and 1 data block of 64B/66B carrying control information into 1 data block of 128B/129B. Unlike fig. 5(c), the additionally added 1 bit is placed in the header of the data block, followed by the 2-bit indication information of the data block of 64B/66B carrying data information and carrying control information, respectively, followed by the data information in the data block of 64B/66B carrying data information, followed by the control information in the data block of 64B/66B of S1(4) with 4 bits removed. It will be appreciated that other arrangements may be used.

FIG. 5(e) transcodes 2 data blocks of 64B/65B carrying data information into 1 data block of 128B/129B. The 1-bit indication information of the 2 64B/65B data blocks can be removed, and the 1-bit indication information can be added to the 128-bit data types (including two types of data information and control information) carried by the transcoded data blocks. As shown in fig. 5(e), DB1(64) and DB2(64) respectively represent 64-bit data information in two data blocks.

FIG. 5(f) transcodes 4 data blocks of 64B/65B carrying data information into 1 data block of 256B/257B. The 1-bit indication information of the 4 64B/65B data blocks can be removed, and the 1-bit indication information can be added to carry 256-bit data types (including two types of data information and control information) carried by the transcoded data blocks. As shown in fig. 5(f), DB1(64), DB2(64), DB3(64), and DB4(64) respectively represent 64-bit data information in four data blocks.

When the 64B/66B data blocks are transcoded into 256B/257B data blocks, every 4 64B/66B data blocks are transcoded into 1 256B/257B data blocks, the specific transcoding principle is similar to the above, effective data information and control information can be reserved, indication information or S1(4) can be removed, 1 bit or more bits can be additionally added, in short, the transcoded data blocks do not lose effective data, and the total bit number is 256B.

For a specific implementation scheme of transcoding the 64B/65B data block into the 128B/129B or 256B/257B data block, reference may be made to the above-mentioned transcoding scheme of the 64B/66B data block, which is not described herein again.

By transcoding, bandwidth efficiency can be effectively improved.

Fig. 6 is a schematic diagram of generating a non-shortened code according to an embodiment of the present application. The FEC code pattern is LDPC (20560,16962) as an example. The first data block is a data block with a length of 66b, and the second data block after transcoding has a length of 257b is taken as an example. 264 for Q1, transcoding every 4 first data blocks into 1 second data block, and transcoding to obtain 66 second data blocks for Q2 264/4. Since 257 x 66 ═ 16962, exactly equals the FEC payload length, 66 second data blocks constitute the payload. After FEC encoding the 66 second data blocks, a second parity portion 3598b is generated. Since the total length of the input data block is consistent with the total length of the output data block, some bit blocks can be added after the input data block. 20560/66 is 311.5, therefore, the sum of the number of the first data block of 66b and the occupied block of 66b is at least 312, for example, 312 is equal to 312, the number of occupied blocks is 312 and 264 is 48, 312 is 66-169602 and 3598 is 32b, the codeword structure includes the payload of 16962b, the second parity portion of 3598b, the remaining 32b can be used as the synchronization flag in its entirety, or the remaining 32b can be used as the synchronization flag in its part, and the rest is used for other purposes (such as precoding enabling indication). In addition, 49 or more placeholders of 66b may be added, and the remaining bits in the codeword structure, except for the payload of 16962b and the second parity portion of 3598b, may be used as synchronization flags or for other purposes. For other FEC code patterns, the principle is the same, and is not described herein again.

S304, the OLT receives the second codeword structure in the physical coding sublayer.

S305, the OLT identifies a second code word structure in the physical coding sublayer according to a second synchronization mark;

S306, extracting a second payload and a second check part from the physical coding sublayer;

s307, the second payload is decoded by the physical coding sublayer according to the FEC code pattern and the second check part.

For details, reference may be made to the above description of the shortened codes, which is not described herein again.

In this embodiment, the second codeword structure is a non-shortened code, and the FEC payload length is also an integer multiple of M, so that it is ensured that the FEC code pattern is not only applicable to the shortened code, but also applicable to the non-shortened code, thereby improving the flexibility of encoding.

When the number of the first data blocks is less than Q1 and the total length of the first data blocks is greater than or equal to the FEC payload length, a coding method of a non-shortened code may also be adopted, as shown in fig. 7, the method is a second coding method of a shortened code, the method further includes steps S400 to S408, and a specific implementation manner of each step is as follows:

s400, the ONU receives Q3 first data blocks in the physical coding sublayer, wherein Q3< Q1, and the total length of the Q3 first data blocks is larger than or equal to the FEC payload length;

s401, the ONU carries out extension processing on the Q3 first data blocks in a physical coding sublayer, so that the total length of the extended data is equal to Q1M;

the FEC code pattern is LDPC (20560,16962) as an example. The first data block is a data block of length 66b for example. Q3 66 is equal to or more than 16962, namely Q3 is equal to or more than 257, Q1 is equal to 264, and Q3 is less than 264.

Therefore, the extended total length of data is 264 × 66 — 17424 b. The extended data length is (Q1-Q3) × M.

S402, the ONU transcodes the expanded data in a physical coding sublayer to generate Q2 third data blocks, wherein the length of each third data block is N bits, and N is more than M;

for the details of transcoding, reference may be made to the above embodiments, which are not described herein again.

S403, the ONU performs FEC encoding on the Q2 third data blocks in the physical encoding sublayer according to the FEC code pattern to generate a fourth check part;

s404, the ONU generates a third code word structure in the physical coding sublayer, the third code word structure comprises a third payload and a third non-payload part, the third payload comprises Q2 third data blocks, and the length of the third payload is equal to the length of the FEC payload; the third non-payload portion includes a third check portion and a third synchronization flag, the third non-payload portion being an integer multiple of M.

Fig. 8 is a schematic diagram of generating a non-shortened code according to another embodiment of the present application. The FEC code pattern is LDPC (20560,16962) as an example. The first data block is a data block of length 66b, and the third data block is 257b for example. Q3 is exemplified as equal to 260. The data block of 264-260-66 b can be expanded after the first data block (or before the first data block, or at other positions, it is enough to be predefined between the OLT and the ONU), so that the total length of the expanded data is 17424 b. And then, transcoding the 17424b data, which is not described herein again, to obtain 66 third data blocks after transcoding. Since 257 x 66 ═ 16962, exactly equal to the FEC payload length, 66 third data blocks constitute the payload. After FEC encoding, a third parity portion 3598b is generated. Since the total length of the input data block is consistent with the total length of the output data block, some bit blocks can be added after the input data block. 20560/66 is 311.5, therefore, the sum of the number of the first data block of 66b and the occupied block of 66b is at least 312, for example, 312 is equal to 312, the number of occupied blocks is 312 and 264 is 48, 312 is 66-169602 and 3598 is 32b, the codeword structure includes the payload of 16962b, the third check part of 3598b, the remaining 32b can be used as the synchronization flag in its entirety, or the remaining 32b can be used as the synchronization flag in its part, and the rest is used for other purposes (such as precoding enabling indication). In addition, 49 or more placeholders of 66b may be added, and the remaining bits in the codeword structure, except for the payload of 16962b and the third parity portion of 3598b, may be used as synchronization flags or for other purposes. For other FEC code patterns, the principle is the same, and is not described herein again.

S405, the OLT receives the third codeword structure in the physical coding sublayer.

S406, the OLT identifies a third code word structure in the physical coding sublayer according to a third synchronization mark;

S407, extracting a third payload and a third check part from the physical coding sublayer;

and S408, performing forward error correction decoding on the third payload according to the FEC code pattern and the third check part in the physical coding sublayer.

In this embodiment, when the number of the input first data blocks cannot generate a shortened code or a non-shortened code, an extension mode may be adopted, so that the data length satisfies a condition for generating a non-shortened code, and the third codeword structure is generated, so that the coding method may be further applicable to all situations (that is, no matter how many first data blocks are, an applicable coding method can be found among the above three coding methods), and the flexibility of coding is improved.

It is understood that, when the total length of the Q3 first data blocks is equal to the length of the FEC payload, the third parity portion may also be generated directly from the Q3 first data blocks without performing the extension process and without performing the transcoding, and the third payload includes the Q3 first data blocks.

It is to be understood that both encoding and decoding methods of the non-shortened codes can be implemented as independent embodiments, or can be implemented in combination with the shortened codes.

The synchronization mark (including the first synchronization mark, the second synchronization mark and/or the third synchronization mark) may immediately follow the payload (including the first payload, the second payload and/or the third payload), or be located between the payload and the check portion (including the first check portion, the second check portion and/or the third check portion), or be located at the head of the codeword structure (including the first codeword structure, the second codeword structure and/or the third codeword structure), or be located at the tail of the codeword structure. The synchronization mark may also be referred to as an am (async mark) or FEC delimiter.

The following embodiments describe the example where the synchronization flag is located between the payload and the check portion, which can further achieve fast synchronization.

In an embodiment, at least two of the first synchronization mark, the second synchronization mark, and the third synchronization mark have the same length. For example, the first sync mark, the second sync mark, and the third sync mark are all the same length. The synchronization is more convenient, and the quick synchronization is favorably realized. It is understood that in other embodiments, the lengths of at least two of the first synchronization mark, the second synchronization mark, and the third synchronization mark may be different.

In an embodiment, at least two of the first synchronization flag, the second synchronization flag, and the third synchronization flag have the same value. For example, the first synchronization flag, the second synchronization flag, and the third synchronization flag all have the same value. The synchronization is more convenient, and the quick synchronization is favorably realized. It is understood that, in other embodiments, values of at least two of the first synchronization flag, the second synchronization flag, and the third synchronization flag may also be different. For example, the values of the first synchronization flag, the second synchronization flag, and the third synchronization flag are different from each other, so that it is convenient to distinguish which codeword structure the currently identified codeword structure is when synchronizing.

In an embodiment, the length of the first payload is equal to the sum of the lengths of the S first data blocks, i.e. the first payload consists of only S first data blocks, and the length of the second payload is equal to the sum of the lengths of the Q2 second data blocks, i.e. the second payload consists of only Q2 second data blocks. The length of the third payload is equal to the sum of the lengths of the Q2 third data blocks, i.e. the third payload consists of only Q2 third data blocks. In other embodiments, the length of the first payload may be greater than the length of the S first data blocks, for example, (S +1) × M, and the more data blocks 66b may be used for other indication purposes.

In one embodiment, the length of the first non-payload portion is greater than or equal to the sum of the lengths of the first synchronization flag and the first check portion, and the remaining bits of the first non-payload portion, except for the first synchronization flag and the first check portion, may be used for other indication purposes; the length of the second non-payload part is greater than or equal to the sum of the lengths of the second synchronization mark and the second check part, and the remaining bits in the second non-payload part except the second synchronization mark and the second check part can be used for other indication purposes; the length of the third non-payload portion is greater than or equal to the sum of the lengths of the third sync mark and the third check portion, and the remaining bits of the third non-payload portion, except for the third sync mark and the third check portion, may be used for other indication purposes.

In an embodiment, the length of the first non-payload portion is equal to the length of the second non-payload portion, thereby facilitating fast synchronization. In an embodiment, the first non-payload portion, the second non-payload portion and the third non-payload portion are all equal in length, thereby facilitating fast synchronization.

For each uplink burst, the ONU transmits a code stream, where the code stream includes an uplink burst structure, a head of the uplink burst structure includes a burst delimiter (end), and a tail of the uplink burst structure includes an end symbol, and the end symbol may also be referred to as an end of burst (EOB), or a tp (terminating pattern). The uplink burst structure may include only 1 first codeword structure, or may also include at least 1 second codeword structure and 1 first codeword structure, or may also include 1 third codeword structure, or may also include at least 1 second codeword structure and 1 third codeword structure. The following embodiments describe, by way of example, various codeword structures in the upper burst structure each include a payload, a synchronization flag, and a check portion, and the synchronization flag is located between the payload and the check portion. The sync mark is 32 bits for example, the payload length of the non-shortened code is 16962b for example, and the length of the check part is 3598b for example. And the synchronization marks of the three code word structures are the same.

For the shortened code, in the step S204, the shortened code is identified according to the synchronization flag, and the identified process may also be understood as a synchronization process, specifically, the synchronization mechanism of the OLT is as shown in fig. 9:

s500, the OLT receives a code stream at a physical coding sublayer, wherein the code stream comprises a burst delimiter and a first code word structure, or the code stream comprises the burst delimiter, the first code word structure and a second code word structure;

s203 includes: s501, after the burst delimiter or the second check part, the OLT identifies whether a first synchronization mark exists at the current interval position once every M bits, and counts the current identification times or the total bit number of the current interval;

s204 comprises the following steps: s502, after the OLT recognizes that the first synchronization mark exists, if the product of the current counted identification times and M is smaller than the FEC payload length, or if the current counted total bit number is smaller than the FEC payload length, executing S503;

s503, judging the currently identified code word as the first code word structure. By adopting the synchronization mechanism, the OLT side can identify the shortened codes with various lengths.

Taking M equal to 66 as an example, after the burst delimiter or after the third test part, counting the number of data blocks with the size of 66b from 0, and every time counting, judging whether the first 32 bits of the current interval position are the synchronization mark, if not, continuing to count the data blocks with the size of 66b of the current interval position. For example, from 0b to 65b, 1 data block of 66b is counted, and the number of times of counting is 1; the current interval position is 66b, whether the 66b to 97b are synchronization marks is identified, if not, 1 data block of 66b is counted from 66b to 131b, and the counting number is 2; the current interval position is 132b, then whether 132b to 163b are synchronous marks is identified, if not, counting is continued from 132 b; if the 132b th to 163b th codes are sync marks, the statistics ends, the number of times of the statistics is 2, obviously, 2 x 66<16962, and thus, the currently identified code word is the first code word structure, i.e., the shortened code.

The scheme for counting the total bit number of the current interval is similar to the above, and is not described herein again. It will be appreciated that the total number of bits of the current interval counted is equal to the product of the current count and M.

In order to further improve the reliability of the identification of the shortened code, step S502 specifically includes:

after each identification of existence of the first synchronization mark, if the product of the identification times of the current statistics and M is smaller than the FEC payload length, or if the total number of bits of the current statistics is smaller than the FEC payload length, identifying whether an end character exists after P bits are spaced, wherein the spacing position is a position behind the synchronization mark, and the difference between the first non-payload length and the first synchronization mark is P bits; taking the first codeword structure including only the first payload, the first synchronization flag, and the first parity portion as an example, the length of the first parity portion is P bits, which is 3598 bits.

And if the end character exists, judging the currently identified code word as the first code word structure. If the end symbol does not exist, returning to the position before the interval P bits, continuously executing the interval M bits, identifying whether the first synchronization mark exists once at the current interval position, and counting the current identification times or counting the total bit number of the current interval.

Taking the above example as an example, if the 132b to 163b are sync marks, it is determined whether the bit starting at 3762b is an end symbol after 3598 bits from 164b, that is, after 164b to 3761b (i.e., the first parity portion), and it is determined whether 3762b to 3791b are end symbols assuming that the length of the end symbol is 30 bits. If the end character is the end character, the currently identified code word is judged to be the first code word structure. If the data block is not the end symbol, the data blocks 132b to 163b are not synchronous marks, and if the previous judgment is wrong, 1 data block 66b is continuously counted from the data blocks 132b to 197b, and the counted number is added with 1, namely the current counted number is refreshed to be 3; the identification continues with the current interval position being 198 b.

For non-shortened codes, the synchronization mechanism of the OLT is shown in figure 9,

the code stream comprises a burst delimiter and a second code word structure, or the code stream comprises the burst delimiter, the first code word structure and the second code word structure;

after identifying the burst delimiter or the second check part, the OLT identifies whether a second synchronization mark exists at the current interval position once every M bits, and counts the current identification times or the total bit number of the current interval;

the method further comprises the following steps: s504, after the OLT identifies each second synchronization flag, if the product of the currently counted identification number and M is equal to the FEC payload length, or if the currently counted total number of bits is equal to the FEC payload length, then it determines that the currently identified codeword is the second codeword structure.

Taking M equal to 66 as an example, after the burst delimiter or after the third check portion, counting the number of data blocks of 66b size from 0, where the specific statistical details are as in the above embodiments and are not described herein again. When the counting number reaches 257 times, the current interval position is 16963b, whether 16963b to 169994 b are synchronization marks or not is judged, when the synchronization marks are detected, the product of the current identification number and 66 is 16962b, and the FEC payload length is equal to the FEC payload length, the current identified code word is of a second code word structure, and the current counting number or the current counted total bit number can be cleared. Beginning at 16942 b is an interval 3598 bits, 1699 b to 20592b are second parity portions. A new round of identification continues from 20593 b.

The third codeword structure is also a non-shortened code, and the specific identification process is the same as the second codeword structure, which is not described herein again.

It will be appreciated that the synchronization mark of the third codeword structure may be different from the synchronization mark of the second codeword structure, thereby facilitating distinguishing the third codeword structure from the second codeword structure.

The method further comprises the following steps: s505, after judging that the currently identified code word is in a second code word structure, a first code word structure or a third code word structure, the OLT clears the currently counted identification times or the currently counted total bit number;

after P bits are spaced after the currently identified second synchronization mark, continuously identifying the first code word structure or the second code word structure; wherein the difference between the first non-payload length and the length of the first synchronization flag is P bits.

The present application further provides an ONU 130.

As shown in fig. 10, the ONU includes a processor 610, a memory 620, a Medium Access Control (MAC) chip 630, a transceiver 640, and a wavelength division multiplexer 650.

The processor 610 may adopt a general Central Processing Unit (CPU), a microprocessor, an application specific integrated circuit ASIC, or at least one integrated circuit, and is configured to execute related programs to implement the technical solutions provided in the embodiments of the present application.

The Memory 620 may be a Read Only Memory (ROM), a static Memory device, a dynamic Memory device, or a Random Access Memory (RAM). The memory 620 may store an operating system and other application programs. When the technical solution provided by the embodiment of the present application is implemented by software or firmware, program codes for implementing the technical solution provided by the embodiment of the present application are stored in the memory 620 and executed by the processor 610.

In an embodiment, the processor 610 may include memory 620 internally. In another embodiment, the processor 610 and the memory 620 are two separate structures.

In one embodiment, processor 610 and MAC chip 630 may be two separate structures. In another embodiment, a MAC chip 630 may be included in processor 610. MAC chip 630 may include a physical coding sublayer and a MAC control sublayer.

The transceiver 640 may include an optical transmitter and/or an optical receiver. The optical transmitter may be used to transmit optical signals and the optical receiver may be used to receive optical signals. The light emitter may be implemented by a light emitting device such as a gas laser, a solid laser, a liquid laser, a semiconductor laser, a direct modulation laser, or the like. The optical receiver may be implemented by a photodetector, such as a photodetector or a photodiode (e.g., an avalanche diode), etc. The transceiver 640 may also include a digital-to-analog converter and an analog-to-digital converter.

The wavelength division multiplexer 650 is connected to the transceiver 640, and acts as a multiplexer when the network device transmits optical signals. When the network device receives an optical signal, the wavelength division multiplexer acts as a demultiplexer. Wavelength division multiplexers may also be referred to as optical couplers.

MAC chip 630 or processor 610 may perform the steps of the physical coding sublayer.

As can be seen from the above embodiments, the MAC chip 630 of the ONU is configured to perform steps S200, S201, S202, S300, S301, S302, S303, S400, S401, S402, S403, and S404.

For more details of the processor 610 and the MAC chip 630 when the physical coding sublayer executes the above steps, reference may be made to the description of each embodiment of the above method and the related description of the drawings, and details are not repeated here.

The embodiments of the present application also have various beneficial effects described in the above method embodiments, and are not described herein again.

The present application also provides an OLT 110.

As shown in fig. 11, the OLT includes a processor 710, a memory 720, a Media Access Control (MAC) chip 730, a transceiver 740, and a wavelength division multiplexer 750.

The processor 710 may be a general Central Processing Unit (CPU), a microprocessor, an application specific integrated circuit ASIC, or at least one integrated circuit, and is configured to execute related programs to implement the technical solutions provided in the embodiments of the present application.

The Memory 720 may be a Read Only Memory (ROM), a static Memory device, a dynamic Memory device, or a Random Access Memory (RAM). Memory 720 may store an operating system and other application programs. When the technical solution provided by the embodiment of the present application is implemented by software or firmware, program codes for implementing the technical solution provided by the embodiment of the present application are stored in the memory 720 and executed by the processor 710.

In an embodiment, processor 710 may include memory 720 therein. In another embodiment, processor 710 and memory 720 are two separate structures.

In one embodiment, processor 710 and MAC chip 730 may be two separate structures. In another embodiment, MAC chip 730 may be included in processor 710. The MAC chip 730 may include a physical coding sublayer and a MAC control sublayer.

The transceiver 740 may include an optical transmitter and/or an optical receiver. The optical transmitter may be used to transmit optical signals and the optical receiver may be used to receive optical signals. The light emitter may be implemented by a light emitting device such as a gas laser, a solid laser, a liquid laser, a semiconductor laser, a direct modulation laser, or the like. The optical receiver may be implemented by a photodetector, such as a photodetector or a photodiode (e.g., an avalanche diode), etc. The transceiver 740 may also include a digital-to-analog converter and an analog-to-digital converter.

The wavelength division multiplexer 750 is connected to the transceiver 740, and functions as a multiplexer when the network device transmits an optical signal. When the network device receives an optical signal, the wavelength division multiplexer acts as a demultiplexer. Wavelength division multiplexers may also be referred to as optical couplers.

MAC chip 730 or processor 710 may perform the steps of the physical coding sublayer.

As can be seen from the above embodiments, the MAC chip 730 of the OLT is configured to perform steps S203, S204, S205, S206, S304, S305, S306, S307, S405, S406, S407, S408, and steps S500, S501, S502, S503, S504, and S505.

For more details of the processor 710 and the MAC chip 730 when the physical coding sublayer executes the above steps, reference may be made to the description of the embodiments of the method and the accompanying drawings, which are not described herein again.

The present application further provides a data encoding apparatus in a PON system, which may be integrated in the ONU in the above embodiments, for example, may be integrated in a MAC chip of the ONU, or integrated in a processor, or integrated in a DSP chip. As shown in fig. 12, the apparatus includes: a receiving module 810, a forward error correction coding module 820 and a generating module 830.

As can be seen from the above embodiments, the receiving module 810 is configured to perform steps S200, S300, and S400, the forward error correction coding module 820 is configured to perform steps S140, S201, S302, and S403, and the generating module 830 is configured to perform steps S202, S303, and S404.

The apparatus further comprises a transcoding module 840, wherein the transcoding module 840 is configured to perform steps S301 and S402.

The apparatus further comprises an extension module 850, the extension module 850 being configured to perform step S401.

For more details of the steps executed by each module of the apparatus, reference may be made to the description of each embodiment of the method and the accompanying drawings, which are not described herein again.

The present application further provides a data decoding apparatus in a PON system, which may be integrated in the OLT in the above embodiments, for example, may be integrated in a MAC chip of the OLT, or integrated in a processor, or integrated in a DSP chip. As shown in fig. 13, the apparatus includes: a receiving module 910, a synchronization module 920, an extraction module 930, and a forward error correction decoding module 940.

As can be seen from the above embodiments, the receiving module 910 is configured to perform steps S203, S304, S405, and S500, the synchronizing module 920 is configured to perform steps S204, S305, S406, S501, S502, S503, S504, and S505, the extracting module 930 is configured to perform steps S205, S306, and S407, and the forward error correction decoding module 940 is configured to perform steps S206, S307, and S408.

The present application also provides an optical line terminal, where the optical line terminal includes the data encoding apparatus in any of the above embodiments, or the optical line terminal includes the data decoding apparatus in any of the above embodiments.

The present application further provides an optical network unit, where the optical network unit includes the data encoding device of any of the above embodiments, or the optical network unit includes the data decoding device of any of the above embodiments.

The present application further provides a PON system, which includes the above optical line terminal and the optical network unit.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the present application are all or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

The above description is only an example of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for encoding data in a PON system, the method comprising:

receiving S first data blocks at a physical coding sublayer, wherein the length of each first data block is M bits, and M × S is smaller than the FEC payload length of a forward error correction coding FEC code pattern;

performing FEC encoding on the S first data blocks on the physical encoding sublayer according to the FEC code pattern to generate a first check part, wherein the FEC payload length is integral multiple of M;

generating a first codeword structure at the physical coding sublayer, the first codeword structure comprising a first payload and a first non-payload portion, the first payload comprising the S first data blocks, the first payload having a length less than the FEC payload length; the first non-payload portion includes the first check portion and a first synchronization flag, and the lengths of the first payload and the first non-payload portion are each an integer multiple of M.

2. The method of claim 1, wherein the method further comprises:

receiving Q1 of said first data blocks at the physical coding sublayer, M x Q1> FEC payload length;

transcoding the Q1 first data blocks in the physical coding sublayer to generate Q2 second data blocks, wherein each second data block has a length of N bits and N > M; transcoding every t of said first data blocks into 1 of said second data blocks, t >1, and Q1 ═ t × FEC payload length/N, Q1 ═ t × Q2;

FEC encoding is carried out on the Q2 second data blocks on the physical coding sublayer according to the FEC code patterns to generate second check parts;

generating a second codeword structure at the physical coding sublayer, the second codeword structure comprising a second payload and a second non-payload portion, the second payload comprising the Q2 second data blocks, the second payload having a length equal to the FEC payload length; the second non-payload portion includes the second parity portion and a second synchronization flag, and the length of the second non-payload portion is an integer multiple of M.

3. The method of claim 2, wherein each third data block is generated by t x M bits of data transcoding, t >1, each of the third data blocks being N bits in length, the method further comprising:

receiving Q3 of the first data blocks at the physical coding sublayer, M x Q3 ≧ FEC payload length, and Q3< Q1;

performing extension processing on the Q3 first data blocks in the physical coding sublayer, so that the total length of the extended data is equal to Q1M;

transcoding the expanded data in the physical coding sublayer to generate Q2 third data blocks;

performing FEC encoding on the Q2 third data blocks in the physical coding sublayer according to the FEC code pattern to generate a third check part;

generating a second codeword structure at the physical coding sublayer, the second codeword structure comprising a third payload and a third non-payload portion, the third payload comprising the Q2 third data blocks, the third payload having a length equal to the FEC payload length; the third non-payload portion includes the third parity portion and a third synchronization flag, and the length of the third non-payload portion is an integer multiple of M.

4. The method according to claim 2 or 3, wherein the first synchronization mark and the second synchronization mark have the same length or the first synchronization mark and the second synchronization mark have the same value.

5. The method of claim 2, wherein the length of the first non-payload portion is greater than or equal to the sum of the lengths of the first synchronization flag and the first parity portion, and the length of the second non-payload portion is greater than or equal to the sum of the lengths of the second synchronization flag and the second parity portion.

6. The method of claim 2, wherein the length of the first non-payload portion is equal to the length of the second non-payload portion.

7. A method for decoding data in a PON system, the method comprising:

receiving a first codeword structure at a physical coding sublayer, wherein the first codeword structure comprises a first payload and a first non-payload portion, the first non-payload portion comprises a first check portion and a first synchronization flag, the first payload comprises at least 1 first data block, the length of each first data block is M bits, the length of each first payload and the length of each first non-payload portion are both integer multiples of M, the FEC payload length of a forward error correction coding (FEC) pattern is integer multiples of M, and the length of each first payload is smaller than the FEC payload length;

identifying, at the physical coding sublayer, the first codeword structure based on the first synchronization flag;

extracting the first payload and the first check part from the physical coding sublayer;

and carrying out forward error correction decoding on the first payload according to the FEC code pattern and the first check part in the physical coding sublayer.

8. The method of claim 7, wherein the method further comprises:

receiving a second codeword structure at the physical coding sublayer, the second codeword structure comprising a second payload and a second non-payload portion, the second non-payload portion comprising a second parity portion and a second synchronization flag, the length of the second payload being equal to the FEC payload length, the second non-payload portion being an integer multiple of M;

identifying, at the physical coding sublayer, the second codeword structure according to the second synchronization flag;

extracting the second payload and the second parity portion at the physical coding sublayer;

and carrying out forward error correction decoding on the second payload according to the FEC code pattern and the second check part in the physical coding sublayer.

9. The method of claim 8, wherein the first synchronization mark and the second synchronization mark are the same length; or the first synchronization mark and the second synchronization mark have the same value.

10. The method of claim 8 or 9, wherein the length of the first non-payload portion is equal to the length of the second non-payload portion.

11. The method of claim 8,

the receiving a first codeword structure comprises: receiving a code stream, wherein the code stream comprises a burst delimiter and the first code word structure, or the code stream comprises the burst delimiter, the first code word structure and the second code word structure;

said identifying said first codeword structure according to said first synchronization flag comprises:

after the burst delimiter or the second check part, identifying whether the first synchronization mark exists at the current interval position once every M bits, and counting the current identification times or the total bit number of the current interval;

and after the first synchronization mark is identified to exist, if the product of the identification times of the current statistics and M is smaller than the FEC payload length, or if the total bit number of the current statistics is smaller than the FEC payload length, judging the current identified code word as the first code word structure.

12. The method of claim 11, wherein the codestream further includes an end-pointer;

after the first synchronization flag is identified to exist, if the product of the identification number of the current statistics and M is smaller than the FEC payload length, or if the total number of the current statistics is smaller than the FEC payload length, determining that the currently identified codeword is the first codeword structure includes:

after each identification of existence of the first synchronization mark, if the product of the identification times of the current statistics and M is smaller than the FEC payload length, or if the total number of bits of the current statistics is smaller than the FEC payload length, identifying whether the end character exists after P bits are spaced, wherein the difference between the length of the first non-payload part and the length of the first synchronization mark is P bits;

and if the end character exists, judging the currently identified code word as the first code word structure.

13. The method of claim 8,

the receiving a second codeword structure comprises: receiving a code stream, wherein the code stream comprises a burst delimiter and the second code word structure, or the code stream comprises the burst delimiter, the first code word structure and the second code word structure;

the identifying the second codeword structure according to the second synchronization flag comprises:

after the burst delimiter or the second check part is identified, identifying whether the second synchronization mark exists at the current interval position once every M bits, and counting the current identification times or counting the total bit number of the current interval;

and after the second synchronization mark is identified to exist, if the product of the identification times and M counted currently is equal to the FEC payload length, or if the total bit number counted currently is equal to the FEC payload length, judging that the currently identified code word is the second code word structure.

14. An apparatus for encoding data in a PON system, the apparatus comprising:

a forward error correction coding and decoding module, configured to perform FEC coding on the S first data blocks according to the FEC code patterns to generate first check portions, where the FEC payload length is an integer multiple of M;

a generating module, configured to generate a first codeword structure, where the first codeword structure includes a first payload and a first non-payload portion, the first payload includes the S first data blocks, and a length of the first payload is smaller than a length of the FEC payload; the first non-payload portion includes the first check portion and a first synchronization flag, and the lengths of the first payload and the first non-payload portion are each an integer multiple of M.

15. The apparatus of claim 14,

the receiving module is further configured to receive Q1 of the first data blocks, M × Q1> FEC payload length;

the device further comprises a transcoding module, wherein the transcoding module is used for transcoding the Q1 first data blocks to generate Q2 second data blocks, the length of each second data block is N bits, and N > M; transcoding every t of said first data blocks into 1 of said second data blocks, t >1, and Q1 ═ t × FEC payload length/N, Q1 ═ t × Q2;

the forward error correction coding and decoding module is further configured to perform FEC coding on the Q2 second data blocks according to the FEC code patterns to generate second check parts;

the generating module is further configured to generate a second codeword structure, where the second codeword structure includes a second payload and a second non-payload portion, where the second payload includes the Q2 second data blocks, and where the length of the second payload is equal to the FEC payload length; the second non-payload portion includes the second parity portion and a second synchronization flag, and the length of the second non-payload portion is an integer multiple of M.

16. The apparatus of claim 15, wherein each third data block is generated by t x M bits of data transcoding, t >1, each said third data block being N bits in length;

the receiving module is further used for receiving Q3 first data blocks, M × Q3 is larger than or equal to FEC payload length, and Q3 is smaller than Q1;

the device further comprises an expansion module, configured to perform expansion processing on the Q3 first data blocks, so that a total expanded data length is equal to Q1 × M;

the transcoding module is further used for transcoding the expanded data to generate Q2 third data blocks;

the forward error correction coding and decoding module is further configured to perform FEC coding on the Q2 third data blocks according to the FEC code patterns to generate third check portions;

the generating module is further configured to generate a second codeword structure, where the second codeword structure includes a third payload and a third non-payload portion, where the third payload includes the Q2 third data blocks, and the length of the third payload is equal to the FEC payload length; the third non-payload portion includes the third parity portion and a third synchronization flag, and the length of the third non-payload portion is an integer multiple of M.

17. The apparatus according to claim 15 or 16, wherein the first synchronization flag and the second synchronization flag have the same length or the first synchronization flag and the second synchronization flag have the same value.

18. The apparatus of claim 15, wherein the length of the first non-payload portion is equal to the length of the second non-payload portion.

19. An apparatus for decoding data in a PON system, the apparatus comprising:

a receiving module, configured to receive a first codeword structure, where the first codeword structure includes a first payload and a first non-payload portion, where the first non-payload portion includes a first check portion and a first synchronization flag, the first payload includes at least 1 first data block, a length of each first data block is M bits, lengths of the first payload and the first non-payload portion are both integer multiples of M, a FEC payload length of a forward error correction coding, FEC, pattern is integer multiples of M, and the length of the first payload is smaller than the FEC payload length;

a synchronization module for identifying the first codeword structure according to the first synchronization flag;

an extraction module, configured to extract the first payload and the first check portion;

and a forward error correction coding and decoding module, configured to perform forward error correction coding on the first payload according to the FEC code pattern and the first check portion.

20. The apparatus of claim 19,

the receiving module is further configured to receive a second codeword structure, where the second codeword structure includes a second payload and a second non-payload portion, where the second non-payload portion includes a second parity portion and a second synchronization flag, where a length of the second payload is equal to the FEC payload length, and the second non-payload portion is an integer multiple of M;

the synchronization module is further configured to identify the second codeword structure according to the second synchronization flag;

the extraction module is further configured to extract the second payload and the second parity portion;

the forward error correction coding and decoding module is further configured to perform forward error correction coding on the second payload according to the FEC code pattern and the second check portion.

21. The apparatus of claim 20, wherein the first synchronization flag and the second synchronization flag have the same length or the first synchronization flag and the second synchronization flag have the same value.

22. The apparatus of claim 20 or 21,

the receiving module is further configured to receive a code stream, where the code stream includes a burst delimiter and the first codeword structure, or the code stream includes the burst delimiter, the first codeword structure, and the second codeword structure;

the synchronization module is further configured to identify whether the first synchronization flag exists at a current interval position once every M bits after the burst delimiter or after the second check part, and count the current identification number of times or count the total number of bits of the current interval;

the apparatus further includes a determining module, configured to determine, after each identification that the first synchronization flag exists, that the currently identified codeword is the first codeword structure if a product of the currently counted identification number and M is smaller than the FEC payload length, or if the currently counted total number of bits is smaller than the FEC payload length.

23. The apparatus of claim 20 or 21,

the receiving module is further configured to receive a code stream, where the code stream includes a burst delimiter and the second codeword structure, or the code stream includes the burst delimiter, the first codeword structure, and the second codeword structure;

the synchronization module is further configured to identify whether the second synchronization flag exists at a current interval position once every M bits after identifying the burst delimiter or the second check part, and count a current identification number of times or a total number of bits of a current interval;

the apparatus further includes a determining module, configured to determine, after each second synchronization flag is identified to exist, that the currently identified codeword is the second codeword structure if a product of the currently counted number of identifications and M is equal to the FEC payload length, or if the currently counted total number of bits is equal to the FEC payload length.

24. An optical line terminal, characterised in that it comprises an apparatus according to any of claims 19 to 23.

25. An optical network unit, characterized in that it comprises an apparatus according to any of claims 14 to 18.

26. A PON system, characterized in that the PON system comprises an optical line terminal according to claim 24 and an optical network unit according to claim 25.