CN110349870A - Wafer stage chip encapsulating structure and preparation method thereof - Google Patents
Wafer stage chip encapsulating structure and preparation method thereof Download PDFInfo
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- CN110349870A CN110349870A CN201810300763.6A CN201810300763A CN110349870A CN 110349870 A CN110349870 A CN 110349870A CN 201810300763 A CN201810300763 A CN 201810300763A CN 110349870 A CN110349870 A CN 110349870A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Present invention discloses a kind of wafer stage chip encapsulating structures and preparation method thereof, production method includes forming the first groove and the second groove in the passivation layer of chip on wafer, first groove exposes metal gasket, second groove surrounds the first groove, and forms ubm layer and salient point on this basis.By means of being centered around the second groove of the first groove vicinity, so that reducing the erosion along chip surface to the first metal layer when etching, and salient point is able to enter the second groove upon reflowing, to improve shearing, prevents from falling off, the size that may insure salient point obtains the salient point of high quality.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of wafer stage chip encapsulating structure and preparation method thereof.
Background technique
In recent years, since the microcircuit production of chip develops towards high integration, so, chip package also needs Xiang Gaogong
Rate, high density, the frivolous direction with microminiaturization are developed.To cooperate these demands, many different packaged types, example are produced
Such as, ball bar battle array is chip size packages (Chip Scale Package, CSP), more to encapsulation (Ball grid array, BGA)
Chip module encapsulates (Multi Chip Module package, MCM package), flip-over type encapsulates (Flip Chip
Package, FCP), coil type encapsulation (Tape Carrier Package, TCP) and wafer stage chip encapsulate (Wafer Level
Chip Scale Package, WLCSP) etc..
Wafer stage chip encapsulation is a trend in method for packaging semiconductor, and wafer stage chip encapsulation is with full wafer wafer
Encapsulated object, thus packaging and testing are both needed to complete before not yet cutting crystal wafer, are a kind of encapsulation technologies of high integration, such as
This can save the production process such as filler, assembling, glutinous brilliant and routing, can largely reduce cost of labor, shorten manufacturing time.
But wafer stage chip encapsulation is also not without disadvantage, such as the stability of salient point needs to be optimized.
Summary of the invention
The purpose of the present invention is to provide a kind of wafer stage chip encapsulating structures and preparation method thereof, improve wafer stage chip
The quality of encapsulating structure.
In order to solve the above technical problems, the present invention provides a kind of production method of wafer stage chip encapsulating structure, comprising:
A chip is provided, the chip is formed on wafer, and metal gasket and the covering metal are formed on the chip
The passivation layer of pad and the chip；
The first groove and the second groove are formed in the passivation layer, first groove exposes the metal gasket, institute
The second groove is stated around first groove；
The first metal layer, the thickness of the first metal layer are formed on the passivation layer and the metal gasket exposed
Less than the depth of first groove；
Photoresist is formed on the first metal layer and forms opening in the photoresist, exposes first gold medal
Belong to layer, the opening range accommodates first groove and second groove；
Second metal layer is formed on the first metal layer in said opening；
The first metal layer of removal photoresist and etching by second metal layer covering does not expose the passivation layer, carves
The first metal layer and the second metal layer after erosion is as ubm layer；And
Placing solder ball on the ubm layer and flowing back becomes salient point.
Optionally, for the production method of the wafer stage chip encapsulating structure, the chip is formed on wafer, institute
Stating has at least one chip on wafer；Flow back become salient point after, further includes: to the wafer cut with isolate to
A few chip.
Optionally, for the production method of the wafer stage chip encapsulating structure, second groove is an annular
Groove.
Optionally, for the production method of the wafer stage chip encapsulating structure, the opening size of second groove
Greater than bottom size, there is inclined side wall.
Optionally, for the production method of the wafer stage chip encapsulating structure, the first metal layer includes copper, nickel
Or combination.
Optionally, for the production method of the wafer stage chip encapsulating structure, described first is formed using galvanoplastic
Metal layer.
Optionally, for the production method of the wafer stage chip encapsulating structure, the material of the second metal layer with
The material of the solder ball is identical.
Optionally, for the production method of the wafer stage chip encapsulating structure, described second is formed using galvanoplastic
Metal layer.
The present invention also provides a kind of wafer stage chip encapsulating structures, comprising:
One chip, the chip are formed on wafer, metal gasket on the chip and are located at the chip and institute
The passivation layer on metal gasket is stated, the passivation layer has the first groove and the second groove, and first groove exposes the gold
Belong to pad, second groove surrounds first groove；
Ubm layer on the metal gasket and on the passivation layer；And
Salient point on the ubm layer, the salient point include interconnecting piece and fixed part, and the interconnecting piece is logical
It crosses the ubm layer to be electrically connected with the metal gasket, the fixed position is in second groove.
Optionally, for the wafer stage chip encapsulating structure, second groove is an annular groove.
Optionally, for the wafer stage chip encapsulating structure, the opening size of second groove is greater than bottom ruler
It is very little, there is inclined side wall.
Optionally, for the wafer stage chip encapsulating structure, the ubm layer includes copper, nickel or combination.
In the production method of wafer stage chip encapsulating structure provided by the invention, comprising: a chip, the chip shape are provided
At the passivation layer on wafer, being formed with metal gasket and the covering metal gasket and the chip on the chip；Described blunt
Change and form the first groove and the second groove in layer, first groove exposes the metal gasket, and second groove surrounds institute
State the first groove；The first metal layer is formed on the passivation layer and the metal gasket exposed, the first metal layer
Thickness is less than the depth of first groove；Photoresist is formed on the first metal layer and is formed in the photoresist opens
Mouthful, the first metal layer is exposed, the opening range accommodates first groove and second groove；In the opening
In the first metal layer on form second metal layer；It removes photoresist and etches first gold medal not covered by second metal layer
Belong to layer and expose the passivation layer, the first metal layer and the second metal layer after etching are as ubm layer；And
Placing solder ball on the ubm layer and flowing back becomes salient point.Then, by means of being centered around the first groove vicinity
Second groove, so that reduce the erosion along chip surface to the first metal layer when etching, and salient point upon reflowing can be into
Enter the second groove, to improve shearing, prevent from falling off, it can be ensured that the size of salient point obtains the salient point of high quality.
Detailed description of the invention
Fig. 1 is a kind of schematic diagram of wafer stage chip encapsulating structure；
Fig. 2 is the flow chart of the production method of wafer stage chip encapsulating structure in one embodiment of the invention；
Fig. 3 is to provide the schematic diagram of chip in one embodiment of the invention；
Fig. 4 is the schematic diagram that the first groove and the second groove are formed in one embodiment of the invention；
Fig. 5 is the schematic diagram that the first metal layer and second metal layer are formed in one embodiment of the invention；
Fig. 6 is the schematic diagram performed etching in one embodiment of the invention；
Fig. 7 is the schematic diagram of the wafer stage chip encapsulating structure obtained in one embodiment of the invention.
Specific embodiment
Wafer stage chip encapsulating structure of the invention and preparation method thereof is carried out below in conjunction with schematic diagram more detailed
Description, which show the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify described herein
Invention, and still realize advantageous effects of the invention.Therefore, following description should be understood as those skilled in the art's
It is widely known, and it is not intended as limitation of the present invention.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
In the following description, it should be appreciated that when layer (or film), region, pattern or structure be referred to as substrate, layer (or
Film), region, pad and/or when pattern "upper", it can be on another layer or substrate, and/or there may also be insert
Enter layer.In addition, it is to be appreciated that when layer be referred to as at another layer of "lower", it can under another layer, and/or
There may also be one or more insert layers.Furthermore it is possible to be carried out based on attached drawing about the reference in each layer "up" and "down".
Inventors have found that wafer stage chip encapsulating structure is easy to happen the problem of ball, as shown in Figure 1, a kind of wafer scale
Chip-packaging structure includes: chip 1, is formed with metal gasket 2 thereon, and passivation layer 3 is located on chip 1 and there is opening to expose portion
Divide metal gasket 2, ubm layer (Under Bump Metal, UBM) is formed in the opening and portion of the passivating layer 3, convex
Point (Bump) 6 is fastened on chip 1 by ubm layer, and is electrically connected with metal gasket 2.Ubm layer includes
The first metal layer 4 and second metal layer 5, when etching forms ubm layer, due to being the etching for the first metal layer,
Therefore high compared to 5 etching selection ratio of second metal layer, therefore it is easy to happen transversal erosion, cause the first metal layer 4 to inside contract, such as dotted line
Shown in frame.In this way after forming salient point 6, shearing (shear force) is easy to become smaller, on the one hand lead to salient point 6
Size (such as height, the area etc. on chip) becomes smaller, and on the other hand, is easy to fall off, falls ball phenomenon.
Based on this, the production method for inventors herein proposing a kind of wafer stage chip encapsulating structure, in one embodiment, such as
Shown in Fig. 2, the production method of wafer stage chip encapsulating structure of the invention includes:
Step S11 provides a chip, and the chip is formed on wafer, and metal gasket and covering are formed on the chip
The passivation layer of the metal gasket and the chip；
Step S12, forms the first groove and the second groove in the passivation layer, and first groove exposes the gold
Belong to pad, second groove surrounds first groove；
Step S13 forms the first metal layer, first metal on the passivation layer and the metal gasket exposed
The thickness of layer is less than the depth of first groove；
Step S14 forms photoresist on the first metal layer and forms opening in the photoresist, exposes institute
The first metal layer is stated, the opening range accommodates first groove and second groove；
Step S15 forms second metal layer on the first metal layer in said opening；
Step S16, removal photoresist and etching are not exposed by the first metal layer that second metal layer covers described
Passivation layer, the first metal layer and the second metal layer after etching are as ubm layer；And
Step S17, solder ball is placed on the ubm layer and is flowed back becomes salient point.
2,3~7 pairs of wafer stage chip encapsulating structures and preparation method thereof of the invention are retouched in detail with reference to the accompanying drawing
It states.
Referring to FIG. 3, providing a chip 10 for step S11, the chip 10 is formed on wafer, the chip 10
On be formed with the passivation layer 20 of metal gasket 11 and the covering metal gasket 11 and the chip 10.
In one embodiment, there is at least one chip 10, wherein Fig. 3 illustrates only one on the wafer.
The technique that the metal gasket 11 and the passivation layer 20 are formed on the chip 10 is that those skilled in the art are public
Know and help art, as an optional process of the invention, can be and form a metal layer on chip 10 first, the metal layer is
Al (aluminium), Cu (copper) or their alloy are constituted, and the metal layer can be for using physical vapour deposition (PVD) (PVD) method system
It is standby, lithography and etching technology pattern metal category layer is then used, the metal gasket 11 is formed.
Then passivation layer 20 is formed on the chip 10 and the metal gasket 11, the passivation layer 20 can be macromolecule
Polymer, e.g. benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), polyimides (PI), the double oxazoles of polyparaphenylene benzo
(PBO) etc. high molecular polymers, passivation layer 20 is selected as polyimides and the double oxazoles of polyparaphenylene benzo in the present embodiment,
The passivation layer 20 is to be prepared using spin coating method.
Then, referring to FIG. 4, for step S12, the first groove 31 and the second groove are formed in the passivation layer 20
32, first groove 31 exposes the metal gasket 11, and second groove 32 surrounds first groove 31.
This step S12 can be completed using photoetching and developing process.
In the present invention, first groove 31 is in the subsequent connection that will be carried out between salient point and metal gasket 11, and
Second groove 32 can control etching degree when etching forms ubm layer.
Second groove 32 for example can be an annular groove, it is of course also possible to be multiple groove gap arrangements,
In comparison, an annular groove preparation is simple, and effect is more preferable.
From fig. 4, it can be seen that in one embodiment, the opening size of second groove 32 is greater than bottom size, has and incline
Oblique side wall.The metal layer formed after as a result, can be extended downwardly along side wall, then consumption when etching is also mainly along this gold
Belong to the layer consumption (i.e. towards chip 10) downwards, so that laterally (i.e. along 10 upper surface of chip) consumption becomes smaller.
In one embodiment, the depth of second groove 32 is less than the depth of first groove 31.
Referring to FIG. 5, forming first on the passivation layer 20 and the metal gasket 11 exposed for step S13
Metal layer, the thickness of the first metal layer are less than the depth of first groove.That is, the first layer covering described first is recessed
The side wall and bottom wall of slot 31, the side wall of second groove 32 and bottom wall and the passivation layer 20.
The first metal layer can be completed using electroplating technology, further, it is also possible to using other forms, such as sputter.
In one embodiment, the first metal layer may include copper, nickel or combinations thereof.For example, being shown as wrapping in Fig. 5
Include layers of copper 41 and nickel layer 42 thereon.The first metal layer can prevent the material for being subsequently formed salient point from diffusing to metal gasket 11
In.
With continued reference to FIG. 5, forming photoresist 30 on the first metal layer and in the photoetching for step S14
Opening is formed in glue, exposes the first metal layer, and the opening range accommodates first groove and second groove.
This step can be completed using the prior art.
With continued reference to FIG. 5, forming second metal layer 51 on the first metal layer in said opening for step S15.
In one embodiment, the second metal layer 51 is formed using electroplating technology.
The material of the second metal layer 51 is identical as the material of the solder ball (namely salient point).For example, may include
Tin (Sn), silver-colored (Ag) etc..
The second metal layer 51, can make the first metal layer below not oxidized, improve electric conductivity and can
By property.In addition it can improve the adhesive force of the first metal layer and salient point, and in reflux course, second metal layer 51 has
Good temperatureization effect, improves the quality for forming salient point.
Here, the second metal layer 51 can be a thin layer, after its formation, can still retain or to show first recessed
The basic configuration of slot and the second groove.
Then, it referring to FIG. 6, for step S16, removes photoresist and etches described the not covered by second metal layer
One metal layer exposes the passivation layer 20, and the first metal layer and the second metal layer after etching are as metal under salient point
Layer.
In one embodiment, the removal of photoresist is completed using wet etching.
Etching first metal layer can also be completed using wet etching.For example, it may be spraying acid solution or placing wafer
Method in acid solution removes the first metal layer of the chip surface other than 51 overlay area of second metal layer, to expose
Passivation layer 20.
In etching first metal layer, the case where being easy to appear over etching (over etch), is generally difficult to ensure just to
The first metal layer removal other than 51 overlay area of second metal layer, can generate lateral etching, form notch 60.However by Fig. 6
In as it can be seen that over etching occur when, etching along the first metal layer move towards carry out, i.e., the second groove side-walls occur,
Then it is understood that although generating over etching, since etching direction Y is towards chip 10, actually on chip 10
The distance of the first metal layer consumed on the direction X of surface is simultaneously little, that is to say, that influence of the over etching to the first metal layer
It is smaller.
Later, referring to FIG. 7, for step S17, solder ball is placed on the ubm layer and is flowed back becomes convex
Point 50.
This step can be in reflow ovens, flows back by heat preservation, forms the salient point 50.
At this time, on the one hand, the contact area base due to reducing the consumption of the X-direction of the first metal layer, with salient point
This available guarantee.On the other hand, due to the presence of the second groove, salient point forms fixed part in the second groove after reflux
54, facilitate fixed salient point 50.
The salient point 50 then forms interconnecting piece in the first groove, by the first metal layer and second metal layer, realize with
Connection between metal gasket 11.
Since the material of second metal layer 20 is identical as the salient point 50, the material of salient point can be flowed into notch 60
Matter, and the second metal layer 20 can be melted with the salient point 50 and is integrated.
The present invention can only may insure the size of salient point 50, prevent from falling off, and obtain the salient point 50 of high quality.
Later, the wafer can also be cut to isolate at least one described chip.
Based on the above process, the present invention obtains a kind of wafer stage chip encapsulating structure, comprising:
One chip 10, metal gasket 11 on the chip 10 and on the chip 10 and the metal gasket 11
Passivation layer 20, the passivation layer 20 have the first groove and the second groove, and first groove exposes the metal gasket 11, institute
The second groove is stated around first groove；Ubm layer on the metal gasket 11 and on the passivation layer 20；
And the salient point 50 on the ubm layer, the salient point 50 include interconnecting piece 53 and fixed part 54, the connection
Portion 53 is electrically connected by the ubm layer with the metal gasket 11, and the fixed part 54 is located in second groove.
In one embodiment, second groove is an annular groove.
In one embodiment, the opening size of second groove is greater than bottom size, has inclined side wall.
In one embodiment, the ubm layer includes copper, nickel or combinations thereof.
In conclusion in the production method of wafer stage chip encapsulating structure provided by the invention, comprising: a chip is provided,
The chip is formed on wafer, and the passivation of metal gasket and the covering metal gasket and the chip is formed on the chip
Layer；Forming the first groove and the second groove in the passivation layer, first groove exposes the metal gasket, and described second
Groove surrounds first groove；Form the first metal layer on the passivation layer and the metal gasket that exposes, described the
The thickness of one metal layer is less than the depth of first groove；Photoresist is formed on the first metal layer and in the photoetching
Opening is formed in glue, exposes the first metal layer, and the opening range accommodates first groove and second groove；
Second metal layer is formed on the first metal layer in said opening；It removes photoresist and etches not by second metal layer covering
The first metal layer exposes the passivation layer, and the first metal layer and the second metal layer after etching are as golden under salient point
Belong to layer；And solder ball is placed on the ubm layer and is flowed back as salient point.Then, recessed by means of being centered around first
The second groove around slot, so that reducing the erosion along chip surface to the first metal layer, and salient point is flowing back when etching
After be able to enter the second groove, to improve shearing, prevent from falling off, it can be ensured that the size of salient point obtains the salient point of high quality.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (12)
1. a kind of production method of wafer stage chip encapsulating structure characterized by comprising
One chip is provided, the chip is formed on wafer, be formed on the chip metal gasket and the covering metal gasket and
The passivation layer of the chip；
Forming the first groove and the second groove in the passivation layer, first groove exposes the metal gasket, and described
Two grooves surround first groove；
The first metal layer is formed on the passivation layer and the metal gasket exposed, the thickness of the first metal layer is less than
The depth of first groove；
Photoresist is formed on the first metal layer and forms opening in the photoresist, exposes first metal
Layer, the opening range accommodate first groove and second groove；
Second metal layer is formed on the first metal layer in said opening；
Removal photoresist simultaneously etches and does not expose the passivation layer by the first metal layer that second metal layer covers, after etching
The first metal layer and the second metal layer as ubm layer；And
Placing solder ball on the ubm layer and flowing back becomes salient point.
2. the production method of wafer stage chip encapsulating structure as described in claim 1, which is characterized in that have on the wafer
At least one chip；After flowing back as salient point, further includes: cut the wafer to isolate at least one described core
Piece.
3. the production method of wafer stage chip encapsulating structure as described in claim 1, which is characterized in that second groove is
One annular groove.
4. the production method of wafer stage chip encapsulating structure as described in claim 1, which is characterized in that second groove
Opening size is greater than bottom size, has inclined side wall.
5. the production method of wafer stage chip encapsulating structure as described in claim 1, which is characterized in that the first metal layer
Including copper, nickel or combination.
6. the production method of wafer stage chip encapsulating structure as described in claim 1, which is characterized in that formed using galvanoplastic
The first metal layer.
7. the production method of wafer stage chip encapsulating structure as described in claim 1, which is characterized in that the second metal layer
Material it is identical as the material of the solder ball.
8. the production method of wafer stage chip encapsulating structure as described in claim 1, which is characterized in that formed using galvanoplastic
The second metal layer.
9. a kind of wafer stage chip encapsulating structure characterized by comprising
One chip, the chip are formed on wafer, metal gasket on the chip and are located at the chip and the gold
Belonging to the passivation layer on pad, the passivation layer has the first groove and the second groove, and first groove exposes the metal gasket,
Second groove surrounds first groove；
Ubm layer on the metal gasket and on the passivation layer；And
Salient point on the ubm layer, the salient point include interconnecting piece and fixed part, and the interconnecting piece passes through institute
It states ubm layer to be electrically connected with the metal gasket, the fixed position is in second groove.
10. wafer stage chip encapsulating structure as claimed in claim 9, which is characterized in that second groove is an annular
Groove.
11. wafer stage chip encapsulating structure as claimed in claim 9, which is characterized in that the opening size of second groove
Greater than bottom size, there is inclined side wall.
12. wafer stage chip encapsulating structure as claimed in claim 9, which is characterized in that the ubm layer include copper,
Nickel or combination.
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| CN201810300763.6A CN110349870A (en) | 2018-04-04 | 2018-04-04 | Wafer stage chip encapsulating structure and preparation method thereof |
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| CN201810300763.6A CN110349870A (en) | 2018-04-04 | 2018-04-04 | Wafer stage chip encapsulating structure and preparation method thereof |
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| US6426556B1 (en) * | 2001-01-16 | 2002-07-30 | Megic Corporation | Reliable metal bumps on top of I/O pads with test probe marks |
| CN1503328A (en) * | 2002-11-25 | 2004-06-09 | 矽品精密工业股份有限公司 | Semiconductor device with welding block button metallization structure and mfg process |
| CN101136383A (en) * | 2006-06-15 | 2008-03-05 | 索尼株式会社 | Electronic component, semiconductor device employing same, and method for manufacturing electronic component |
| KR20110114155A (en) * | 2010-04-13 | 2011-10-19 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and fabricating method thereof |
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2018
- 2018-04-04 CN CN201810300763.6A patent/CN110349870A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6426556B1 (en) * | 2001-01-16 | 2002-07-30 | Megic Corporation | Reliable metal bumps on top of I/O pads with test probe marks |
| CN1503328A (en) * | 2002-11-25 | 2004-06-09 | 矽品精密工业股份有限公司 | Semiconductor device with welding block button metallization structure and mfg process |
| CN101136383A (en) * | 2006-06-15 | 2008-03-05 | 索尼株式会社 | Electronic component, semiconductor device employing same, and method for manufacturing electronic component |
| KR20110114155A (en) * | 2010-04-13 | 2011-10-19 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and fabricating method thereof |
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