CN110347031A - A kind of high-precision amplitude time converting circuit of Pixel-level - Google Patents
A kind of high-precision amplitude time converting circuit of Pixel-level Download PDFInfo
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- CN110347031A CN110347031A CN201910715901.1A CN201910715901A CN110347031A CN 110347031 A CN110347031 A CN 110347031A CN 201910715901 A CN201910715901 A CN 201910715901A CN 110347031 A CN110347031 A CN 110347031A
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
The invention discloses a kind of high-precision amplitude time converting circuits of Pixel-level.The present invention realizes a kind of high-precision amplitude time converting circuit of Pixel-level, i.e., is integrated with an amplitude time converting circuit in each pixel inside reading circuit, and therefore, in primary detection, all pixels can provide the strength information of different echo-signals.Amplitude time converting circuit of the invention is limited smaller by clock frequency, greatly improves conversion accuracy, and the voltage for representing echo signal intensity directly exports in a digital format, is carried out 2 quantizations without on piece ADC, is reduced the difficulty of system-on-chip designs.
Description
Technical field
The present invention relates to a kind of high-precision amplitude time converting circuits, belong to field of circuit technology.
Background technique
Laser radar is a kind of active probing technique that can accurately and quickly obtain ground or atmosphere three-dimensional spatial information,
It can be used to carry out ranging angle measurement etc., therefore it is widely used in military and civilian field.Imaging laser radar point
For multiple-working mode, such as it is imaged using the scanning imagery of unit or detector array with using the Non-scanning mode of detector array.
Can be far using the scanning imagery operating distance of unit or detector array, but imaging rate will receive certain limitation；And
The image taking speed of detector array is very fast, while it is big to overcome scanning co-volume, the shortcomings that quality weight, poor reliability, in reality
It is played a crucial role in when property and the higher extraterrestrial target Relative Navigation application of volume requirement, has become many states at present
The emphasis and hot spot of family's research.
APD array has the characteristics that structure of whole solid state, high-quantum efficiency, and good noise can be kept under high-gain
Than.Laser three-dimensional imaging radar based on APD array carries out floodlight irradiation to target scene using laser, and one time laser pulse is
It can get the 3-D image of target.When the bias voltage of APD is lower than its avalanche voltage, Linear Amplifer is played to incident photoelectron
Effect, this working condition are known as linear model.Under linear model, backward voltage is higher, and gain is bigger.It is APD pairs linear
Continuous current is formed after the gains such as the photoelectron of input carries out amplification, it is continuous to obtain the laser with temporal information and strength information
Echo-signal.
The mating large area array laser radar reading circuit of linear APD detector needs of large area array, and domestic laser thunder at present
Up to reading circuit still based on discrete device or partial array, resolution ratio and imaging rate are lower.When APD scale reaches 64 × 64
When pixel is even more big, laser radar reading circuit can only be realized using single chip integrated method.Measured CMOS technology
It realizes large area array laser radar readout circuit chip, the volume of control system can be reduced, mitigate weight, reduce power consumption, improve
Anti-interference ability increases reliability, obtains high-precision temporal resolution while capture to the high frame rate of target realizing.
The laser of large area array three-dimensional imaging at present reading circuit generally only has timing distance measurement function because being limited by pixel area,
Therefore a split-second precision digital conversion circuit is integrated in i.e. each pixel can only extract the temporal information of echo-signal.It is right
Echo signal intensity information is extracted, circuit can only share an ADC using each column or several column to solve, pass through row/column and control letter
The amplitude for number selecting corresponding pixel, carries out ADC conversion to the amplitude information of each pixel one by one.The method seriously limits reading
The working frequency of circuit, and then limit the image taking speed of linear APD detector.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the deficiencies of existing technologies, a kind of high-precision width of Pixel-level is provided
Degree time converting circuit is, it can be achieved that be integrated with an amplitude time converting circuit in each pixel inside the reading circuit, therefore,
In primary detection, make all pixels and can provide the strength information of the high-precision digital quantization of different echo-signals.
In order to solve the above technical problems, The technical solution adopted by the invention is as follows:
A kind of high-precision amplitude time converting circuit of Pixel-level, characterized in that select 1 including multiple d type flip flops, latch units, 2
Multiple selector, comparator, gate circuit and capacitor；
Voltage is protected at the anti-phase input termination peak of comparator, and homophase input terminates the detection port of capacitor charge and discharge；
The output signal of first d type flip flop and comparator therein generates control signal Control through gate circuit, for controlling it
His d type flip flop is in the state during amplitude transition period or data are read；
N number of d type flip flop therein, which is sequentially connected, constitutes trigger group, output end and the latter trigger of previous trigger
Input terminal is connected；The amplitude transition period: trigger group is used as counter；During data are read, trigger group is used as shift LD
Device；
Remaining d type flip flop is sequentially connected with trigger group, in the amplitude transition period as memory, stores each clock signal phase
State；Shift register is used as during data are read；
Latch units are used for the phase state of latching clock signal, and latch signal is stored into remaining d type flip flop；
Charge or discharge are carried out by control commencing signal Start control capacitor, according to the different control signals of generation
Control, selection transmission is corresponding during control 2 selects 1 multiple selector to be read according to locating amplitude transition period or data
One circuit-switched data.
Further, control commencing signal Start is input to the grid of MOS switch pipe, passes through control MOS switch pipe control
Constant-current source I carries out charge or discharge to capacitor.
Further, when the grid voltage for controlling commencing signal Start control MOS switch pipe is high, capacitor C discharges；
When the grid voltage for controlling commencing signal Start control MOS switch pipe is low, capacitor C charges.
Further, the clock signal include reference clock signal and through multiple delay units delays formed it is multiple when
Clock signal.
Further, 2 select 1 multiple selector transmit two paths of data include previous pixel data and four input with or
The output data of gate circuit.
Further, the output signal of comparator is generated with after with the output signal phase of the first d type flip flop again behind the door through non-
Control signal Control.
Further, when controlling signal Control=0, during being read into data；
When controlling signal Control=1, into the amplitude transition period.
Advantageous effects of the invention:
The present invention realizes a kind of high-precision amplitude time converting circuit of Pixel-level, i.e., integrates in each pixel inside reading circuit
One amplitude time converting circuit, therefore all pixels can provide the strength information of different echo-signals；Meanwhile the present invention
Amplitude time converting circuit limited by clock frequency smaller, greatly improve conversion accuracy.Represent echo signal intensity
Voltage directly exports in a digital format, carries out 2 quantizations without on piece ADC, reduces the difficulty of system-on-chip designs.
Detailed description of the invention
Fig. 1 is the high-precision amplitude time converting circuit of Pixel-level.
Specific embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following embodiment is only used for clearly illustrating the present invention
Technical solution, and not intended to limit the protection scope of the present invention.
As shown in Figure 1, conversion circuit in the present embodiment by 16 d type flip flop 1D~16D, latch units LATCH1~
1 circuit, comparator com, gate circuit, MOS switch pipe M0, constant-current source I are selected in LATCH4, delay cell DELAY1~DELAY3,2
And capacitor C etc. is constituted.
Circuit external signal is control commencing signal Start, voltage VR and clock signal clk are protected in peak.
D type flip flop 1D~16D is the d type flip flop of 16 identical failing edge triggerings.
D type flip flop 1D~12D constitutes trigger group, and each d type flip flop is sequentially connected, and the output end of previous trigger is with after
The input terminal of one trigger is connected, and the clock of all triggers is clock signal ck1.The amplitude transition period: trigger group is made
For counter use；During data are read, trigger group does shift register use.
The clock signal of three d type flip flop 13D~15D is ck1.The amplitude transition period: 13D~15D trigger is used as and deposits
Reservoir uses；During data are read, 13D~15D does shift register use.
Under other embodiments, the quantity of d type flip flop can also use other quantity, mainly according to clock cycle, letter
Depending on number size.
D type flip flop 16D and control commencing signal Start and comparator com generates control signal Control through gate circuit.
The output signal of comparator com exports control signal Control through non-with the output signal phase of d type flip flop 16D with after again behind the door.
When controlling signal Control=1, circuit is in the amplitude transition period；
When control signal Control becomes 0, during circuit enters data reading by 1.
Clock signal clk can latched unit LA TCH1 latch, the clock signal ck1 phase state after latch is stored to D
In trigger 13D；Clock signal clk 2 obtains for clock signal clk through a delay cell DEALY1, and can latched unit
LATCH2 is latched, and the phase state signal ck2 after latch is stored into d type flip flop 14D；Clock signal clk 3 is clock signal
CLK2 is obtained through a delay cell DEALY2；Clock signal clk 4 is that clock signal clk 3 is obtained through a delay cell DEALY3,
Also, clock signal clk 3, clock signal clk 4 are latched through latch units LATCH3, LATCH4 respectively, the phase after latch
Status signal is stored through biconditional gate output into d type flip flop 15D.
Latch units LATCH is used for the state of latching clock signal CLK, CLK2, CLK3 and CLK4.
Signal Control=1 is controlled, 2 select 1 circuit to select the end A, and the end A is connected with the output of the same OR circuit of four inputs；
Signal Control=0 is controlled, 2 select 1 circuit to select the end B.2 select the i.e. two-way selection circuit of 1 circuit principle be control signal
Under effect, realization transfers out the data at the end A or the data at the end B is transferred out.The data at the end B are exactly previous pixel
Data, the data at the end A are the output of the same OR circuits of four inputs.
Voltage VR is protected at the anti-phase input termination peak of comparator com, and non-inverting input terminal is constant-current source I to capacitor C charge and discharge
Detect port VC.
MOS switch pipe M0 controls capacitor C and carries out charge or discharge, when control commencing signal Start controls MOS switch pipe M0
Grid voltage be it is high when, capacitor C carry out discharge operation；When the grid voltage of control commencing signal Start control MOS switch pipe M0 is low
When, capacitor C carries out charging operations.
Working principle:
The laser burst pulse echo-signal received is converted into current signal by linear APD photosensor chip, is turned through trans-impedance amplifier
Change the voltage signal of certain amplitude into, which represents the intensity of laser echo signal；Circuit is protected this voltage signal in peak
It keeps being that voltage VR is protected at peak.Peak is protected voltage VR and carries out digital quantization processing by amplitude time converting circuit of the invention, convenient
It integrates with the temporal information of echo-signal to realize quick transmission.
D type flip flop clear 0 each first.After control commencing signal Start is lower by height, start to carry out width of the present invention
Spend time conversion.
Constant-current source I charges to capacitor C, and the voltage of detection port VC is gradually risen by 0.Meanwhile trigger group is as integer
Counter uses, and d type flip flop 13D~15D is used as accurate counter, until voltage VR is protected at voltage VC > peak of detection port.
Control commencing signal Control sets 0,2 by 1 and 1 circuit is selected to select the end B, under the failing edge effect of next clock signal clk,
The peak for representing echo strength is protected failing edge of the voltage VR in totally 15 clock signal ck1 and is successively read from d type flip flop 1D~15D,
Therefore seamless connection is realized in the voltage conversion and data output of pixel.
When voltage VR is protected at the voltage VC < peak for detecting port, latch units LATCH1~LATCH4 is not latched；Detection
When the voltage VC of port > peak protects voltage VR, triggering latch units LATCH1~LATCH4 latch the moment clock signal clk,
The phase state of CLK2, CLK3 and CLK4, and the state is squeezed into d type flip flop 13D~15D and is stored.
The counting precision of accurate counter can be adjusted according to delay cell DELAY.Clock signal and latch units
Quantity is equipped with according to the quantity of delay cell.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (7)
1. a kind of high-precision amplitude time converting circuit of Pixel-level, characterized in that including multiple d type flip flops, latch units, 2
Select 1 multiple selector, comparator, gate circuit and capacitor；
Voltage is protected at the anti-phase input termination peak of comparator, and homophase input terminates the detection port of capacitor charge and discharge；
The output signal of first d type flip flop and comparator therein generates control signal Control through gate circuit, for controlling it
His d type flip flop is in the state during amplitude transition period or data are read；
N number of d type flip flop therein, which is sequentially connected, constitutes trigger group, output end and the latter trigger of previous trigger
Input terminal is connected；The amplitude transition period: trigger group is used as counter；During data are read, trigger group is used as shift LD
Device；
Remaining d type flip flop is sequentially connected with trigger group, in the amplitude transition period as memory, stores each clock signal phase
State；Shift register is used as during data are read；
Latch units are used for the phase state of latching clock signal, and latch signal is stored into remaining d type flip flop；
Charge or discharge are carried out by control commencing signal Start control capacitor, according to the different control signals of generation
Control, selection transmission is corresponding during control 2 selects 1 multiple selector to be read according to locating amplitude transition period or data
One circuit-switched data.
2. a kind of high-precision amplitude time converting circuit of Pixel-level according to claim 1, characterized in that control starts
Signal Start is input to the grid of MOS switch pipe, controls constant-current source I by control MOS switch pipe and capacitor is charged or put
Electricity.
3. a kind of high-precision amplitude time converting circuit of Pixel-level according to claim 1, characterized in that when control is opened
When the grid voltage of beginning signal Start control MOS switch pipe is high, capacitor C discharges；
When the grid voltage for controlling commencing signal Start control MOS switch pipe is low, capacitor C charges.
4. a kind of high-precision amplitude time converting circuit of Pixel-level according to claim 1, characterized in that the clock
Signal includes reference clock signal and multiple clock signals for being formed through multiple delay units delays.
5. a kind of high-precision amplitude time converting circuit of Pixel-level according to claim 1, characterized in that 2 select 1 multichannel
Selector transmission two paths of data include previous pixel data and four input with OR circuit output data.
6. a kind of high-precision amplitude time converting circuit of Pixel-level according to claim 1, characterized in that comparator
Output signal generates control signal Control through non-with the output signal phase of the first d type flip flop with after again behind the door.
7. a kind of high-precision amplitude time converting circuit of Pixel-level according to claim 1, characterized in that when control is believed
When number Control=0, during being read into data；
When controlling signal Control=1, into the amplitude transition period.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910715901.1A CN110347031B (en) | 2019-08-05 | 2019-08-05 | Pixel-level high-precision amplitude-time conversion circuit |
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| CN201910715901.1A CN110347031B (en) | 2019-08-05 | 2019-08-05 | Pixel-level high-precision amplitude-time conversion circuit |
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