CN110233611B - Cascade phase interpolation method and circuit and clock data recovery circuit - Google Patents
Cascade phase interpolation method and circuit and clock data recovery circuit Download PDFInfo
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- CN110233611B CN110233611B CN201910525525.XA CN201910525525A CN110233611B CN 110233611 B CN110233611 B CN 110233611B CN 201910525525 A CN201910525525 A CN 201910525525A CN 110233611 B CN110233611 B CN 110233611B
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Abstract
The invention discloses a cascade phase interpolation method, a circuit and a clock data recovery circuit, wherein a T digital control module controls the work or short circuit of a current source switch of a triangular interpolator, and the triangular interpolation module carries out multiplexing interpolation on 4 paths of four-phase quadrature clocks and outputs 4 paths of multiplexing eight-phase clocks; the L digital control module of the linear interpolation module controls the work switch of the current steering type analog-to-digital converter to work or close, the C digital control module of the linear interpolation module outputs complementary control signals to control each path of power switch of the current steering type analog-to-digital converter, the linear interpolation module carries out multiplexing interpolation on the multiplexing 4 paths of eight-phase clocks and outputs a specific phase clock, the problems of low speed, high power consumption, low linearity and high circuit complexity of an interpolator module are solved, and the phase interpolator and the method with low power consumption, high linearity and simple circuit multiplexing structure are provided.
Description
Technical Field
The invention relates to the field of communication, in particular to a cascade phase interpolation method and circuit and a clock data recovery circuit.
Background
In the case of a high clock frequency, a Phase Locked Loop (PLL) provides four quadrature signals (0 °, 90 °,180 °, and 270 °) at most after frequency division by two, and therefore a Phase Interpolator (PI) is required to obtain a clock signal with a smaller Phase accuracy. Fig. 1 is a schematic diagram of a phase interpolator in a cascade form according to the related art, as shown in fig. 1, a cascade structure PI principle: the input four orthogonal signals (0 degrees, 90 degrees, 180 degrees and 270 degrees) pass through a triangular interpolator, 8 signals (0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees and 315 degrees) with the phase difference of 45 degrees are output, and the 8 signals with the phase difference of 45 degrees are input to the next stage. By selecting 8 from 2 by control signal E, 2 parts with a phase difference of 45 DEG are selected for interpolation, and a control signal C is given. Different interpolation operations are performed according to the difference of C, so that a clock of a specific phase is output.
Fig. 2 is a schematic diagram of a triangular interpolator according to the related art, as shown in fig. 2. Specific clock input and output relationships are shown in fig. 1.
Fig. 3 shows a schematic diagram of a linear triangular interpolator according to the related art, and as shown in fig. 3, the linear triangular interpolator is further composed of eight sets of Current-steering analog-to-digital converters (C-DACs), each set of C-DACs being composed of a pair of differential pairs plus 8 Current sources. The 8-to-2 digital selector selects two differential pairs with a difference of 45 degrees to work for interpolation. The complementary control signals C <7 > are input to the C-DACs corresponding to the two differential pairs such that one side turns on a certain number of current sources and the other side turns on a complementary number of current sources, for a total of a fixed value.
Fig. 4 is a schematic diagram of a current source superposition switching tube according to the related art, as shown in fig. 4. The structure is that a switch tube is superposed on a current source, and the on-off of the switch tube is controlled by C <7 >.
In the related art, there are problems including:
1. because the second-stage input only uses two paths of the first-stage 8-path output, the other 6 paths of first stages are always generated at each interpolation stage, and unnecessary power consumption is increased;
2. because the 8 paths of output of the first stage are simultaneously opened in any state and are all input to the next stage, 8 completely same C-DACs are used in the later stage, and the complexity and the unnecessity of the circuit are increased;
3. because the phase interpolator C-DAC has the structural limitation of a pair of differential pairs and 8 current sources, the linearity of the output phase is not good;
4. because the current source of the current source superposition switching tube is greatly influenced by the current source Vds, the same circuit current can be changed under the condition that different C <7 > are input, so that the total current of the two complementary C-DAC is not a fixed value, and the linearity is also influenced.
In the related art, no effective solution is provided at present for the problems of slow speed, high power consumption, low linearity and high circuit complexity of an interpolator module.
Disclosure of Invention
The invention provides a cascade phase interpolation method, a circuit and a clock data recovery circuit aiming at the problem of direct current offset of differential signals in a high-speed data transmission system in the related art, and at least solves the problem.
According to an aspect of the present invention, there is provided a cascaded phase interpolator circuit, comprising a triangular interpolation module and a linear interpolation module, wherein the triangular interpolation module and the linear interpolation module are connected;
the triangular interpolation module comprises: the digital control circuit comprises a triangular interpolator and a T digital control module, wherein 4 paths of four-phase quadrature clocks are input into the triangular interpolation module, the T digital control module controls the work or short circuit of a current source switch of the triangular interpolator, and the triangular interpolation module carries out multiplexing interpolation on the 4 paths of four-phase quadrature clocks to output multiplexed 4 paths of eight-phase clocks;
the linear interpolation module comprises: the system comprises a current steering type analog-to-digital converter, a C digital control module and an L digital control module, wherein the L digital control module controls a working switch of the current steering type analog-to-digital converter to work or close, the C digital control module outputs complementary control signals to control each power switch of the current steering type analog-to-digital converter, and the linear interpolation module performs multiplexing interpolation on the multiplexing 4-path eight-phase clock and outputs a specific phase clock.
Further, the triangular interpolator includes: a first triangular interpolator, a second triangular interpolator, a third triangular interpolator and a fourth triangular interpolator;
the first, second, third and fourth triangular interpolators each include: the current source circuit comprises a load, two pairs of input differential pair transistors, a first current source and a first current source switch, wherein the first current source switch controls the switch of the first current source;
the T digital control module controls the work or short circuit of the current source switch of the triangular interpolator to comprise: the T digital control module controls the first current source switches of the first, second, third, and fourth triangular interpolators through a first two-bit control signal T <1 >.
Further, the linear interpolation module includes: the current steering control system comprises a first current steering analog-to-digital converter, a second current steering analog-to-digital converter, a third current steering analog-to-digital converter and a fourth current steering analog-to-digital converter;
the first current-steering analog-to-digital converter, the second current-steering analog-to-digital converter, the third current-steering analog-to-digital converter, and the fourth current-steering analog-to-digital converter each include: 8 pairs of differential pair transistors, 8 second current sources and 8 second current source switches; the switch of the second current source is connected to the gate path of the second current source.
Further, the C digital control module controls 8 of the second current source switches of the 8 pairs of differential pair transistors of the first and second current steering analog-to-digital converters by a first eight bit control signal C <7 > following a thermometer code change;
the C digital control module controls 8 second current source switches of the 8 pairs of differential pair transistors of a third current steering analog-to-digital converter and a fourth current steering analog-to-digital converter through a second eight-bit control signal and C <7 >;
the first eight-bit control signal C <7 > and the second eight-bit control signal are complementary to C <7 > with respect to 11111111111.
Further, the L digital control module controls the operating switches of the first current steering analog-to-digital converter, the second current steering analog-to-digital converter, the third current steering analog-to-digital converter, and the fourth current steering analog-to-digital converter through a second two-bit control signal L <1 >, and the second two-bit control signal L < 0> controls the operating switches to be turned off or turned on.
According to an aspect of the present invention, there is also provided a method for cascaded phase interpolation, the method is applied to a cascaded phase interpolator circuit, the cascaded phase interpolator circuit comprises a triangular interpolation module and a linear interpolation module, the triangular interpolation module and the linear interpolation module are connected;
the triangular interpolation module comprises: the digital control circuit comprises a triangular interpolator and a T digital control module, wherein 4 paths of four-phase quadrature clocks are input into the triangular interpolation module, the T digital control module controls the work or short circuit of a current source switch of the triangular interpolator, and the triangular interpolation module carries out multiplexing interpolation on the 4 paths of four-phase quadrature clocks to output multiplexed 4 paths of eight-phase clocks;
the linear interpolation module comprises: the system comprises a current steering type analog-to-digital converter, a C digital control module and an L digital control module, wherein the L digital control module controls a working switch of the current steering type analog-to-digital converter to work or close, the C digital control module outputs complementary control signals to control each power switch of the current steering type analog-to-digital converter, and the linear interpolation module performs multiplexing interpolation on the multiplexing 4-path eight-phase clock and outputs a specific phase clock.
Further, the triangular interpolator includes: a first triangular interpolator, a second triangular interpolator, a third triangular interpolator and a fourth triangular interpolator;
the first, second, third and fourth triangular interpolators each include: the current source circuit comprises a load, two pairs of input differential pair transistors, a first current source and a first current source switch, wherein the first current source switch controls the switch of the first current source;
the T digital control module controls the work or short circuit of the current source switch of the triangular interpolator, and the T digital control module comprises the following steps: the T digital control module controls the first current source switches of the first, second, third, and fourth triangular interpolators through a first two-bit control signal T <1 >.
Further, the linear interpolation module includes: the current steering control system comprises a first current steering analog-to-digital converter, a second current steering analog-to-digital converter, a third current steering analog-to-digital converter and a fourth current steering analog-to-digital converter;
the first current-steering analog-to-digital converter, the second current-steering analog-to-digital converter, the third current-steering analog-to-digital converter, and the fourth current-steering analog-to-digital converter each include: 8 pairs of differential pair transistors, 8 second current sources and 8 second current source switches; the switch of the second current source is connected to the gate path of the second current source;
the C digital control module controls 8 second current source switches of the 8 pairs of differential pair transistors of a first current steering analog-to-digital converter and a second current steering analog-to-digital converter through a first eight-bit control signal C <7 >, the first eight-bit control signal C <7 > following a thermometer code change;
the C digital control module controls 8 second current source switches of the 8 pairs of differential pair transistors of a third current steering analog-to-digital converter and a fourth current steering analog-to-digital converter through a second eight-bit control signal and C <7 >;
the first eight-bit control signal C <7 > and the second eight-bit control signal are complementary to C <7 > with respect to 11111111111.
Further, the L digital control module controls the operating switches of the first current steering analog-to-digital converter, the second current steering analog-to-digital converter, the third current steering analog-to-digital converter, and the fourth current steering analog-to-digital converter through a second two-bit control signal L <1 > where L < 0> controls the operating switches to be turned on or off.
According to another aspect of the present invention, there is also provided a clock data recovery circuit, including a cascaded phase interpolator circuit including a triangular interpolation module and a linear interpolation module, the triangular interpolation module and the linear interpolation module being connected;
the triangular interpolation module comprises: the digital control circuit comprises a triangular interpolator and a T digital control module, wherein 4 paths of four-phase quadrature clocks are input into the triangular interpolation module, the T digital control module controls the work or short circuit of a current source switch of the triangular interpolator, and the triangular interpolation module carries out multiplexing interpolation on the 4 paths of four-phase quadrature clocks to output multiplexed 4 paths of eight-phase clocks;
the linear interpolation module comprises: the system comprises a current steering type analog-to-digital converter, a C digital control module and an L digital control module, wherein the L digital control module controls a working switch of the current steering type analog-to-digital converter to work or close, the C digital control module outputs complementary control signals to control each power switch of the current steering type analog-to-digital converter, and the linear interpolation module performs multiplexing interpolation on the multiplexing 4-path eight-phase clock and outputs a specific phase clock.
According to the invention, 4 paths of four-phase orthogonal clocks are input into the triangular interpolation module, the T digital control module controls the work or short circuit of a current source switch of the triangular interpolator, and the triangular interpolation module carries out multiplexing interpolation on the 4 paths of four-phase orthogonal clocks to output multiplexed 4 paths of eight-phase clocks; the linear interpolation module comprises: the system comprises a current steering type analog-to-digital converter, a C digital control module and an L digital control module, wherein the L digital control module controls a working switch of the current steering type analog-to-digital converter to work or close, the C digital control module outputs complementary control signals to control each path of power switch of the current steering type analog-to-digital converter, the linear interpolation module performs multiplexing interpolation on the multiplexing 4 paths of eight-phase clocks and outputs a specific phase clock, the problems of low speed, high power consumption, low linearity and high circuit complexity of an interpolator module are solved, and the phase interpolator and the method with low power consumption, high linearity and simple circuit multiplexing structure are provided.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a schematic diagram of a phase interpolator in a cascade form according to the related art;
FIG. 2 is a schematic diagram of a triangular interpolator according to the related art;
FIG. 3 is a schematic diagram of a linear triangular interpolator according to the related art;
FIG. 4 is a schematic diagram of a current source superposition switching tube according to the related art;
FIG. 5 is a block diagram of a cascaded phase interpolator circuit according to an embodiment of the present invention;
FIG. 6 is a system schematic block diagram of a cascaded phase interpolator circuit according to an embodiment of the present invention;
FIG. 7 is a schematic circuit diagram of a triangular interpolation module according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a triangulated interpolated input clock and output clock in accordance with an embodiment of the present invention;
FIG. 9 is a schematic diagram of a linear interpolation module connection according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a current source and power source switch connection according to an embodiment of the present invention;
FIG. 11 is a flow chart of a method of cascaded phase interpolation according to an embodiment of the present invention;
fig. 12 is a block diagram of a clock data recovery circuit according to an embodiment of the present invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
In this embodiment, a cascaded phase interpolator circuit is provided, and fig. 5 is a block diagram of a cascaded phase interpolator circuit according to an embodiment of the present invention, as shown in fig. 5, the cascaded phase interpolator circuit includes: a triangular interpolation module 50 and a linear interpolation module 60, wherein the triangular interpolation module 50 is connected with the linear interpolation module 60;
the triangular interpolation module 50 includes: a triangular interpolator 51 and a T digital control module 52, wherein 4 paths of four-phase quadrature clocks are input into the triangular interpolation module 50, the T digital control module 52 controls the work or short circuit of a current source switch of the triangular interpolator 51, and the triangular interpolation module 50 carries out multiplexing interpolation on the 4 paths of four-phase quadrature clocks to output a multiplexed 4 paths of eight-phase clocks;
the linear interpolation module 60 includes: the current steering type analog-to-digital converter 61, the C digital control module 62 and the L digital control module 63, the L digital control module 63 controls the operation switch of the current steering type analog-to-digital converter 61 to operate or close, the C digital control module 62 outputs complementary control signals to control each power switch of the current steering type analog-to-digital converter 61, and the linear interpolation module 60 performs multiplexing interpolation on the multiplexed 4-path eight-phase clock and outputs a specific phase clock.
Fig. 6 is a schematic block diagram of a system of a cascaded phase interpolator circuit according to an embodiment of the present invention, as shown in fig. 6, 4 four-phase quadrature clocks are input to the triangular interpolation module 50, the T digital control module 52 inputs a control signal T to control the operation or short circuit of current source switches of the triangular interpolator 51 (triangular interpolator 0, triangular interpolator 1, triangular interpolator 2, and triangular interpolator 3), the triangular interpolation module 50 performs multiplexing interpolation on the 4 four-phase quadrature clocks to output multiplexed 4 eight-phase clocks, the L digital control module 63 inputs a control signal L to control the operation or turning off of operation switches of the current steering type analog-to-digital converter 61 (C-DAC 0, C-DAC1, C-DAC2, and C-DAC 3), the C digital control module 62 outputs a complementary control signal C to control the power switches of the current steering type analog-to analog-digital converter 61, the linear interpolation module 60 performs multiplexing interpolation on the multiplexed 4 eight-phase clocks to output a specific phase clock, and solves the problems of slow speed of the power consumption of the module, high linearity of the interpolation, low linearity, and high complexity of the interpolation circuit structure and the simple circuit structure.
Fig. 7 is a schematic circuit connection diagram of a triangular interpolation module according to an embodiment of the present invention, fig. 8 is a schematic circuit connection diagram of a triangular interpolation input clock and an output clock according to an embodiment of the present invention, and as shown in fig. 7 and 8, the triangular interpolator 51 includes: a first triangular interpolator (triangular interpolator 0), a second triangular interpolator (triangular interpolator 1), a third triangular interpolator (triangular interpolator 2) and a fourth triangular interpolator (triangular interpolator 3), the first triangular interpolator, the second triangular interpolator, the third triangular interpolator and the fourth triangular interpolator each comprising: a load, two pairs of input differential pair transistors, a first current source and a first current source switch, wherein the first current source switch controls a switch (K) of the first current source;
the triangular interpolation module 50 inputs 4 paths of four-phase orthogonal signals (0 °, 90 °,180 ° and 270 °), generates 8 paths of signals with a phase difference of 45 ° (0 °,45 °, 90 °, 135 °,180 °,225 °, 270 °, 315 °) through interpolation, but the output can be multiplexed due to the T digital control module 52. And finally outputting 4 paths of multiplexed 8-phase clocks: 0 ° &90 °,45 ° &135 °,180 ° &270 °,225 ° &315 °. The corresponding relationship between the input 4 four-phase clocks and the output 4-multiplexed eight-phase clocks is shown in FIG. 8,
for the triangular interpolator 0, INK + and INK-input are 0 degree/180 degrees, INK '+, INK' -input are 0 degree/180 degrees, and output is 0 degree/180 degrees;
for the triangular interpolator 1, INK +, INK-input is 0/180 degrees, INK '+, INK' -input is 90/270 degrees, and output is 45/225 degrees;
for the triangular interpolator 2, INK +, INK-inputs are 90/270, INK '+, INK' -inputs are 90/270, and outputs are 90/270;
for the triangular interpolator 3, the INK +, INK-inputs are 90/270, the INK '+, INK' -inputs are 180/0, and the outputs are 135/315.
The T digital control module 52 controls the first current source switches of the first triangular interpolator, the second triangular interpolator, the third triangular interpolator and the fourth triangular interpolator to operate normally or short-circuit through a first two-bit control signal T <1 >.
When T =00, switches 0, 1 are open, 2, 3 are closed; the triangular interpolators 0 and 1 work normally, and 2 and 3 are short-circuited; the output is 0 degree/180 degree, 45 degree/225 degree.
When T =01, the switches 1 and 2 are open, the switches 3 and 0 are closed, the triangular interpolators 1 and 2 are normally operated, and the switches 3 and 0 are short-circuited. The output is 45 °/225 °, 90 °/270 ° at this time.
When T =10, the switches 2 and 3 are opened, 0 and 1 are closed, the triangular interpolators 2 and 3 operate normally, and 0 and 1 are short-circuited. The output is 90/270, 135/315.
When T =11, the switches 3 and 0 are open, 1 and 2 are closed, the triangular interpolators 3 and 0 are normally operated, and 1 and 2 are short-circuited. The output is 135/315 DEG, 180/0 deg.
Since in each case and only the adjacent triangular interpolators (0, 1 or 1, 2 or 2, 3 or 3, 0) are active simultaneously, the alternating triangular interpolators (0, 2 or 1, 3) do not operate simultaneously, and therefore output a 0 ° and 90 ° connection multiplex, a 45 ° and 135 ° connection multiplex, a 180 ° and 270 ° connection multiplex, and a 225 ° and 315 ° connection multiplex. The final output is four ways of 0 degree and 90 degrees, 45 degrees and 135 degrees, 180 degrees and 270 degrees, and 225 degrees and 315 degrees.
In this embodiment, fig. 9 is a schematic connection diagram of a linear interpolation module according to an embodiment of the present invention, and as shown in fig. 9, the linear interpolation module 60 includes: a first current steering analog-to-digital converter (C-DAC 0), a second current steering analog-to-digital converter (C-DAC 1), a third current steering analog-to-digital converter (C-DAC 2), and a fourth current steering analog-to-digital converter (C-DAC 3);
the first current-steering analog-to-digital converter, the second current-steering analog-to-digital converter, the third current-steering analog-to-digital converter, and the fourth current-steering analog-to-digital converter each include: 8 pairs of differential pair transistors, a second current source (Isoource) and 8 second current source switches (C < m > or C < n >); FIG. 10 is a schematic diagram of the connection of a current source and a power source switch, where the switch (C < m >) of the second current source is connected to the Gate (Gate) path of the second current source, as shown in FIG. 10.
Because the output of the circuit at the upper stage of the triangular interpolation module 50 is multiplexed, the C-DAC can be multiplexed:
0 ° &90 °/180 ° &270 ° share C-DAC0; the C-DAC1 is shared by 45 degrees and 135 degrees/225 degrees and 315 degrees;
sharing C-DAC2 at 180 degrees and 270 degrees/0 degrees and 90 degrees; the C-DAC3 is shared by 225 DEG &315 DEG/45 DEG &135 deg.
Each C-DAC is controlled by a switch Lk controlled by the second two-bit control signal L <1 > of the input L digital control block 63. For C-DAC0 and C-DAC2, each current source is connected to a switch C < m >, which is controlled by a first eight-bit control signal C <7 > for; for C-DAC1 and C-DAC3, each current source is connected to a switch C < n >, and the switch is controlled by a second eight-bit control signal C <7 > and C < n > are complementary to each other.
The input signals of the eight C-DAC0 groups of differential pairs are 0 degrees and 90 degrees, 180 degrees and 270 degrees, and the input control signal is C <7 >;
the input signals of the eight groups of differential pairs of the C-DAC1 are 45 degrees and 135 degrees, 225 degrees and 315 degrees, and the input control signal is C <7 >;
the input signals of the eight groups of differential pairs of the C-DAC2 are 180 degrees and 270 degrees, 0 degrees and 90 degrees, and the input control signal is C <7 >;
the input signals of the eight groups of differential pairs of the C-DAC3 are 225 degrees and 315 degrees, 45 degrees and 135 degrees, and the input control signal is C <7 >.
The C digital control module 62 inputs the first eight bit control signal C <7 >, and follows the thermometer code variation (i.e., 00000000-00000001-00000011-00000111-00001111-00011111-00111111-011111111-11111111111).
Inputting the same signal C <7 > to the C-DAC0 and the C-DAC1, and when C < m > is 1, closing the switch and operating the corresponding current source; and when C < m > is 0, the switch is disconnected, and the corresponding current source does not work.
Inputting the same signal C <7 > for C-DAC2 and C-DAC3, and when C < n > is 1, the switch is closed and the corresponding current source operates; and when C < n > is 0, the switch is turned off and the corresponding current source does not work.
C <7 > is complementary to C <7 > with respect to 11111111111.
The L digital control module 63 controls the operation switches of the first current steering analog-to-digital converter (C-DAC 0), the second current steering analog-to-digital converter (C-DAC 1), the third current steering analog-to-digital converter (C-DAC 2), and the fourth current steering analog-to-digital converter (C-DAC 3) by a second two-bit control signal L <1 > where the second two-bit control signal L < 0> controls the opening or closing of the operation switches.
When L =00, switches 0, 1 are open, 2, 3 are closed; the C-DAC0 and the C-DAC1 work normally, and the C-DAC2 and the C-DAC3 are turned off; according to the selection of the previous stage control signal T, interpolation is carried out at the time of 0 degrees, 45 degrees or 45 degrees, 90 degrees or 90 degrees and 135 degrees.
When L =01, the switches 1 and 2 are opened, the switches 3 and 0 are closed, the C-DAC1 and the C-DAC2 work normally, and the C-DAC3 and the C-DAC0 are turned off; according to the selection of the previous stage control signal T, interpolation is carried out at 135 degrees and 180 degrees at the moment.
When L =10, the switches 2 and 3 are opened, 0 and 1 are closed, the C-DAC2 and the C-DAC3 work normally, and the C-DAC0 and the C-DAC1 are turned off; according to the selection of the previous stage control signal T, interpolation is carried out at 180 degrees, 225 degrees, 270 degrees and 315 degrees.
When L =11, the switches 3 and 0 are opened, the switches 1 and 2 are closed, the C-DAC3 and the C-DAC0 work normally, and the C-DAC1 and the C-DAC2 are turned off; according to the selection of the previous stage control signal T, interpolation is carried out at 315 degrees and 0 degrees.
Note that, for L =00 and L =10, although there are different input interpolation selections, since the previous stage T control signal is present and only one group is input in each interpolation process, aliasing does not occur.
The digital control logic of the above embodiment is shown in Table 1 below
TABLE 1
In the embodiment, a cascaded phase interpolation method is applied to a cascaded phase interpolator circuit, the cascaded phase interpolator circuit comprises a triangular interpolation module 50 and a linear interpolation module 60, the triangular interpolation module 50 is connected with the linear interpolation module 60; the triangular interpolation module 50 includes: a triangular interpolator 51 and a T digital control module 52, the linear interpolation module 60 comprising: a current steering type analog-to-digital converter, a C digital control module 62, and an L digital control module 63.
Fig. 11 is a flowchart of a method of cascaded phase interpolation according to an embodiment of the present invention, as shown in fig. 11, the method comprising the steps of:
s1101, inputting the 4 four-phase quadrature clocks into the delta interpolation module 50, controlling the current source switch of the delta interpolator 51 to work or short-circuit by the T digital control module 52, and multiplexing and interpolating the 4 four-phase quadrature clocks by the delta interpolation module 50 to output the multiplexed 4 eight-phase clocks;
s1101, the L digital control module 63 controls the operation switch of the current steering analog-to-digital converter 61 to operate or close, the C digital control module 62 outputs complementary control signals to control the power switches of the current steering analog-to-digital converter 61, and the linear interpolation module 60 performs multiplexing interpolation on the multiplexed 4-path eight-phase clock and outputs a specific phase clock.
Through the steps, the problems of low speed, high power consumption, low linearity and high circuit complexity of an interpolator module are solved, and the phase interpolator and the method with low power consumption, high linearity and simple circuit multiplexing structure are provided.
The cascaded phase interpolator can be applied to many circuit modules, such as a digital phase-locked loop PLL, a Spread Spectrum Clock Generator (SSCG), a serial deserializer (SerDes), and so on, and is a sub-module circuit with a wide range of applications. For example, in the ultra-high speed SerDes interface, a Clock Data Recovery circuit (abbreviated as Clock Data Recovery) is an important part.
Fig. 12 is a block diagram of a clock data recovery circuit according to an embodiment of the present invention, and as shown in fig. 12, the CDR120 of the clock data recovery circuit includes the cascaded phase interpolator circuit, the CDR structure commonly used in the industry is a Phase Interpolator (PI) -based structure for performing a specific function, and as the technology develops, higher and higher requirements are put on the speed, power consumption, and circuit complexity of the module, and as the PI, the linearity is also an important index. The invention provides a phase interpolator with low power consumption, high linearity and simple circuit multiplexing structure, which can be applied to CDR to meet the requirements of high speed, low power consumption, high linearity, low complexity and the like.
The advantages of the above embodiments compared with the related art are at least as follows:
in the above embodiment, the T digital control module 52 and the L digital control module 63 control the tail current multiplexing of the triangular interpolator 51 and the output multiplexing of the triangular interpolation module 50, so as to enable low power consumption of the cascaded phase interpolator, the eight sets of differential pairs of the linear interpolation module 60 add 8 current sources, and the switch position of the second current source is changed, so as to enable high linearity of the cascaded phase interpolator, for the triangular interpolator 51, the tail current sources are combined into one, and at the same time, a switch controlled by the control signal T is added, so as to implement corresponding functions, thereby reducing the mismatch between the circuit complexity and the design process compared with the conventional method.
The above embodiment replaces the 8-out-of-2 digital control module of the control linear interpolator in the related art, and controls the T digital control module 52 of the triangular interpolation module 50 and the L digital control module 63 of the control linear interpolation module 60 instead.
Due to the use of the two-bit T digital control module 52, in each interpolation process, only two triangular interpolators 51 are operated to output 2 signals with a phase difference of 45 °, and the other two triangular interpolators 51 are not operated. The related art structure does not have the two-bit T digital control block 52, so that the four triangular interpolators 51 are always operated. The novel circuit structure of the embodiment of the invention reduces the power consumption by 40% compared with the structure of the related art.
Since the triangular interpolation module 50 has only 2 signals output with a phase difference of 45 °, the outputs with a phase difference of 90 ° can be multiplexed;
because the output signals of the previous stage triangular interpolation module 50 with a 90 ° phase difference are multiplexed, the C-DAC of the next stage linear interpolation module 60 can also be multiplexed. Compared with the prior art which needs 8 identical C-DACs, the novel circuit structure of the embodiment of the invention only needs 4C-DACs, thereby reducing the complexity of the circuit and further reducing the power consumption. For the C-DAC, a group of differential pairs and 8 current sources are adopted in the related technology, and the novel circuit structure is formed by eight groups of differential pairs and 8 current sources, so that the linearity is greatly improved on the premise of ensuring similar power consumption.
For each current source Isource, the second current source switch is connected in series to the Gate (Gate) end of the second current source instead of the Drain (Drain) end, so that on one hand, noise can be reduced, and on the other hand, the influence of the switch tube on Vds can be reduced, so that the current change is small, the total current is guaranteed to be a constant value, and the linearity is improved.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A cascaded phase interpolator circuit, characterized in that: the device comprises a triangular interpolation module and a linear interpolation module, wherein the triangular interpolation module is connected with the linear interpolation module;
the triangular interpolation module comprises: the digital phase-locked loop comprises a triangular interpolator and a T digital control module, wherein 4 paths of four-phase quadrature clocks are input into the triangular interpolation module, the T digital control module controls the work or short circuit of a current source switch of the triangular interpolator, and the triangular interpolation module carries out multiplexing interpolation on the 4 paths of four-phase quadrature clocks to output multiplexed 4 paths of eight-phase clocks;
the linear interpolation module comprises: the system comprises a current steering type analog-to-digital converter, a C digital control module and an L digital control module, wherein the L digital control module controls a working switch of the current steering type analog-to-digital converter to work or close, the C digital control module outputs complementary control signals to control each power switch of the current steering type analog-to-digital converter, and the linear interpolation module performs multiplexing interpolation on the multiplexing 4-path eight-phase clock and outputs a specific phase clock.
2. The circuit of claim 1,
the triangular interpolator includes: a first triangular interpolator, a second triangular interpolator, a third triangular interpolator and a fourth triangular interpolator;
the first, second, third and fourth triangular interpolators each include: the current source circuit comprises a load, two pairs of input differential pair tubes, a first current source and a first current source switch, wherein the first current source switch controls the switch of the first current source;
the T digital control module controls the work or short circuit of the current source switch of the triangular interpolator to comprise: the T digital control module controls the first current source switches of the first, second, third, and fourth triangular interpolators by a first two-bit control signal T <1 >.
3. The circuit of claim 1,
the linear interpolation module comprises: the current steering control system comprises a first current steering analog-to-digital converter, a second current steering analog-to-digital converter, a third current steering analog-to-digital converter and a fourth current steering analog-to-digital converter;
the first current-steering analog-to-digital converter, the second current-steering analog-to-digital converter, the third current-steering analog-to-digital converter, and the fourth current-steering analog-to-digital converter each include: 8 pairs of differential pair transistors, 8 second current sources and 8 second current source switches; the switch of the second current source is connected to the gate path of the second current source.
4. The circuit of claim 3,
the C digital control module controls 8 of the second current source switches of the 8 pairs of differential pair transistors of the first and second current steering analog-to-digital converters by a first eight bit control signal C <7 >, the first eight bit control signal C <7 > following a thermometer code variation;
the C digital control module controls 8 second current source switches of the 8 pairs of differential pair transistors of a third current steering analog-to-digital converter and a fourth current steering analog-to-digital converter through a second eight-bit control signal and C <7 >;
the first eight-bit control signal C <7 > and the second eight-bit control signal are complementary to C <7 > with respect to 11111111111.
5. The circuit of claim 3,
the L digital control module controls the operating switches of the first current steering analog-to-digital converter, the second current steering analog-to-digital converter, the third current steering analog-to-digital converter and the fourth current steering analog-to-digital converter through a second two-bit control signal L <1 >, and the second two-bit control signal L < 0> controls the opening or closing of the operating switches.
6. A cascade phase interpolation method is characterized in that the method is applied to a cascade phase interpolator circuit, the cascade phase interpolator circuit comprises a triangular interpolation module and a linear interpolation module, and the triangular interpolation module is connected with the linear interpolation module;
the triangular interpolation module comprises: the digital control circuit comprises a triangular interpolator and a T digital control module, wherein 4 paths of four-phase quadrature clocks are input into the triangular interpolation module, the T digital control module controls the work or short circuit of a current source switch of the triangular interpolator, and the triangular interpolation module carries out multiplexing interpolation on the 4 paths of four-phase quadrature clocks to output multiplexed 4 paths of eight-phase clocks;
the linear interpolation module comprises: the system comprises a current steering type analog-to-digital converter, a C digital control module and an L digital control module, wherein the L digital control module controls a working switch of the current steering type analog-to-digital converter to work or close, the C digital control module outputs complementary control signals to control each path of power switch of the current steering type analog-to-digital converter, and the linear interpolation module carries out multiplexing interpolation on the multiplexing 4 paths of eight-phase clocks and outputs a specific phase clock.
7. The method of claim 6,
the triangular interpolator includes: a first triangular interpolator, a second triangular interpolator, a third triangular interpolator and a fourth triangular interpolator;
the first, second, third and fourth triangular interpolators each include: the current source circuit comprises a load, two pairs of input differential pair tubes, a first current source and a first current source switch, wherein the first current source switch controls the switch of the first current source;
the T digital control module controls the work or short circuit of the current source switch of the triangular interpolator to comprise: the T digital control module controls the first current source switches of the first, second, third, and fourth triangular interpolators through a first two-bit control signal T <1 >.
8. The method of claim 6,
the linear interpolation module comprises: the current steering control system comprises a first current steering analog-to-digital converter, a second current steering analog-to-digital converter, a third current steering analog-to-digital converter and a fourth current steering analog-to-digital converter;
the first current-steering analog-to-digital converter, the second current-steering analog-to-digital converter, the third current-steering analog-to-digital converter, and the fourth current-steering analog-to-digital converter each include: 8 pairs of differential pair transistors, 8 second current sources and 8 second current source switches; the switch of the second current source is connected to the gate path of the second current source;
the C digital control module controls 8 of the second current source switches of the 8 pairs of differential pair transistors of the first and second current steering analog-to-digital converters by a first eight bit control signal C <7 >, the first eight bit control signal C <7 > following a thermometer code variation;
the C digital control module controls 8 second current source switches of the 8 pairs of differential pair transistors of a third current steering analog-to-digital converter and a fourth current steering analog-to-digital converter through a second eight-bit control signal and C <7 >;
the first eight-bit control signal C <7 > and the second eight-bit control signal are complementary to C <7 > with respect to 11111111.
9. The method of claim 8,
the L digital control module controls the operating switches of the first current steering analog-to-digital converter, the second current steering analog-to-digital converter, the third current steering analog-to-digital converter, and the fourth current steering analog-to-digital converter through a second two-bit control signal L <1 >, and the second two-bit control signal L < 0> controls the operating switches to be turned on or off.
10. A clock data recovery circuit is characterized by comprising a cascade phase interpolator circuit, wherein the cascade phase interpolator circuit comprises a triangular interpolation module and a linear interpolation module, and the triangular interpolation module is connected with the linear interpolation module;
the triangular interpolation module comprises: the digital control circuit comprises a triangular interpolator and a T digital control module, wherein 4 paths of four-phase quadrature clocks are input into the triangular interpolation module, the T digital control module controls the work or short circuit of a current source switch of the triangular interpolator, and the triangular interpolation module carries out multiplexing interpolation on the 4 paths of four-phase quadrature clocks to output multiplexed 4 paths of eight-phase clocks;
the linear interpolation module comprises: the system comprises a current steering type analog-to-digital converter, a C digital control module and an L digital control module, wherein the L digital control module controls a working switch of the current steering type analog-to-digital converter to work or close, the C digital control module outputs complementary control signals to control each path of power switch of the current steering type analog-to-digital converter, and the linear interpolation module carries out multiplexing interpolation on the multiplexing 4 paths of eight-phase clocks and outputs a specific phase clock.
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