CN110176458A - A kind of 3D nand memory part and its manufacturing method - Google Patents
A kind of 3D nand memory part and its manufacturing method Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The present invention provides a kind of 3D nand memory part and its manufacturing method, it is formed after array common source doped region in the substrate, groove is initially formed in the substrate on array common source doped region, and the bottom contact of the array common source doped region is formed in a groove, stack layer is then re-formed, when etching stack layer formation grid line gap, is contacted with the bottom as stop-layer, and the upper contact of array common source doped region is formed in grid line gap, to form the contact of array common source.In this way, before carrying out deep etching to stack layer, the groove of common source doped region bottom is just defined, and it is stopped in the deep etching of stack layer in the contact of the bottom, to, deep etching is needed not move through to form the recess of common source doped region, direct etching substrate can preferably control the recess pattern in common source doped region, improve the performance of device.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, in particular to a kind of 3D nand memory part and its manufacture
Method.
Background technique
Nand memory part is the non-volatile memory product with low in energy consumption, light weight and excellent performance, in electronic product
It is widely used.
The limit of the NAND device of planar structure nearly true extension reduces every to further improve memory capacity
The carrying cost of bit proposes 3D nand memory part.In 3D nand memory part structure, using vertical stacking multilayer
The mode of grid, the central area of stack layer is array memory block, fringe region is step structure, and array memory block is used to form
Memory cell string, grid line of the conductive layer as each layer of storage unit in stack layer, grid line pass through the contact structures on step
It draws, to realize the 3D nand memory part of stack.And in the common source contact for forming memory cell string, it needs to carve
Stack layer is lost until in substrate, and recess is formed in the common source doped region of substrate, however, during this deep etching, lining
The pattern and flatness being recessed in bottom are all difficult to control, this can impact device performance.
Summary of the invention
In view of this, preferably being controlled the purpose of the present invention is to provide a kind of 3D nand memory part and its manufacturing method
Recess pattern in common source doped region processed, improves the performance of device.
To achieve the above object, the present invention has following technical solution:
A kind of manufacturing method of 3D nand memory part, comprising:
Substrate is provided, the substrate includes array memory block；
In the substrate of the array memory block formed array common source doped region, and in the substrate, the array
Groove is formed on common source doped region；
The bottom contact of the array common source doped region is formed in the groove；
Stack layer is formed on the array memory block；
It is contacted with the bottom as etching stop layer, carries out the etching of the stack layer, to contact upper shape in the bottom
At grid line gap；
The upper contact of the array common source doped region is formed, in the grid line gap, in the contact of the bottom with shape
It is contacted at array common source.
Optionally, in the substrate of the array memory block formed array common source doped region, and in the substrate, institute
It states and forms groove on array common source doped region, comprising:
Mask layer is formed over the substrate；
It is masking with the mask layer, ion implanting is carried out, to form array common source doped region；
It is masking with the mask layer, the substrate for carrying out the array common source doped region performs etching, in the array
Groove is formed on common source doped region.
Optionally, in the substrate of the array memory block formed array common source doped region, and in the substrate, institute
It states and forms groove on array common source doped region, comprising:
Mask layer is formed over the substrate；
It is masking with the mask layer, the etching of the substrate is carried out, to form groove；
It is masking with the mask layer, carries out ion implanting, forms array common source doped region under the groove.
Optionally, it forms used mask plate when the mask layer and forms used exposure mask when the grid line gap
Version is identical.
Optionally, the material of the bottom contact is tungsten.
Optionally, after forming stack layer, before formation grid line gap, further includes:
Memory cell string is formed in the stack layer, the memory cell string includes through the channel hole of the stack layer
And the store function layer and channel layer stacked gradually in channel hole along side wall.
Optionally, the stack layer includes alternately stacked insulating layer and sacrificial layer, after forming the grid line gap,
It is formed before the upper contact, further includes:
The sacrificial layer in the stack layer is replaced with into grid layer using the grid line gap.
Optionally, the upper contact that the array common source doped region is formed in the grid line gap, comprising:
It is sequentially filled the first conductive material and the second conductive material in the grid line gap, it is described to form upper contact
First conductive material, second conductive material has smaller stress, the second conductive material first conduction material
Material has smaller resistance value.
Present invention also provides a kind of 3D nand memory parts, comprising:
Substrate, the substrate include array memory block；
Array common source doped region in the substrate of the array memory block；
Stack layer on the array memory block；
Memory cell string in the stack layer；
Array common source contact on the array common source doped region, the array common source contact include that the array common source is mixed
In groove, the groove in miscellaneous area bottom contact, the bottom contact on through the stack layer grid line gap and
Upper contact in the grid line gap.
Further, the upper contact includes that the first conductive material of grid line gap bottom and described first are led
The second conductive material on electric material.
Further, first conductive material, second conductive material has smaller stress, and described second leads
Electric material first conductive material has smaller resistance value.
Further, the array common source doped region and groove extending direction having the same.
3D nand memory part provided in an embodiment of the present invention and its manufacturing method form array common source in the substrate and mix
After miscellaneous area, it is initially formed groove in the substrate on array common source doped region, and forms the array common source doped region in a groove
Bottom contact, then re-form stack layer, etch stack layer formed grid line gap when, with the bottom contact for stop-layer,
And the upper contact of array common source doped region is formed in grid line gap, to form the contact of array common source.In this way, to stacking
Before layer carries out deep etching, the groove of common source doped region bottom is just defined, and stop at this in the deep etching of stack layer
In the contact of bottom, thus, deep etching is needed not move through to form the recess of common source doped region, and direct etching substrate can be controlled preferably
Recess pattern in common source doped region processed, improves the performance of device.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the flow diagram of the manufacturing method of 3D nand memory part according to embodiments of the present invention；
Fig. 2-8 shows the structural schematic diagram during manufacturing method formation memory device according to an embodiment of the present invention.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technique needs to etch stack layer straight in the common source contact for forming array memory block
Into substrate, and recess is formed in the common source doped region of substrate, however, being recessed in substrate during this deep etching
Pattern and flatness are all difficult to control, this can impact device performance.
For this purpose, forming array common source in the substrate present applicant proposes a kind of 3D nand memory part and its manufacturing method
After doped region, it is initially formed groove in the substrate on array common source doped region, and forms array common source doping in a groove
The bottom in area contacts, and then re-forms stack layer, is to stop with bottom contact when etching stack layer formation grid line gap
Layer, and in grid line gap formed array common source doped region upper contact, thus formed array common source contact.In this way, right
Before stack layer carries out deep etching, the groove of common source doped region bottom is just defined, and stop in the deep etching of stack layer
In the contact of the bottom, thus, deep etching is needed not move through to form the recess of common source doped region, and direct etching substrate can be more preferable
Ground controls the recess pattern in common source doped region, improves the performance of device.
The technical solution and technical effect of the application in order to better understand, below with reference to flow chart Fig. 1 and attached drawing 2-8
Specific embodiment is described in detail.
Refering to what is shown in Fig. 1, providing substrate 100, the substrate 100 includes array memory block, with reference to Fig. 2 institute in step S01
Show.
In the embodiment of the present application, substrate 100 is semiconductor substrate, such as can be Si substrate, Ge substrate, SiGe lining
Bottom, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..In other embodiments, the semiconductor substrate can also be include other elemental semiconductors or compound
The substrate of semiconductor, such as GaAs, InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can be with other outer
Prolong structure, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, the substrate 100 is body silicon substrate.
Substrate 100 includes array memory block, and array memory block is used to form the memory cell string of array arrangement, these storages
Unit string is the storage unit perpendicular to the multiple interconnection formed on the Z of substrate direction, column of the memory cell string in substrate plane
Array arrangement on direction X and line direction Y, line direction Y can be word-line direction, and column direction X can be bit line direction.Array storage
It can be already formed with well region (not shown go out) in the substrate 100 in area, can be formed by p-type or N-type heavy doping, in this reality
It applies in example, which is p-type heavy doping well region (HVPW), is also formed with the periphery of phase contra-doping in p-type heavy doping well region periphery
Well region, N-type heavy doping well region (HVNW), the periphery well region are formed in the region except array memory block.
In step S02, array common source doped region 112 is formed in the substrate 100 of the array memory block, and described
In substrate 100, groove 110 is formed on the array common source doped region 112, with reference to shown in Fig. 4.
Array common source doped region (Array common source) 112 can be used as the source area of memory cell string, this is mixed
Miscellaneous area 112 can extend along word-line direction, and be separated from each other at a predetermined interval in bit line direction.The array common source doped region
112 can be formed by heavy doping.Groove 110 is formed on doped region 112, with the extension side having the same of doped region 112
To can also extend along word-line direction.
In some embodiments of the application, groove 110 can be first formed in substrate 100, with reference to shown in (A) in Fig. 3, and
Afterwards, it is doped technique, array common source doped region 112 is formed in the substrate 100 under groove 110, with reference to shown in Fig. 4.
In further embodiments, doping process can be first carried out, with reference to shown in (B) in Fig. 3, is formed in substrate 100
Array common source doped region 112 then performs etching the substrate where array common source doped region 112, in array common source doped region
Groove 110 is formed on 112, with reference to shown in Fig. 4.
It in these embodiments, can be under the same mask layer in being doped technique and recess etch technique
It carries out, in this way, it is possible to reduce processing step reduces manufacturing cost, improves the integrated level of technique.
Specifically, firstly, forming mask layer 102 on substrate 100.
The mask layer 102 can be hard exposure mask or photoresist, and the material of hard exposure mask can be for example silica, nitridation
Pattern in mask plate can be transferred in photoresist by silicon, silicon oxynitride etc. or their combination by photoetching process, and
Afterwards, the pattern in photoresist is transferred in hard exposure mask using etching technics.
The mask plate used in a lithographic process can be used mask plate when being subsequently formed grid line gap, in this way,
Without the design of new mask plate, manufacturing cost is further decreased, improves process integration.
Later, it is masking with the mask layer 102, the etching of substrate 100 is carried out, and carry out ion implanting, thus serving as a contrast
Array common source doped region 112 is formed in bottom 100, and forms groove 110 on array common source doped region 112, with reference to Fig. 3 and figure
Shown in 4.Then, which is removed, with reference to shown in Fig. 5.As previously mentioned, in this step, can first carry out substrate
Etching then carries out ion implanting, can also first carry out ion implanting, then, carry out the etching of substrate.
In step S03, the bottom contact 114 of the array common source doped region 112, reference are formed in the groove 110
Shown in Fig. 5.
Groove 110 forms the bottom contact 114 of array common source doped region 112 by filling is used for, and bottom contact 114 will be used for
The electricity of array common source doped region 112 is drawn, and will be reserved in the substrate.In this way, just formed stack layer and to stack layer into
Before row deep etching, the groove of common source doped region bottom has just been defined, and has formd array common source doped region 112 in a groove
Bottom contact 114, thus, need not move through deep etching to form the recess of common source doped region, direct etching substrate can be more preferable
Ground controls the recess pattern in common source doped region, improves the performance of device.
The material of bottom contact 114 is conductive material, such as can be the metal materials such as W, can be in specific application
The filling for first carrying out conductive material is then planarized, and flatening process for example can be chemical mechanical grinding, thus,
The bottom contact 114 of the array common source doped region 112 is formed in groove 110, refering to what is shown in Fig. 5, the bottom contact 114 formed
With the extending direction having the same of groove 110.
In step S04, stack layer 120 is formed on the array memory block, with reference to shown in Fig. 6.
Stack layer 120 is used to wherein form the memory cell string perpendicular to substrate direction, may include in stack layer 120
By the grid layer of insulator separation or the substitutable layer of grid layer, which is used for layer storage unit each in memory cell string
Grid.In some embodiments, using rear grid technique, refering to what is shown in Fig. 6, stack layer 120 includes by insulating layer 122 and sacrificing
124 alternately stacked lamination of layer, sacrificial layer 124 will be replaced by grid layer in subsequent steps.In further embodiments,
Using preceding grid technique, stack layer 120 includes by insulating layer and the alternately stacked lamination of grid layer.
Stack layer 120 can be formed by individually stacking (Single deck), can also be by multiple sub- stackings
(Multiple deck) stacks gradually to be formed, and the number of plies of sacrificial layer or grid layer in stack layer is more, the storage unit of formation
The storage unit for including in string is more, and the integrated level of device is higher.Grid layer in stack layer may include storage unit
The grid layer of grid layer and selection grid, selection grid may include drain selection grid (Source Selection Gate, SSG)
And/or drain electrode selection grid (Drain Selection Gate, DSG), wherein the number of plies of storage unit grid layer for example can be
16 layers, 32 layers, 48 layers, 64 layers, 72 layers, 96 layers, 128 layers etc..
Stack layer 120 can be formed by alternating deposit layer laminate, the central region of stack layer 120 can deposit for array
Storage area, fringe region can be stepped region (not shown go out), and stepped region will be used to form the contact of grid layer, by grid layer
Electricity is drawn, and in specific application, can form step structure in stepped region after alternating deposit forms stack layer.Step
Structure can for along substrate planar direction separate unit stage structure incremented by successively, alternate photoresist can be passed through
Trimming (Trim) and stack layer etching technics are formed in stepped region；Step structure can also be subregion step (Staircase
Divide Scheme, SDS), subregion step along substrate be planar all formed with step on two orthogonal directions, point
Area's step can have different subregions, such as 3 subregions, 4 subregions or more multi partition etc., such as can use different subregions
Plate closely follows the etching of a stack layer by the multiple trimming of photoresist in 2 orthogonal directions after trimming each time, thus
Form subregion step.
Then, memory cell string 130 can be formed in the stack layer 120 of array memory block, with reference to shown in Fig. 6.Storage
Unit string 130 is along perpendicular to the sequentially connected memory device on 100 direction Z of substrate, each layer of grid layer and storage unit
String constitutes a storage unit.Wherein, memory cell string 130 includes channel hole 132, is sequentially formed in depositing in channel hole 132
Functional layer 136 and channel layer 138 are stored up, through stack layer 120 to substrate 100, channel layer 138 is formed in storage function in channel hole 132
It on the side wall of ergosphere 136 and the bottom in channel hole, contacts, can also be formed between channel layer 138 absolutely with epitaxial structure 132
The filled layer of edge material, store function layer 136 may include the barrier layer stacked gradually, charge storage layer and tunnelling
(Tunneling) layer.In the particular embodiment, barrier layer, charge storage layer and tunnelling (Tunneling) layer specifically can be with
For ONO lamination, the lamination of ONO (Oxide-Nitride-Oxide) lamination, that is, oxide, nitride and oxide, channel layer can
Think that polysilicon layer, filled layer can be silicon oxide layer.
In the embodiment of the present application, the bottom in channel hole 132 is also formed with epitaxial structure 134, which passes through
It is epitaxially grown on the substrate semiconductor material to be formed, the channel of the lower gating tube device as memory cell string 130, in stack layer
Bottom grid layer will as it is lower gating tube device grid.Conductive layer 139 is also formed on memory cell string 130, this is led
Electric layer 139 can be used for being formed the upper gating tube device of memory cell string 130, will also form interconnection architecture on conductive layer 139, with
It is further formed bit line.
In step S05, be etching stop layer with bottom contact 114, carry out the etching of the stack layer 120, with
Grid line gap 140 is formed in the bottom contact 114, it is shown in Figure 7.
Grid line gap (Gate Line Seam) 140 is set in stack layer 120, is extended along word-line direction and by stack layer
Multiple memory blocks are divided into, in rear grid technique, which is used for the removal of sacrificial layer 124 in stack layer 120 simultaneously
Grid layer is replaced with, meanwhile, also by the contact for the array common source doped region 112 being used to form in substrate in the grid line gap 140,
It is contacted as common source.And in preceding grid technique, which is used to form the array common source doped region 112 in substrate
Contact is contacted as common source.
In the embodiment of later grid technique, specifically, can be by lithographic technique, such as can be carved using reactive ion
Erosion carries out the etching of stack layer 120, until bottom contact 114 of the perforation into substrate 100, so that grid line gap 140 is formed,
With reference to shown in Fig. 7.It, will not in the deep etching process in grid line gap 140 due to pre-buried in the substrate bottom contact 114
It is related to the formation of recess pattern in substrate, direct etching substrate can preferably control the recess pattern in common source doped region, mention
The performance of high device.
It then, can be using the sacrificial layer 124 in acid system erosion removal stack layer, in the realization of one embodiment, heap
Lamination can choose the acid solution of the high selectivity ratio to silicon nitride and silica by silicon nitride and the alternately laminated formation of silica, real
While now removing silicon nitride, the removal of silica is avoided, such as phosphoric acid (H can be used3PO4) carry out silicon nitride layer removal.
After the removal of sacrificial layer 124, stack layer 120 is engraved structure, is vacancy layer between insulating layer 122, then,
Using grid line gap 140, grid material is filled into vacancy layer to form grid layer 125, refering to what is shown in Fig. 7, the grid layer 125
For the control gate of storage unit.In one embodiment, grid material can be metal material, such as tungsten, tungsten can
To be formed using physical vapour deposition (PVD) (PVD).
Then, over etching can also be carried out to the grid layer 125 of 140 side-walls of grid line gap, and forms insulating layer, this is absolutely
Edge layer is used for contact to be formed in isolated gate linear slit gap.
In step S06, the array common source doped region is formed in the grid line gap 140, in bottom contact 114
112 upper contact 150, to form the contact of array common source, with reference to shown in Fig. 8.
The grid line gap 140 is formed on bottom contact 114, after the filling for carrying out conductive material, grid line gap
The upper contact 150 that 114 contacts are contacted with bottom will be formed in 140, which contacts 114 forming arrays with bottom
The extraction of common source doped region 112 contacts, i.e., array common source contacts.
The upper contact 150 can be formed by one or more materials.In some embodiments, the upper contact is formed
150 the step of, specifically includes: the first conductive material 152 and the second conductive material 154 is sequentially filled in the grid line gap, with shape
At upper contact 150, refering to what is shown in Fig. 8, further, the first conductive material second conductive material has more
Small stress, the second conductive material first conductive material have smaller resistance value.In a specific embodiment
In, the first conductive material 152 can be polysilicon, and the second conductive material 154 can be tungsten.This way it is possible to avoid stress
Caused chip deformation reduces the resistance value of common source contact simultaneously, improves the performance of device.
So far, it is formed the 3D nand memory part of the embodiment of the present application.
The manufacturing method of the 3D nand memory part of the embodiment of the present application is described in detail above, in addition, this
Application additionally provides the 3D nand memory part formed by the above method, refering to what is shown in Fig. 8, the memory device includes:
Substrate 100, the substrate 100 include array memory block；
Array common source doped region 112 in the substrate 100 of the array memory block；
Stack layer 120 on the array memory block, the stack layer 120 include alternately stacked insulating layer 122 and grid
Pole layer 125；
Memory cell string 130 in the stack layer 120；
Array common source contact on the array common source doped region 112, the array common source contact include that the array is total
Run through the stack layer in bottom contact 114, bottom contact 114 in groove, the groove on source dopant region 112
Upper contact 150 in 120 grid line gap and the grid line gap.
Further, the upper contact 150 may include a kind of conductive material.
Further, the upper contact 150 can also include grid line gap bottom the first conductive material 152 with
And the second conductive material 154 on first conductive material 152.
Further, first conductive material, second conductive material has smaller stress, and described second leads
Electric material first conductive material has smaller resistance value.
Further, the first conductive material 152 can be polysilicon, and the second conductive material 154 can be tungsten.
Further, the material of the bottom contact can be tungsten.
It further, can also be including the memory cell string 130 between the grid line gap, the memory cell string 130
Including the store function layer 133 stacked gradually in the channel hole 130 and channel hole 130 of the stack layer 120 along side wall
With channel layer 136.
Wherein, the array common source doped region 112 and groove extending direction having the same.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and the highlights of each of the examples are differences from other embodiments.Especially for memory
For part embodiment, since it is substantially similar to the method embodiment, so describing fairly simple, related place is referring to method reality
Apply the part explanation of example.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, anything that does not depart from the technical scheme of the invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
Claims (12)
1. a kind of manufacturing method of 3D nand memory part characterized by comprising
Substrate is provided, the substrate includes array memory block；
In the substrate of the array memory block formed array common source doped region, and in the substrate, the array common source
Groove is formed on doped region；
The bottom contact of the array common source doped region is formed in the groove；
Stack layer is formed on the array memory block；
It is contacted with the bottom as etching stop layer, carries out the etching of the stack layer, to form grid in the contact of the bottom
Linear slit gap；
The upper contact of the array common source doped region is formed, in the grid line gap, in the contact of the bottom to form battle array
The contact of column common source.
2. the manufacturing method according to claim 1, which is characterized in that form array in the substrate of the array memory block
Common source doped region, and form groove in the substrate, on the array common source doped region, comprising:
Mask layer is formed over the substrate；
It is masking with the mask layer, ion implanting is carried out, to form array common source doped region；
It is masking with the mask layer, the substrate for carrying out the array common source doped region performs etching, in the array common source
Groove is formed on doped region.
3. the manufacturing method according to claim 1, which is characterized in that form array in the substrate of the array memory block
Common source doped region, and form groove in the substrate, on the array common source doped region, comprising:
Mask layer is formed over the substrate；
It is masking with the mask layer, the etching of the substrate is carried out, to form groove；
It is masking with the mask layer, carries out ion implanting, forms array common source doped region under the groove.
4. manufacturing method according to claim 2 or 3, which is characterized in that form used exposure mask when the mask layer
Version is identical as used mask plate when forming the grid line gap.
5. the manufacturing method according to claim 1, which is characterized in that the material of the bottom contact is tungsten.
6. the manufacturing method according to claim 1, which is characterized in that after forming stack layer, formed grid line gap it
Before, further includes:
Form memory cell string in the stack layer, the memory cell string include through the stack layer channel hole and
The store function layer and channel layer stacked gradually in channel hole along side wall.
7. the manufacturing method according to claim 1, which is characterized in that the stack layer include alternately stacked insulating layer and
Sacrificial layer after forming the grid line gap, is formed before the upper contact, further includes:
The sacrificial layer in the stack layer is replaced with into grid layer using the grid line gap.
8. the manufacturing method according to claim 1, which is characterized in that described to form the array in the grid line gap
The upper contact of common source doped region, comprising:
It is sequentially filled the first conductive material and the second conductive material in the grid line gap, to form upper contact, described first
Conductive material second conductive material has smaller stress, the second conductive material the first conductive material tool
There is smaller resistance value.
9. a kind of 3D nand memory part characterized by comprising
Substrate, the substrate include array memory block；
Array common source doped region in the substrate of the array memory block；
Stack layer on the array memory block；
Memory cell string in the stack layer；
Array common source contact on the array common source doped region, the array common source contact includes the array common source doped region
On groove, the bottom contact in the groove, in the contact of the bottom through the grid line gap of the stack layer and described
Upper contact in grid line gap.
10. memory device according to claim 8, which is characterized in that the upper contact includes grid line gap bottom
The second conductive material on first conductive material in portion and first conductive material.
11. memory device according to claim 10, which is characterized in that first conductive material more described second is conductive
Material has smaller stress, and the second conductive material first conductive material has smaller resistance value.
12. memory device according to claim 9, which is characterized in that the array common source doped region and the groove have
There is identical extending direction.
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| CN111403405A (en) * | 2020-03-09 | 2020-07-10 | 长江存储科技有限责任公司 | 3D NAND storage structure and preparation method thereof |
| CN112768457A (en) * | 2020-12-23 | 2021-05-07 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory structure and mask plate |
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