CN110162377A

CN110162377A - A kind of communication means and logic processor

Info

Publication number: CN110162377A
Application number: CN201810152182.2A
Authority: CN
Inventors: 刘晓建
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-02-14
Filing date: 2018-02-14
Publication date: 2019-08-23

Abstract

The embodiment of the present application discloses a kind of communication means and logic processor, and the processor resource for reducing to sender occupies and the final transmission delay of IPI.The embodiment of the present application provides a kind of communication means, it include: after the first logic processor enters virtualization mode, first logic processor interrupts IPI information between obtaining processor, and the IPI information includes: the mark and virtual interrupt information of target virtual processor；First logic processor carries out virtual processor address translation to the mark of the target virtual processor, obtains the target logic processor where the target virtual processor is currently run；First logic processor sends the IPI information to the target logic processor.

Description

A kind of communication means and logic processor

Technical field

This application involves field of computer technology more particularly to a kind of communication means and logic processor.

Background technique

In current processor (Central Processing Unit, CPU), a physical cpu module is externally presented For multiple instruction processing component, each instruction processing unit can independently execute an instruction stream.These instruction processing units Generally known as logic processor (Logical CPU).Needed in computer system operational process, between logic processor into Line asynchronous communication, such as: a logic processor needs that other logic processors is notified to carry out task switching.For another example, it patrols for one Processor is collected to need that other logic processors is notified to remove certain translation lookaside buffer (Translation Lookaside Buffer, TLB) list item.For another example, a logic processor needs to notify that other logic processors are initialized.Logical process This asynchronous communication between device is generally known as interrupting (Inter Processor Interrupt, IPI) between processor, or Software interrupt (Software Generated Interrupt, SGI).

Computer virtualized is the technology that separate unit physical computer is rendered as to multiple stage computers on network, and the network user can To use but actually not existing computer is referred to as virtual machine, referred to as virtual machine (Virtual Machine, VM).For the network user, virtual machine has processor, memory, network interface card, disk etc. hard as true physical computer Part equipment.The processor that virtual machine is included is referred to as virtual processor (Virtual CPU), when logic processor operation is virtual When the corresponding entity of processor, just externally it is presented as that virtual processor is currently running.By virtual processor at runtime to other The IPI that virtual processor is sent is known as virtual IP address I.

In order to be co-located on separate unit physical computer with allowing multiple secure virtual machines, the ability of virtual machine need to be limited System, but the normal work of virtual machine cannot be interfered, this process is referred to as computer system virtualization, is responsible for realizing computer The software of system virtualization is referred to as monitor of virtual machine (Virtual Machine Monitor, VMM).

Hardware virtual machine (Hardware Virtual Machine, HVM) is a kind of dependent on hardware CPU support realization Virtualization, its feature is: VME operating system not being required to provide cooperation, virtual machine operations system to computer system virtualization System can manage virtual machine as management physical computer, such as send IPI.Hardware can embody the support of virtualization are as follows: One specific processor operational mode, such as virtualization mode are provided.Hardware processor guarantee " is run on virtual under this mode The processor state that machine operating system views is identical as non-virtualized situation, the privilege that the VME operating system of HVM carries out It operates or can be done directly or will lead to logic processor and exit present mode of operation, go to the processing logic of VMM ". At this time when VMM needs to make some virtual processor in operating status, VMM just enables logic processor enter virtualization mode, Logic processor executes the code that this virtual processor is needed to be implemented in operating status, and logic processor is needed when sending IPI Virtualization mode is exited, registers " exiting the code entrance that should be executed after virtualization mode " from VMM to logic processor.

In the prior art computer system virtualization by VMM software realize, VMM software take under non-virtualized situation Identical mode, a virtual processor are realized to target virtual processor transmission IPI is logic-based processor transmission IPI , and IPI is the operation for causing logic processor to exit virtualization mode, therefore is being exited as the logic processor of sender Pattern switching is carried out when virtualization mode and needs the regular hour, this processor resource that will increase sender is occupied with IPI's Final transmission delay.

Summary of the invention

The embodiment of the present application provides a kind of communication means and logic processor, for reducing the processor money to sender Source occupies and the final transmission delay of IPI.

In order to solve the above technical problems, the embodiment of the present application the following technical schemes are provided:

In a first aspect, the embodiment of the present application provides a kind of communication means characterized by comprising when the first logical process Device enters after virtualization mode, and first logic processor interrupts IPI information, the IPI packet between obtaining processor It includes: the mark and virtual interrupt information of target virtual processor；First logic processor is to the target virtual processor Mark carry out virtual processor address translation, obtain the target virtual processor currently run where target logic handle Device；First logic processor sends the IPI information to the target logic processor.

In the embodiment of the present application, after the first logic processor enters virtualization mode, the first logic processor is obtained Processor is taken to interrupt IPI information, IPI information includes: the mark and virtual interrupt information of target virtual processor；At first logic It manages device and virtual processor address translation is carried out to the mark of target virtual processor, obtain target virtual processor and currently run institute Target logic processor；First logic processor sends IPI information to target logic processor.In the embodiment of the present application, First logic processor can carry out virtual processor address translation to the mark of target virtual processor, may thereby determine that out Target virtual processor currently runs the target logic processor at place, therefore the first logic processor can be in virtualization mode IPI information directly is sent to the target virtual processor being currently running, allows target virtual processor by injection IPI, no It needs to realize by VMM and IPI information is sent, the first logic processor does not need to exit virtualization mode, therefore yet The final transmission delay to the processor resource occupancy and IPI of sender can be reduced.

In a kind of possible design of the application first aspect, the method also includes: first logic processor pair After the mark of the target virtual processor carries out virtual processor address translation, determine that the target virtual processor does not have In the operation of any one logic processor, first logic processor stores the IPI information, and exits the virtualization Mode；First logic processor described in the first logic processor notice monitor of virtual machine VMM stores the IPI letter Breath.Wherein, after the first logic processor carries out virtual processor address translation to the mark of target virtual processor, mesh is determined Virtual processor is marked not when any one logic processor is run, then illustrates that first logic processor can not determine mesh Mark virtual processor currently runs the target logic processor at place, can store IPI information at this time, such as storage is arrived In sender's exception information storage region, allows the vmm software for running on non-virtualized mode to inquire IPI and send details Information.

In a kind of possible design of the application first aspect, the method also includes: when first logic processor When sending IPI information failure to the target logic processor, first logic processor stores the IPI information, And exit the virtualization mode；First logic processor described in the first logic processor notice VMM stores the IPI Information.Wherein, used interrupt number when " deliver and interrupt " can be set in the first logic processor, enters void in logic processor After quasi-ization mode, IPI information is executed.It exits after virtualization mode, then reason is exited in judgement, if the reason is that " virtualization mode Lower delivery virtual interrupt ", then continue to execute IPI interrupting information using interrupt number by VMM.

In a kind of possible design of the application first aspect, the method also includes: first logic processor to The target logic processor sends the mark of the virtual machine VM where the target virtual processor.Wherein, at the first logic Reason device also needs the mark to the VM where target logic processor transmission target virtual processor, so that recipient can be true Make the VM where the target virtual processor.

In a kind of possible design of the application first aspect, first logic processor handles the destination virtual The mark of device carries out virtual processor address translation, comprising: first logic processor is by inquiry virtual processor to patrolling The routing table for collecting processor carries out virtual processor address translation to the mark to the target virtual processor.Wherein, every When running virtual processor on a logic processor, each logic processor corresponding one carries out according to virtual processor number Routing table of the virtual processor of index to logic processor, oneself the accessible corresponding virtual processing of a logic processor Device to logic processor routing table, thus complete from virtual processor to the address translation of corresponding logic processor.

In a kind of possible design of the application first aspect, the routing table of the virtual processor to logic processor is deposited Storage is in the storage region of first logic processor；Or, the routing table of the virtual processor to logic processor stores In the storage region of the processor that can be used for physics plug where first logic processor；Or, the virtual processing The routing table of device to logic processor is stored into memory.

In a kind of possible design of the application first aspect, first logic processor has for modifying the void The interface of routing table of the quasi- processor to logic processor.

Second aspect, the embodiment of the present application provide a kind of communication means, comprising: when the second logic processor enters virtualization After mode, second logic processor receives the processor that the first logic processor is sent and interrupts IPI information, the IPI Information includes: the mark and virtual interrupt information of target virtual processor；Second logic processor according to it is described it is virtual in Disconnected information carries out virtual interrupt injection processing to the second virtual processor, and second virtual processor is at second logic Reason device enters the virtual processor being currently running after Virtualization Mode.

In the previous embodiment of the application, the first logic processor can carry out the mark of target virtual processor virtual Processor address translation may thereby determine that out the target logic processor where target virtual processor is currently run, therefore First logic processor directly can send IPI information to the target virtual processor that is currently running in virtualization mode, and second Logic processor is as target logic processor, and operation has a target virtual processor on second logic processor, therefore the Two logic processors can carry out IPI injection to the target virtual processor, do not need to realize by VMM to IPI information into Row is sent, and the first logic processor does not need to exit virtualization mode yet, therefore can reduce the processor resource to sender Occupy the final transmission delay with IPI.

In a kind of possible design of the application second aspect, the method also includes: when second virtual processor Mark it is not identical as the mark of the target virtual processor when, second logic processor stores the IPI information, and Exit the virtualization mode.Wherein, the second logic processor determines that the second virtual processor being currently running is not When target virtual processor, the second logic processor can be stored IPI information, such as recipient's exception information is arrived in storage In storage region, allows the vmm software for running on non-virtualized mode to inquire IPI and send detail information.

In a kind of possible design of the application second aspect, the method also includes: second logic processor connects After the IPI information for receiving the transmission of the first logic processor, second logic processor determines the mark of the second virtual processor It is whether identical as the mark of the target virtual processor；At the mark of second virtual processor and the destination virtual Manage device mark it is identical when, triggering executes following steps: second logic processor is according to the virtual interrupt information to the Two virtual processors carry out virtual interrupt injection processing.

In the third aspect of the application, aforementioned first aspect and each is can also be performed in the comprising modules of logic processor The step of described in the possible implementation of kind, it is detailed in aforementioned saying to first aspect and in various possible implementations It is bright.

The third aspect, the embodiment of the present application provide a kind of logic processor, and the logic processor is the first logical process Device, first logic processor includes: processing module, for obtaining after the first logic processor enters virtualization mode Processor is taken to interrupt IPI information, the IPI information includes: the mark and virtual interrupt information of target virtual processor；The place Module is managed, is also used to carry out virtual processor address translation to the mark of the target virtual processor, it is empty to obtain the target Quasi- processor currently runs the target logic processor at place；Sending module, for sending institute to the target logic processor State IPI information.

In a kind of possible design of the application third aspect, the processing module is also used to at the destination virtual After the mark progress virtual processor address translation for managing device, determine the target virtual processor not in any one logic When processor is run, the IPI information is stored, and exit the virtualization mode；The sending module is also used to notify virtual First logic processor described in monitor unit VMM stores the IPI information.

In a kind of possible design of the application third aspect, the processing module is also used at first logic Device is managed to when target logic processor transmission IPI information failure, stores the IPI information, and exit described virtual Change mode；The sending module is also used to notify the first logic processor described in VMM to store the IPI information.

In a kind of possible design of the application third aspect, the sending module is also used to at the target logic Reason device sends the mark of the virtual machine VM where the target virtual processor.

In a kind of possible design of the application third aspect, the processing module is specifically used for through the virtual place of inquiry Device is managed to the routing table of logic processor, virtual processor address translation is carried out to the mark to the target virtual processor.

In a kind of possible design of the application third aspect, the routing table of the virtual processor to logic processor is deposited Storage is in the storage region of first logic processor；Or, the routing table of the virtual processor to logic processor stores In the storage region of the processor that can be used for physics plug where first logic processor；Or, the virtual processing The routing table of device to logic processor is stored into memory.

In a kind of possible design of the application third aspect, first logic processor has for modifying the void The interface of routing table of the quasi- processor to logic processor.

Fourth aspect, the embodiment of the present application provide a kind of logic processor, and the logic processor is the second logical process Device, second logic processor includes: receiving module, for connecing after the second logic processor enters virtualization mode The processor for receiving the transmission of the first logic processor interrupts IPI information, and the IPI information includes: the mark of target virtual processor With virtual interrupt information；Processing module, it is virtual for being carried out according to the virtual interrupt information to second virtual processor Injection processing is interrupted, second virtual processor is that second logic processor enters the void being currently running after Virtualization Mode Quasi- processor.

In a kind of possible design of the application fourth aspect, the processing module is also used to when the described second virtual place When the mark of the mark and the target virtual processor of managing device is not identical, the IPI information is stored, and exit the virtualization Mode.

In a kind of possible design of the application fourth aspect, the processing module is also used to the receiving module and receives First logic processor send IPI information after, determine the second virtual processor identify whether at the destination virtual The mark for managing device is identical；

The processing module is also used to mark and the mark of the target virtual processor when second virtual processor It is sensible simultaneously, triggering execute following steps: according to the virtual interrupt information to the second virtual processor carry out virtual interrupt note Enter processing.

In the fourth aspect of the application, aforementioned second aspect and each is can also be performed in the comprising modules of logic processor The step of described in the possible implementation of kind, it is detailed in aforementioned saying to second aspect and in various possible implementations It is bright.

5th aspect, the embodiment of the present application provide a kind of computer readable storage medium, the computer-readable storage Instruction is stored in medium, when run on a computer, so that computer executes method described in above-mentioned various aspects.

6th aspect, the embodiment of the present application provides a kind of computer program product comprising instruction, when it is in computer When upper operation, so that computer executes method described in above-mentioned various aspects.

7th aspect, the embodiment of the present application provides a kind of communication device, the communication device may include terminal device or The entities such as chip, the communication device include: processor, memory；The memory is for storing instruction；The processor is used In executing the described instruction in the memory, the side as described in any one of aforementioned first aspect or second aspect is specifically executed Method.

Eighth aspect, this application provides a kind of chip systems, which includes processor, for supporting network to set It is standby to realize function involved in above-mentioned aspect, for example, for example sending or handling data and/or letter involved in the above method Breath.In a kind of possible design, the chip system further includes memory, and the memory must for saving the network equipment The program instruction and data wanted.The chip system, can be made of chip, also may include chip and other discrete devices.

Detailed description of the invention

Fig. 1 is the system architecture schematic diagram of processor provided by the embodiments of the present application；

Fig. 2 is a kind of block flowsheet schematic diagram of communication means provided by the embodiments of the present application；

Fig. 3 is the block flowsheet schematic diagram of another communication means provided by the embodiments of the present application；

Fig. 4 is the basic framework schematic diagram of logic processor provided by the embodiments of the present application；

Fig. 5 is a kind of friendship between the logic processor of sender and the logic processor of recipient of the embodiment of the present application Mutual flow diagram；

Fig. 6 is the another kind in the embodiment of the present application between the logic processor of sender and the logic processor of recipient Interaction flow schematic diagram；

Fig. 7 is the module diagram that processor socket includes in the embodiment of the present application；

Fig. 8 is that process when logic processor executes IPI information under virtualization mode provided by the embodiments of the present application is illustrated Figure；

Fig. 9 is that logic processor detects there is information in notify_if under virtualization mode provided by the embodiments of the present application Processing flow schematic diagram afterwards；

Figure 10 is the processing that logic processor requests notify_if under virtualization mode provided by the embodiments of the present application Flow diagram；

Figure 11 is a kind of composed structure schematic diagram of first logic processor provided by the embodiments of the present application；

Figure 12 is a kind of composed structure schematic diagram of second logic processor provided by the embodiments of the present application.

Specific embodiment

With reference to the accompanying drawing, embodiments herein is described.

The description and claims of this application and term " first " in above-mentioned attached drawing, " second " etc. are for distinguishing Similar object, without being used to describe a particular order or precedence order.It should be understood that the term used in this way is in appropriate feelings It can be interchanged under condition, this is only to describe the used differentiation in description to the object of same alike result in embodiments herein Mode.In addition, term " includes " and " having " and their any deformation, it is intended that cover it is non-exclusive include, so as to A series of process, method, system, product or equipment comprising units are not necessarily limited to those units, but may include unclear Other units that ground is listed or intrinsic for these process, methods, product or equipment.

The important terms in the embodiment of the present application are made as described below first:

Virtual machine: in the architecture in computer science, referring to a kind of special software, it can be flat in computer Create a kind of environment between platform and terminal user, and terminal user is then that the environment that is created based on this software is soft to operate Part.In computer science, virtual machine refers to the software realization that the computer of program can be run as real machine.Refer to logical Cross software simulation with complete hardware system function, operate in complete computer in a freestanding environment.One Physical machine can need to fictionalize more virtual machines according to application, realize and run multiple operation systems simultaneously in a physical machine System.For each operating system, user can be carried out virtual subregion, configuration.Meanwhile user can be between multiple operating systems Switching.Virtual machine is a software computer, is similar to a physical machine, runs operating system and application.Multiple virtual functions It is enough to be run simultaneously in same host system.

Monitor of virtual machine (Virtual Machine Monitor, VMM): VMM is exactly a shirtsleeve operation system in fact System.It, which provides much abstract virtual machine and can allow, multiple operating systems while running.Even these operating systems do not need yet It is identical.From the point of view of system, each virtual machine of this when is equivalent to one of VMM this OS (operating system) in fact Process.

Hyper-threading: it hyperthread: goes to improve the performance of CPU using another thinking, CPU can be held simultaneously The multiple thread of row, it will be able to CPU be allowed to play bigger efficiency, i.e., so-called " hyperthread (Hyper-Threading, referred to as " HT ") " skill Art.Hyper-Threading is exactly that two logic cores are modeled to two phy chips using special hardware instruction, allows single place Reason device can be calculated using Thread-Level Parallelism, and then compatible multi-threaded operating system and software, reduce the standby time of CPU, Improve the operational efficiency of CPU.Two threads can be performed simultaneously using Hyper-Threading, but it unlike two real CPU that Sample, each CPU have independent resource.When two threads all need some resource simultaneously, one of them will temporarily stop Only, and resource is conceded, could continued after these resources idles.Therefore the performance of hyperthread and the property not equal to two CPU Energy.

Socket: socket.The reception socket of connector, for injecting plug.

Processor socket: the CPU hardware module of physics plug can be carried out.

Processor interrupts (Inter-Processor Interrupt, IPI): a processor is to another processor The asynchronous notifications of sending.In the system having, it is referred to as SGI/ software interrupt.IPI is a kind of special interruption.In symmetrical many places It manages under device (SMP, symmetric multiprocessing) environment, it can be used to by any one processor to another Processor generates interruption.IPI is typically used to realize consistency synchronization (the Cache Coherency between cache Synchronization) and other side is notified to carry out task schedule/try to be the first.

Symmetric multi-processors (symmetric multiprocessing, SMP): SMP refers to summarizes one on a computer It organizes processor (multi -CPU), shared drive subsystem and bus structures between each CPU.Task queue is symmetrically distributed by system On multiple CPU, all CPU can coequally access memory, input/output (Input/Output, I/O) and outside Equipment.

It is described in detail separately below.

Refering to Figure 1, the system architecture schematic diagram of the processor provided for the application one embodiment, the system tray Structure may include: processor and virtual machine, and wherein processor is hardware, and virtual machine is software.Processor is also referred to as central processing Unit, is the operation and control unit of computer, it is the component explained and executed instruction, and has and location, decoding and execution is taken to refer to The basic function of order, and by the key data transmission channel (such as bus) of computer, with other parts swap information.Place Managing device may include multiple logic processors (logical processor, LP), which is referred to as at physics Manage device, for example, LP1, LP2 ..., LPn, n indicates that the number of logic processor, the value of n can be positive integer, logic processor It is included in processor socket, with the processor unit for independently executing thread.Virtual machine may include multiple virtual Processor (virtual processor, VP), for example, Vp1, VP2 ..., VPn, the value of n can be positive integer.

Such as Fig. 2, a kind of communication means provided by the embodiments of the present application, comprising:

201, after the first logic processor enters virtualization mode, the first logic processor obtains IPI information, IPI Information includes: the mark and virtual interrupt information of target virtual processor.

In the embodiment of the present application, currently operation has virtual processor on the first logic processor, by the first logic processor On the virtual processor that is currently running be defined as the first virtual processor, which needs to handle to destination virtual When device injects IPI, the first logic processor is can be used to send IPI information in the first virtual processor, wherein the IPI information It include: the mark and virtual interrupt information of target virtual processor.The mark of the target virtual processor can be destination virtual The number of processor, the virtual interrupt information can be the detail information of virtual IP address I, such as the virtual interrupt information may include Interrupt number and interruption sending method.

202, the first logic processor carries out virtual processor address translation to the mark of target virtual processor, obtains mesh Mark virtual processor currently runs the target logic processor at place.

In the embodiment of the present application, virtual processor number may be implemented in the first logic processor to compile to logic processor Number translation, function, which includes virtual processor number, numbers the maintenance and inquiry of corresponding table to logic processor.Therefore when the After one logic processor gets the mark of target virtual processor, the mark of target virtual processor can be carried out virtual Processor address translation, obtains the target logic processor where target virtual processor is currently run.

In some embodiments of the present application, first logic processor of step 202 to the mark of target virtual processor into Row virtual processor address translation, comprising:

First logic processor, to the routing table of logic processor, is handled to destination virtual by inquiry virtual processor The mark of device carries out virtual processor address translation.

Wherein, when running virtual processor on each logic processor, each logic processor corresponds to a basis For the virtual processor that virtual processor number is indexed to the routing table of logic processor, a logic processor is accessible Oneself corresponding virtual processor to logic processor routing table, thus complete from virtual processor to corresponding logical process The address translation of device.

In some embodiments of the present application, the routing table of virtual processor to logic processor is stored at the first logic In the storage region for managing device；Or,

The physics that can be used for where the routing table of virtual processor to logic processor is stored in the first logic processor is inserted In the storage region of the processor pulled out；Or,

The routing table of virtual processor to logic processor is stored into memory.

Wherein, the processor that can be used for physics plug refers to processor socket above-mentioned.That is virtual processor is to logic The routing table of processor can individually be stored by a logic processor, can also the processor belonging to the logic processor Carried out in the range of socket it is globally shared, or storage into memory, so that a void can be used in each logic processor Quasi- processor pointer reads virtual processor to the routing table of logic processor from the memory.

In some embodiments of the present application, the first logic processor has for modifying virtual processor to logical process The interface of the routing table of device.

Wherein, logic processor can also provide the support scheme for the routing table for modifying virtual processor to logical process, Such as when this support scheme is triggered, current logic processor is to itself addressable virtual processor to the road of logical process It is modified by table.For another example, logic processor can utilize inter-processor communication mechanism, notify other logic processor modifications virtual Processor is to the routing table of logical process, and specific implementation is herein without limitation.

203, the first logic processor sends IPI information to target logic processor.

In the embodiment of the present application, the first logic processor determines that target virtual processor currently runs the target at place After logic processor, the first logic processor can send IPI information to target logic processor, so that at the target logic IPI injection can be executed according to IPI information by managing device.

In some embodiments of the present application, communication means provided by the embodiments of the present application can also include the following steps:

After first logic processor carries out virtual processor address translation to the mark of target virtual processor, mesh is determined Virtual processor is marked not when any one logic processor is run, the first logic processor stores IPI information, and exits void Quasi-ization mode；

First logic processor notice the first logic processor of VMM stores the IPI information.

Wherein, after the first logic processor carries out virtual processor address translation to the mark of target virtual processor, Determine that target virtual processor in the operation of any one logic processor, does not then illustrate that first logic processor can not be true The target logic processor where target virtual processor is currently run is made, can be stored IPI information at this time, such as It stores in sender's exception information storage region, the vmm software for running on non-virtualized mode is allowed to inquire IPI hair Send detail information.

When the first logic processor, which sends IPI information to target logic processor, to fail, the storage of the first logic processor IPI information, and exit virtualization mode；

First logic processor notice the first logic processor of VMM stores IPI information.

Wherein, used interrupt number when " deliver interrupt " can be set in the first logic processor, logic processor into After entering virtualization mode, IPI information is executed.It exits after virtualization mode, then reason is exited in judgement, if the reason is that " virtualization Virtual interrupt is delivered under mode ", then IPI interrupting information is continued to execute using interrupt number by VMM.

Virtual machine (Virtual where from first logic processor to target logic processor transmission target virtual processor Machine, VM) mark.

Wherein, the first logic processor is also needed to the VM's where target logic processor transmission target virtual processor Mark, so that recipient can determine the VM where the target virtual processor.

Through the illustration of previous embodiment it is found that after the first logic processor enters virtualization mode, first Logic processor obtains processor and interrupts IPI information, and IPI information includes: the mark and virtual interrupt letter of target virtual processor Breath；First logic processor carries out virtual processor address translation to the mark of target virtual processor, obtains at destination virtual Reason device currently runs the target logic processor at place；First logic processor sends IPI information to target logic processor.This To apply in embodiment, the first logic processor can carry out virtual processor address translation to the mark of target virtual processor, It may thereby determine that out the target logic processor where target virtual processor is currently run, therefore the first logic processor can Directly to send IPI information to the target virtual processor being currently running in virtualization mode, so that target virtual processor can IPI information is sent with not needing to realize by VMM by injection IPI, the first logic processor does not need to exit void yet Quasi-ization mode, therefore the final transmission delay to the processor resource occupancy and IPI of sender can be reduced.

The execution process of the logic processor of sender is illustrated in previous embodiment, next patrolling from recipient The execution process for collecting processor is illustrated, and please refers to shown in Fig. 3, communication means provided by the embodiments of the present application mainly wraps Include following steps:

301, after the second logic processor enters virtualization mode, the second logic processor receives the first logical process The IPI information that device is sent, IPI information includes: the mark and virtual interrupt information of target virtual processor.

Wherein, based on the communication mechanism of processor hardware in the embodiment of the present application, the first logic processor sends IPI information Afterwards, the second logic processor can receive the IPI information as recipient, and the second logic processor can be true from the IPI information Make the mark and virtual interrupt information of target virtual processor.

302, the second logic processor carries out at virtual interrupt injection the second virtual processor according to virtual interrupt information Reason.

In the embodiment of the present application, the second virtual processor being currently running is exactly the virtual processing for needing interruption to be implanted Device carries out virtual interrupt injection processing to the second virtual processor according to virtual interrupt information by the second logic processor.Pass through Hardware direct communication between first logic processor and the second logic processor may be implemented to target in the embodiment of the present application The virtual terminal injection of virtual processor is handled, and whole process does not need the access of VMM software, and the second logic processor is also not required to Exit virtualization mode.

In some embodiments of the present application, after step 301 execution, following steps can also be performed:

Second logic processor determine the second virtual processor identify whether it is identical as the mark of target virtual processor, Second virtual processor is that the second logic processor enters the virtual processor being currently running after Virtualization Mode.

When the mark of the second virtual processor is identical as the mark of target virtual processor, triggering executes aforementioned step 302: the second logic processors carry out virtual interrupt injection processing to the second virtual processor according to virtual interrupt information.

In the embodiment of the present application, the second logic processor judges second that second logic processor is currently running Whether virtual processor is exactly the target virtual processor, such as the second logic processor can determine the second virtual processor Identify whether identical as the mark of target virtual processor, the second virtual processor is that the second logic processor enters Virtualization Mode The virtual processor being currently running afterwards.

In the embodiment of the present application, when the mark of the second virtual processor is identical as the mark of target virtual processor, Illustrate that second virtual processor being currently running is exactly the virtual processor for needing interruption to be implanted, at this time by the second logic It manages device and virtual interrupt injection processing is carried out to the second virtual processor according to virtual interrupt information.By the first logic processor and Hardware direct communication between second logic processor may be implemented to the virtual of target virtual processor in the embodiment of the present application Terminal injection processing, whole process do not need the access of VMM software, and the second logic processor does not need to exit virtualization mould yet Formula.

When the mark of the mark of the second virtual processor and target virtual processor is not identical, the second logic processor is deposited IPI information is stored up, and exits the virtualization mode.

Wherein, the second logic processor determines that the second virtual processor being currently running not is destination virtual processing When device, the second logic processor can be stored IPI information, such as be stored into recipient's exception information storage region, Allow the vmm software for running on non-virtualized mode to inquire IPI and sends detail information.

After the second logic processor enters non-virtualized mode, the second logic processor receives the first logic processor The IPI information of transmission, IPI information include: the mark and virtual interrupt information of target virtual processor；

Second logic processor determine the second virtual processor identify whether it is identical as the mark of target virtual processor；

When the mark of the second virtual processor is identical as the mark of target virtual processor, the second logic processor is by The corresponding relationship of two logic processors and the second virtual processor is updated to virtual processor into the routing table of logic processor.

Wherein, after the second logic processor enters non-virtualized mode, i.e., the second logic processor is not to be in Virtualization mode, the second logic processor, which can update the corresponding relationship of the second logic processor and the second virtual processor, to be arrived Virtual processor is into the routing table of logic processor, to realize that logic processor updates the dynamic of the routing table.

By the illustration of previous embodiment it is found that in the embodiment of the present application, the first logic processor can be to target The mark of virtual processor carries out virtual processor address translation, may thereby determine that out that target virtual processor currently runs institute Target logic processor, therefore the first logic processor can be in virtualization mode directly to the destination virtual being currently running Processor sends IPI information, and the second logic processor is used as target logic processor, and running on second logic processor has this Target virtual processor, therefore the second logic processor can carry out IPI injection to the target virtual processor, not need to pass through VMM sends IPI information to realize, the first logic processor does not need to exit virtualization mode yet, therefore can reduce To the final transmission delay of the processor resource occupancy and IPI of sender.

For the above scheme convenient for better understanding and implementing the embodiment of the present application, corresponding application scenarios of illustrating below come It is specifically described.

The technical issues of the embodiment of the present application can solve must be sent by VMM between the virtual processor of HVM IPI, and can not direct communication, so as to cause cpu resource occupy and IPI final transmission delay the problem of.In subsequent embodiment It is identical with the meaning that IPI is interrupted is sent to send IPI.

Between virtual processor by VMM send IPI during cause " cpu resource occupy and IPI it is final transmit prolongs During the main reason for slow problem " is " carrying out IPI communication by VMM ", logic processor can exit virtualization mode, Concrete reason is as follows:

1), sending when IPI is interrupted needs the logic processor of intended receiver to number, but the virtual processing that HVM is perceived Device is numbered generally to be different with the logic processor of physical computer number, if HVM uses the IPI sending logic of standard, IPI The logic processor of mistake will be sent to；

If 2), allow virtual processor to directly transmit IPI to interrupt, the virtual machine of malice may be by not having to virtual machine There is the logic processor used to send IPI, causes system in case of system halt or influence the normal work of other virtual machines；

3), logic processor, which can not be handled correctly, " receives the virtual processor that virtual IP address I is interrupted and is not currently in operation, very To be in blocked state " situation.

In the embodiment of the present application, logic processor, which has, " can get virtual processor to logic processor corresponding relationship " Mechanism.Logic processor has " the virtual processing increased newly by target logic processor not by VMM under virtualization mode Whether device Address translation module " monitoring objective virtual processor is currently running, to judge whether to need the intervention of VMM software. In logic processor when virtual processor executes and exits virtualization mode due to IPI sends instruction, have to VMM software exposure mesh The mechanism for marking the function of virtual processor number and virtual IP address I interruption details, so that VMM software can be in logic processor After exiting virtualization mode, inquiry obtains the reason of exiting, and then the transmission process of virtual IP address I is completed by VMM software.

It should be noted that logic processor sends IPI and sends order in the embodiment of the present application, do not need to exit virtual Change mode.

The application scenarios of the embodiment of the present application are the CPU of computer system, such as x86 processor, arm processor etc..

Fig. 4 is the basic framework schematic diagram of logic processor provided by the embodiments of the present application.The embodiment of the present application is mainly right CPU hardware optimizes.As shown in figure 4, the embodiment of the present application be directed to CPU hardware, in addition to comprising instruction processing logic module it Outside, further include following module: virtual processor Address translation module, virtual processor interrupt reception and dispatch module, object matching module, Sender's exception information memory module, recipient's exception information memory module, sender's exception information enquiry module, recipient are different Normal information inquiry module, recipient's exception reporting module.

Next the function to above-mentioned each module and its correlation are described as follows:

Virtual processor Address translation module: being responsible for realizing the translation that virtual processor number is numbered to logic processor, Its function includes the maintenance and inquiry that virtual processor number numbers corresponding table to logic processor.When logic processor runs void Quasi-ization mode sends instruction because executing IPI, can not obtain effective logic processor by virtual processor Address translation module When number, IPI detail records to be sent in sender's exception information memory module, and are exited virtualization mould by logic processor Formula；

Object matching module: being responsible for the target receiver that the virtual interrupt injection that decision logic processor receives is requested is No is the virtual processor being currently running；

Virtual processor interrupt reception and dispatch module: including sending end interface and interrupting injection submodule two parts.Instruction processing Logic module is requested by sending to the transmission end interface of current logic processor, at the logic to notify to receive IPI interruption Submodule is injected in the interruption for managing device.It is patrolled when the interruption injection submodule of virtual processor interrupt reception and dispatch module is received from other When collecting the interruption injection request of processor, if current logic processor is in non-virtualized mode, recipient's exception is triggered Reporting modules work.If current logic processor is in virtualization mode, just according to the judgement of object matching module as a result, certainly It surely is to deliver to interrupt to virtual processor.Exist alternatively, the interruption received is injected request detail records by current logic processor Recipient's exception information memory module, and it is transferred to non-virtualized mode.

Sender's exception information enquiry module and recipient's exception information enquiry module, can be to run on non-virtualized mould The VMM software of formula provides the inquiry IPI support for sending details.

After recipient's exception reporting module is triggered, the exception that VMM software is registered to logic processor before this is executed Process flow.

In logic processor described in the embodiment of the present application, positioned at logic processor LP_X virtual processor VP_x to When virtual processor VP_y sends IPI interruption, main process be may include steps of:

1) and 2) step 1 mainly includes following both of these case.

1) the virtual processor Address translation module of logic processor LP_X shows that " virtual processor VP_y is currently being patrolled It collects and is run on processor LP_Y ".

When virtual processor VP_x executes the instruction of " sending IPI to virtual processor VP_y to interrupt ", the instruction of LP_X Logic module is handled by its virtual processor Address translation module, VP_y is obtained and is located on effective logic processor LP_Y, The delivery interrupted by the transmission end interface of instruction processing logic module notice virtual processor interrupt reception and dispatch module, Huo Zheyou The delivery that the transmission end interface of virtual processor Address translation module notice virtual processor interrupt reception and dispatch module is interrupted.It patrols The interruption that virtual interrupt injection request is sent to logic processor LP_Y is injected submodule by the transmission end interface for collecting processor LP_X Block.

2) the virtual processor Address translation module of logic processor LP_X shows that " virtual processor VP_y is not being patrolled currently Collect and run on processor ":

Instruction processing logic module known by virtual processor Address translation module " virtual processor VP_y currently without Run on logic processor " after, sender's exception information memory module is written into the IPI details for sending instruction, at the logic Reason device LP_X exits virtualization mode.VMM software can obtain instruction processing logic by sender's exception information enquiry module Module is in the information being placed in sender's exception information memory module before.

After step 1 executes, step 2 is executed:

When the interruption injection module of logic processor LP_Y receives the injection message of the interruption from other logic processors When, it 1) and 2) mainly include following both of these case.:

1), object matching module determines " being currently running the corresponding virtual processor of interruption injection message ".

Interrupt injection submodule receive interrupt injection message after, by object matching module discovery be currently running with This interrupts the corresponding virtual processor of injection message, then direct notification instruction processing logic module infuses current virtual processor Enter IPI interruption.

2), object matching module determines " being not currently running the corresponding virtual processor of interruption injection message ".

Injection submodule is interrupted after receiving interruption injection message, it should be by being not currently in by the discovery of object matching module The virtual processor run on this logic processor receives this IPI interruption, then injects interrupts into the detail records of message to reception Square exception information memory module, and logic module is handled by recipient's exception reporting module notification instruction and carries out abnormality processing. If instruction processing logic module, current just in virtualization mode, exits virtualization mode after receiving this exception reporting；It is no Then directly it is transferred to abnormal conditions (as interrupted) process flow.VMM software can be obtained by recipient's exception information enquiry module Instruction processing logic module is in the information being put into recipient's exception information memory module before.

It is pointed out that virtual processor Address translation module, virtual processor interrupt reception and dispatch module, object matching mould Block, sender's exception information memory module, recipient's exception information enquiry module, is sent recipient's exception information memory module Square exception information enquiry module, recipient's exception reporting module are logic modules, and two or more logic processors completely may be used To share the realization of some or certain logic modules therein, such as: logic processor LP_X and logic processor LP_Y may Virtual processor interrupt reception and dispatch module can be shared.

Logical process implement body provided by the embodiments of the present application can be arm processor hardware.As shown in figure 5, being this Shen It please a kind of interaction flow schematic diagram between the logic processor of sender and the logic processor of recipient of embodiment.? After the logic processor of IPI sender enters virtualization mode, if get IPI transmission instruction, target void is first looked for IPI when cannot obtain effective logic processor number, is interrupted Delivery Information record by the logic processor where quasi- processor To the addressable region of VMM software, it is then log out virtualization mode, and exits reason to VMM software exposure.When can be had When the logic processor of effect, using interrupting information transmission mechanism, recipient's logic processor is notified to carry out virtual interrupt injection, In, it can also include virtual interrupt relevant information in the interrupting information that is transmitted.The logic processor of recipient receives interruption letter After breath, whether target virtual processor is currently currently running by the matching logic judgement of object matching module, if so, carrying out Virtual interrupt injection, otherwise branches to abnormality processing.

Fig. 6 is the another kind in the embodiment of the present application between the logic processor of sender and the logic processor of recipient Interaction flow schematic diagram.Mainly comprise the following processes:

Used interrupt number when " deliver and interrupt " is arranged, it is assumed for example that the interrupt number of setting is to interrupt vec in step 1. After logic processor enters virtualization mode, executes IPI and send instruction or other instructions, for example calculate cpu instruction, timer Instruction.Wherein, which is used to distinguish the interruption of different virtual processors.

Step 2, if exiting virtualization mode after executing IPI transmission instruction, then reason is exited in judgement, if the reason is that " empty Virtual interrupt is delivered under quasi-ization mode ", then IPI is continued to execute using interrupt number interrupt transmission instruction；If other reasons are then held Other processing logics of row.

Step 3 continues to execute IPI using interrupt number and interrupts transmission instruction, delivers under virtualization mode before judgement Whether IPI fails, if delivering IPI failure, then according to current target logic update processor virtual processor at logic The routing iinformation of device is managed, injection failure information is then removed, finally carries out the injection of virtual interrupt；If not IPI failure is delivered, Then directly carry out the injection of virtual interrupt.

Fig. 7 is the module diagram that processor socket includes in the embodiment of the present application.Included in processor socket Main correlation module:

Each processor socket corresponding one is used to refer to " the logic processor number that this socket is included " Bitmap lp_bitmap.

Each logic processor corresponding one stores<vmid, virtual processor, ntr>delivery interrupt storage area domain Pintr_info, wherein " virtual processor " of interrupt storage area domain storage is that the target virtual processor that virtual IP address I is interrupted is compiled Number, vmid is the number of vm where target virtual processor, and intr is that the virtual IP address I being delivered interrupts included related letter Breath, such as virtual IP address I interrupt number, delivery mode.

When running virtual processor, each logic processor corresponding one stores < virtual processor, vmid, Intr > delivery fail memory block f_info, wherein " virtual processor " be virtual IP address I interrupt target virtual processor compile Number, vmid is the number of the virtual machine where target virtual processor, and intr is that the virtual IP address I being delivered interrupts included phase Information is closed, such as virtual IP address I interrupt number delivers mode.In addition, the embodiment of the present application, which also has to VMM software, exposes this information Mechanism.

When running virtual processor, each logic processor has recorded the number and current void of current virtual processor The number vmid of VM where quasi- processor.

When running virtual processor, each logic processor corresponding one is indexed according to virtual processor number Virtual processor to logic processor routing table, logic processor can only access oneself corresponding virtual processor at logic Manage device routing table.

Logic processor provides the receiving end hardware interface notify_if of " virtual interrupt injection notice ", receiving end and hair Sending end is located at same processor socket.

Logic processor provides the setting interface failed_vec of " virtual interrupt injection notice turns IPI interrupt number ".

Logic processor provides the hardware interface recv_if of " receive virtual interrupt and inject message ", receiving end and transmitting terminal Positioned at different processor socket.It includes recipient institute that lpcpu where the sender of virtual IP address I can be transmitted by this interface Logic processor number, receive virtual IP address I virtual processor number, receive virtual IP address I virtual processor where Number, the details of virtual IP address I (such as interrupt number, sending method) of VM；

Each logic processor corresponds to a pintr_info arbitrated logic, and the input of arbitrated logic is each socket The pintr_info request line of other interior logic processors, the recv_if of this logic processor handle logic, such as have for one For the socket for having 24 logic processors, the arbitrated logic of each logic processor includes 23 and comes from other logical process Pintr_info request line, the 1 request line from recv_if processing logic of device.When pintr_info arbitrated logic simultaneously When receiving multiple pintr_info transmission requests, in the way of in turn, some pintr_info that lets pass sends request, with Exempt from multiple senders while writing the memory block pintr_info information is caused to lose.

It should be noted that delivering failure storage region f_info, virtual processor to physical processor (i.e. logical process Device) routing table, virtual processor id, vmid and logic processor not necessarily one-to-one relationship, for example, at for X86 It manages for device, f_info, virtual processor to logic processor routing table, virtual processor id, vmid can be defined within In vmcs control structure, so that, due to having switched vmcs, logic processor is used instead automatically when executing different virtual processors Different f_info, virtual processor to logic processor routing table, virtual processor id and vmid.In addition, processor The corresponding lp_bitmap of socket can be automatic to tie up by logic processor at execution " setting logic processor numbers instruction " Shield, can also be safeguarded by system software or virtual management software.

As shown in figure 8, when executing IPI transmission instruction for logic processor under virtualization mode provided by the embodiments of the present application Flow diagram.IPI is executed as follows in the processor of virtualization mode operation interrupts transmission instruction:

1) if IPI, which, cannot be uniquely determined, interrupts the recipient for sending and specifying in instruction, step 11) is gone to.

2), according to virtual processor to physical processor routing table, the logical process where target virtual processor is searched Device lpcpu.

3), if lp_bitmap corresponding to current socket does not include the lpcpu that step 1) obtains, step 8) is gone to, If going to step 4) including the lpCPU that step 1) obtains.

4), instruction processing logic module sends to the pintr_info arbitrated logic of lpcpu and requests, and waits its letter of letting pass Number.

5), number current logic processor corresponding vmid, IPI target virtual processor for sending instruction, The IPI that IPI sends instruction interrupts the delivery interrupt storage area that details (such as interrupt number, sending method) is put into lpcpu pintr_info.After step 5 executes, step 9) is executed.

6), using notify_if, lpcpu is notified to carry out the injection of virtual IP address I interruption.

7), IPI interrupts transmission instruction execution and terminates.

8), if lpcpu is not legal logic processor number, step 11) is gone to.

9), using recv_if, virtual interrupt is sent to target lpcpu and injects message.

10), IPI interrupts transmission instruction execution and terminates.

11) target virtual processor number (or set of number), the IPI IPI for sending instruction, are interrupted into details Current delivery failure memory block f_info is charged to, and sets invalid value for the vmid in f_info.

12) virtualization mode, is exited.

As shown in figure 9, being detected in notify_if for logic processor under virtualization mode provided by the embodiments of the present application Processing flow schematic diagram after having information.It is received virtually in the logic processor of virtualization mode operation by notify_if When interrupting injection notice, the process included the following steps is executed:

1), by the corresponding pintr_info information cache of this logic processor into the scratchpad area (SPA) cached_info；

2), if the corresponding virtual processor id of current logic processor is not equal to the virtual place recorded in cached_info Reason device number or the corresponding vmid of current logic processor then go to step not equal to the vmid recorded in cached_info 5)；

3), the information recorded according to cached_info injects virtual interrupt to current virtual processor；

4), the next pintr_info of notice pintr_info arbitrated logic clearance sends request, and ends processing process；

5), according to the information in cached_info, the f_info of this logic processor, vmid cached_ are filled in Respective value in info；

6), the next pintr_info of notice pintr_info arbitrated logic clearance sends request, and exits virtualization fortune Row mode terminates the processing for " virtual interrupt injection notice ".

It should be noted that VMM utilizes failed_vec interface before running virtual processor, notify_ is set Vector: " after virtual interrupt injection failure, virtual interrupt injection notice is received by notify_if, or pass through recv_ If receives the number that IPI received by the logic processor of virtual interrupt injection message is interrupted ".

Next for notify_if and recv_if, both realize execution of the scene to the logic processor of receiving end Process is illustrated, and receives virtual interrupt note by notify_if in the logic processor of non-virtualized mode operation When entering to notify, the process included the following steps is executed:

1), by the corresponding pintr_info information cache of this logic processor into the scratchpad area (SPA) cached_info.

2), according to the information in cached_info, the f_info of this logic processor, vmid cached_ are filled in Respective value in info.

3), can let pass next pintr_info of notice pintr_info arbitrated logic sends request.

4) interrupt handling routine corresponding to notify_vector, is executed.

5), terminate the processing for virtual interrupt injection notice.

When logic processor receives virtual interrupt injection message by recv_if, the process included the following steps is executed:

1), the purpose virtual processor number for including in message, purpose vm are numbered, IPI interrupts details and is put into cached_ The temporary storage area info.

2), the pintr_info arbitrated logic transmission for the purpose logic processor specified into virtual interrupt injection message is asked It asks, waits its all-clear.

3), information included in cached_info is put into the delivery interrupt storage area pintr_info of lpcpu.

4), using notify_if, current logic processor is notified to carry out the injection of virtual IP address I interruption.

5), terminate the processing for virtual interrupt injection message.

The logic processor run under non-virtualized mode finds this instruction when executing IPI interruption transmission instruction Execution will lead to some virtual processor receive virtual IP address I interruption, then according to standard mode executing this IPI send instruction Except, also additionally execute the process included the following steps:

1), if the vmid for including in the f_info information of current logic processor is virtual value, processing terminate.Otherwise after Continue following process.

2) it, obtains current IPI and interrupts the corresponding logic processor number dest_cpu of transmission instruction.

3), according to the f_info information of current logic processor, obtaining target virtual processor number is that dest_ virtually locates Manage device.

4) virtual processor of current logic processor, is updated into logic processor routing table, dest_ virtual processor Corresponding logic processor is dest_cpu.

5), processing terminate.

In the previous embodiment of the application, logic processor all includes that a virtual processor is routed to logic processor Table, the virtual processor is transparent to VMM software to logic processor routing table, i.e., VMM software is unaware.In virtualization mould Under formula, when logic processor executes IPI transmission instruction, target virtual processor number can be translated as patrolling according to this routing table Volume processor number, and submit virtual IP address I to interrupt injection notice to the logic processor obtained after translation.Logic processor is being received After interrupting injection notice to virtual IP address I, this virtual IP address I is currently running in confirmation and interrupts corresponding target virtual processor When, just interrupted to current virtual processor injection virtual IP address I；Logic processor is executing IPI transmission under non-virtualized mode When instruction, corresponding list item of the virtual processor into logic processor routing table can be filled automatically.

The embodiment of the present application can guarantee the void that logic processor can be directly currently running to some in virtualization mode Quasi- processor sends IPI and interrupts, and is capable of handling the situation of " target virtual processor currently practical and not running ".

In the embodiment of the present application, the logic processor of sender can be only capable of obtaining at destination virtual according to routing logic Manage the logic processor where device, the interruption description information of not direct manipulation of objects virtual processor.The advantages of this mode Be: 1) when routing table is non-globally shared, adaptive building routing table is may be implemented in the embodiment of the present application.2) in virtual interrupt There was only a kind of information transfer channel (i.e. interruption Delivery Information) when delivery, between logic processor, there is no need to be directed to multiple types The synchronizing information problem for needing to solve when type information is transmitted, simplifies the treatment process between two logic processors.

Other embodiments of the application, the virtual processor of VM to logic processor routing table is no longer logic processor Privately owned data structure, but one uses global data knot by logic processor all in entire processor socket is shared Structure.For example, numbered according to<vm, virtual processor number>hashed value, general<vm numbers, virtual processor number, logic Processor number > is stored in the storage region in socket (such as in cache).When logic processor load operating virtual processor When (such as when the x86 processor load corresponding VMCS data structure of virtual processor), logic processor according to current virtual at The number of device, number, the current logic processor number of current virtual processor place virtual machine are managed, hash table is updated.When patrolling When volume processor unloading virtual processor when VMCS data structure (such as x86 processor unloading virtual processor corresponding), patrol Processor is collected according to the number of current virtual processor, the number of current virtual processor place virtual machine, current logic processing Device number, by hash table<vmid, virtual processor id>corresponding list item deletes.

In the previous embodiment of the application, logic processor can route to avoid storage virtual processor to logic processor Table, and the building speed of routing table is faster.

Other embodiments of the application, virtual processor to logic processor routing table are stored in memory, are transporting When row virtual processor, each logic processor corresponds to a virtual processor pointer, which has been directed toward virtual processor To the position of logic processor routing table in memory.Virtual processor to logic processor routing table and logic processor not It must be one-to-one relationship, for example, virtual processor pointer can be defined within vmcs structure for X 86 processor In, so that, due to having switched vmcs, logic processor uses different virtual places instead automatically when executing different virtual processors Manage device subframe.

When virtual processor to logic processor routing table is stored in the region of memory for allowing processor to be cached, Processor can use its cache mechanism, realize for virtual processor to the quick-searching of logic processor routing table.

When logic processor load operating virtual processor (for example x86 processor load virtual processor is corresponding When VMCS data structure), void pointed by virtual processor pointer (i.e. virtual processor _ rte) is directly arranged in logic processor Intend processor to logic processor routing table.Such as: if the value of virtual processor subframe is 0x10000, each table in routing table Item occupies 2 bytes, and when logic processor 10 is in the virtual processor that load number is 80, logic processor 10 will be memory 2 bytes at 0x100a0 are set as 10.

When logic processor unloads virtual processor (such as the corresponding VMCS number of x86 processor unloading virtual processor When according to structure), logic processor directly removes corresponding list item of the virtual processor into logic processor routing table.Such as: if The value of virtual processor pointer is 0x10000, each list item occupies 2 bytes in routing table, when logic processor 10 is unloading When the virtual processor that number is 80,2 bytes at memory 0x100a0 will be set as invalid value (such as by logic processor 10 0xffff)。

In other embodiments of the application, src_cpu information is contained in pintr_info, wherein src_cpu is indicated " executing the logic processor number that virtual IP address I sends operation ", for example, if virtual processor 20 currently operation number is 10 On logic processor, virtual processor 20 under virtualization mode to virtual processor 30 send IPI interrupt, current virtual processing Device is to logic processor routing table instruction " virtual processor 30 is located on the logic processor that number is 11 " and currently without other Logic processor is delivered to the logic processor that number is 11 to interrupt, then this IPI sending action of virtual processor 20 will lead to The src_cpu of the pintr_info for the logic processor that number is 11 becomes 10.

As shown in Figure 10, notify_if is asked for logic processor under virtualization mode provided by the embodiments of the present application The processing flow schematic diagram asked.Virtual interrupt note is received by notify_if in the logic processor of virtualization mode operation When entering to notify, the process included the following steps is executed:

2), if the virtual processor number for including in cached_info goes to step 15) less than 0.Wherein, virtual place Device number is managed less than 0, indicates that the virtual processor is illegal.

3), if the corresponding virtual processor id of current logic processor is not equal to the virtual place recorded in cached_info Reason device number or the corresponding vmid of current logic processor then go to step not equal to the vmid recorded in cached_info 6)。

4), the information recorded according to cached_info injects virtual interrupt to current virtual processor.

5), the next pintr_info of notice pintr_info arbitrated logic clearance sends request, and completes for " virtual The processing of interruption injection notice ".

6), according to the information in cached_info, the f_info of this logic processor, vmid cached_ are filled in Respective value in info.

7) src_cpu for including in cached_info, is obtained.

If 8), src_cpu is not located at this socket, step 9) is gone to, step 11) is otherwise gone to.

9) recv_if message, void in the virtual processor number cached_info that message body includes, are sent to src_cpu Quasi- processor number presses " position " negated value.Such as: if processor maximum can only support 32767 virtual processors, when Virtual processor number is 1 in cached_info, and virtual processor number is 0xfffe in this recv_if, and vm number is Number in cached_info.

10), the next pintr_info of notice pintr_info arbitrated logic clearance sends request, and ends processing Journey.

11) it, sends and requests to the pintr_info arbitrated logic of src_cpu, wait its all-clear.

It 12), will be after virtual processor number be negated by " position " in vmid, cached_info for including in cached_info Value be put into the delivery interrupt storage area pintr_info of src_cpu.

13), using notify_if, src_cpu is notified to carry out the injection of virtual IP address I interruption.

14), the next pintr_info of notice pintr_info arbitrated logic clearance sends request, exits virtualization operation Mode, and terminate the processing for " virtual interrupt injection notice ".

15) virtual processor number included in cached_info is negated by " position ", obtains true virtual place Manage device number r virtual processor.

If 16), the corresponding vmid of current logic processor is equal with the virtual machine number specified in cached_info, By virtual processor used in logic processor into logic processor routing table, the corresponding list item setting of r virtual processor For invalid value.

17), the next pintr_info of notice pintr_info arbitrated logic clearance sends request, and completes for virtual Interrupt the processing of injection notice.

When the logic processor of non-virtualized mode operation receives virtual interrupt injection notice by notify_if, Execute the process included the following steps:

2), if the virtual processor number for including in cached_info goes to step 5) less than 0.

3), according to the information in cached_info, the f_info of this logic processor, vmid cached_ are filled in Respective value in info.

4), can let pass next pintr_info of notice pintr_info arbitrated logic sends request, and executes Interrupt handling routine corresponding to notify_vector, and terminate the processing for virtual interrupt injection notice；

5) virtual processor number included in cached_info is negated by " position ", obtains true virtual processing Device number r virtual processor.

6), if the corresponding vmid of logic processor is identical as the virtual machine number specified in cached_info, by logic For virtual processor used in processor into logic processor routing table, the corresponding list item of r virtual processor is set as invalid Value.

7), let pass next pintr_info of notice pintr_info arbitrated logic sends request, completes in virtual The processing of disconnected injection notice.

In other embodiments of the application, logic processor also provides modification virtual processor and routes to physical processor The support scheme (such as instruction, particular register) of table.Such as it is a kind of it is feasible be achieved in that, be triggered in this support scheme When, current logic processor modifies to itself addressable virtual processor to physical processor routing table.It is for another example another Kind is feasible to be achieved in that: logic processor can notify other logic processors modifications empty using inter-processor communication mechanism Intend processor to logic processor routing table.

The freedom degree that the embodiment of the present application can give software bigger facilitates and carries out virtual processor to logic processor routing The building of table.Relative to previous embodiment, the embodiment of the present application can by software realization it is non-frequently occur " need to notify IPI Sender updates virtual processor to logic processor routing table " situation, thus the hardware design of simplified processor.

The embodiment of the present application may include the following technical solution:

(1) logic processor has the mechanism of " available virtual processor to logic processor corresponding relationship ", i.e. logic The newly-increased configuration of processor " inquiring the logic processor that this virtual processor is currently located according to virtual processor number to number " Function, i.e., the functions such as newly-increased " virtual processor Address translation module ", sender are only capable of obtaining destination virtual according to routing logic Logic processor where processor, the interruption description information of not direct manipulation of objects virtual processor:

1, it can be virtual processor privately owned inside logic processor to logic processor routing table；

2, can be shared by logic processors all in socket<vm mark, virtual processor mark>at logic Manage device routing table；

3, can be storage in memory, corresponding each virtual machine is a, virtual processor to logic processor road By table, and the logic processor internal record memory address of the unique routing table of this virtual machine；

4, " the virtual processor Address translation module " etc. between multiple logic processors can be shared；

5, when routing table is non-globally shared, adaptive building routing table is may be implemented (see saying for embodiment 1 in the method It is bright)；

6, when virtual interrupt is delivered, only a kind of information transfer channel (interrupting Delivery Information) between logic processor.

(2) logic processor has under virtualization mode not by VMM, new by the target logic processor of acquisition Whether " virtual processor Address translation module " the monitoring objective virtual processor increased is currently running, to judge whether to need The intervention of VMM software:

If 1, judgement display current goal virtual processor is currently running, sender is by newly-increased " in virtual processor " sending end interface " submodule of disconnected transceiver module " sends virtual IP address I interruption injection request in target logic processor new " interrupting injection " submodule of " the virtual processor interrupt reception and dispatch module " increased:

Disappear when the interruption injection submodule of target logic processor receives the injection of the interruption from other logic processors When breath, whether newly-increased " object matching module " judgement is currently currently running " interrupting the corresponding virtual processor of injection message ":

If 1) judgement is currently running, direct notification instruction processing logic module injects IPI to current virtual processor It interrupts, it is straight-through to complete IPI interruption；

If 2) judgement is not being run, inject interrupts into the detail records of message to recipient increase newly " exception information is deposited Store up module ", and logic module is handled by " exception reporting module " notification instruction that recipient increases newly and carries out abnormality processing.Instruction Logic module is handled after receiving this exception reporting, if current just in virtualization mode, exits virtualization mode；Otherwise straight Switch through into abnormal conditions (as interrupted) process flow.

If 2, judgement display current goal virtual processor is in not running or blocked state, IPI is sent into the detailed of instruction Sender's exception information memory module is written in feelings, and exits virtualization mode.VMM software can be looked by sender's exception information Module is ask, obtains instruction processing logic module in the information being placed in sender's exception information memory module before.

3, " the virtual processor interrupt reception and dispatch module " etc. between multiple logic processors can be shared.

(3) in logic processor when virtual processor executes and exits virtualization mode due to IPI sends instruction, with reference to such as Upper (one) (two) mechanism, logic processor is by newly-increased configuration " sender's exception information storage/enquiry module ", and " recipient is different The functions such as normal reporting modules ", " recipient's exception information storage/enquiry module " have to VMM software and give away one's position virtual processing Device number and virtual IP address I interrupt the function of details, so that VMM software can exit virtualization mode in logic processor Afterwards, inquiry obtains the reason of exiting, and then the transmission process of virtual IP address I is completed using traditional mode.

Firstly, the embodiment of the present application solve the problems, such as it is as follows: send when IPI is interrupted and need the logical process of intended receiver Device number, but HVM can not obtain target processor number, and if HVM uses the IPI sending logic of standard, IPI will be sent to mistake Logic processor.

In the embodiment of the present application, logic processor has by newly-increased " virtual processor Address translation module " and " can obtain Virtual processor to logic processor corresponding relationship " mechanism；

In the embodiment of the present application, HVM can obtain target logic processor by " virtual processor Address translation module " Number.Sender is only capable of the logic processor where acquisition target virtual processor according to routing logic, does not manipulate mesh directly Mark the interruption description information of virtual processor.The advantages of this mode is: 1) when routing table is non-globally shared, the method can be with Realize adaptive building routing table.2) when virtual interrupt is delivered, there was only a kind of information transfer channel between logic processor (interrupting Delivery Information).

It is interrupted secondly, the virtual processor of the prior art must send IPI by VMM, if allowing to directly transmit in IPI Disconnected, then the virtual machine of malice may send IPI by the logic processor not used to virtual machine and interrupt, and cause system dead Machine or the normal work for influencing other virtual machines；

In the embodiment of the present application, logic processor has under virtualization mode not by VMM, is patrolled by the target of acquisition Collecting processor newly-increased " virtual processor Address translation module ", whether monitoring objective virtual processor is currently running, to judge Whether the intervention of VMM software is needed；

In the embodiment of the present application, if being judged at destination virtual by newly-increased " virtual processor Address translation module " monitoring Reason device is currently running, then issues virtual IP address I and interrupt injection request, and " the object matching module " that target logic processor is newly-increased Determine currently whether be currently running " interrupting the corresponding virtual processor of injection message ", then can complete the virtual processor of HVM Between directly IPI communication.

Finally, the virtual processor of the prior art sends the method that IPI is interrupted by VMM, cause logic processor can not The situation of correct processing " receive the virtual processor that virtual IP address I is interrupted and be not currently in operation, even in blocked state "；

In the embodiment of the present application, virtualization mould is exited because virtual processor executes due to IPI sends instruction in logic processor When formula, have to VMM software give away one's position virtual processor number and virtual IP address I interrupt details function mechanism；

In the embodiment of the present application, allow VMM software after logic processor exits virtualization mode, inquiry is moved back Out the reason of, and then using the transmission process of traditional mode completion virtual IP address I.

It should be noted that for the various method embodiments described above, for simple description, therefore, it is stated as a series of Combination of actions, but those skilled in the art should understand that, the application is not limited by the described action sequence because According to the application, some steps may be performed in other sequences or simultaneously.Secondly, those skilled in the art should also know It knows, the embodiments described in the specification are all preferred embodiments, related actions and modules not necessarily the application It is necessary.

For the above scheme convenient for better implementation the embodiment of the present application, phase for implementing the above scheme is also provided below Close device.

A kind of logic processor that the embodiment of the present application also provides, the logic processor are specially at the first logic above-mentioned Device is managed, is please referred to shown in Figure 11, the first logic processor 1100 provided by the embodiments of the present application, may include: processing module 1101, sending module 1102, wherein

Processing module 1101 interrupts IPI for after the first logic processor enters virtualization mode, obtaining processor Information, the IPI information include: the mark and virtual interrupt information of target virtual processor；

The processing module 1101 is also used to carry out virtual processor address to the mark of the target virtual processor to turn over It translates, obtains the target logic processor where the target virtual processor is currently run；

Sending module 1102, for sending the IPI information to the target logic processor.

In some embodiments of the present application, the processing module 1101 is also used to the target virtual processor After mark carries out virtual processor address translation, determine the target virtual processor not in any one logic processor When operation, the IPI information is stored, and exit the virtualization mode；

It is described to be also used to notify that the first logic processor described in monitor of virtual machine VMM stores for the sending module 102 IPI information.

In some embodiments of the present application, the processing module 1101, be also used to when first logic processor to When the target logic processor sends IPI information failure, the IPI information is stored, and exit the virtualization mode；

The sending module 102 is also used to notify the first logic processor described in VMM to store the IPI information.

In some embodiments of the present application, the sending module 1102 is also used to send out to the target logic processor Send the mark of the virtual machine VM where the target virtual processor.

In some embodiments of the present application, the processing module 1101, specifically for being arrived by inquiring virtual processor The routing table of logic processor carries out virtual processor address translation to the mark to the target virtual processor.

In some embodiments of the present application, the routing table of the virtual processor to logic processor is stored in described In the storage region of one logic processor；Or,

The routing table of the virtual processor to logic processor is stored in available where first logic processor In the storage region of the processor of physics plug；Or,

The routing table of the virtual processor to logic processor is stored into memory.

In some embodiments of the present application, first logic processor has to be arrived for modifying the virtual processor The interface of the routing table of logic processor.

Another logic processor that the embodiment of the present application also provides, the logic processor are specially the second logic above-mentioned Processor please refers to shown in Figure 12, and the second logic processor 1200 provided by the embodiments of the present application, may include: receiving module 1201, processing module 1202, wherein

Receiving module 1201, for receiving the first logical process after the second logic processor enters virtualization mode The IPI information that device is sent, the IPI information includes: the mark and virtual interrupt information of target virtual processor；

Processing module 1202, for carrying out virtual interrupt to second virtual processor according to the virtual interrupt information Injection processing, second virtual processor is that second logic processor enters the virtual place being currently running after Virtualization Mode Manage device.

In some embodiments of the present application, the processing module 1202 is also used to when second virtual processor When mark is not identical as the mark of the target virtual processor, the IPI information is stored, and exit the virtualization mode.

In some embodiments of the present application, the processing module 1202 is also used to the receiving module 1201 and receives the After the IPI information that one logic processor is sent, identifying whether and destination virtual processing for the second virtual processor is determined The mark of device is identical；

The processing module 1202 is also used to mark and the target virtual processor when second virtual processor Mark it is identical when, triggering executes following steps: being carried out in virtual according to the virtual interrupt information to the second virtual processor Disconnected injection processing.

It should be noted that the contents such as information exchange, implementation procedure between each module/unit of above-mentioned apparatus, due to The application embodiment of the method is based on same design, and bring technical effect is identical as the application embodiment of the method, particular content Reference can be made to the narration in embodiment of the method shown in the application is aforementioned, details are not described herein again.

The embodiment of the present application also provides a kind of computer storage medium, wherein and the computer storage medium is stored with program, It includes some or all of record step in above method embodiment that the program, which executes,.

It should be noted that in the embodiment of the present application processor can also be known as central processing unit (full name in English: Central Processing Unit, English abbreviation: CPU).In specific application, the various components of processor pass through total linear system System is coupled.Processor can be a kind of IC chip, the processing capacity with signal.During realization, on Each step for stating method can be completed by the integrated logic circuit of the hardware in processor or the instruction of software form.It is above-mentioned Processor can be general processor, digital signal processor (full name in English: digital signal processing, English Text abbreviation: DSP), specific integrated circuit (full name in English: Application Specific Integrated Circuit, English Text is abridged: ASIC), (full name in English: Field-Programmable Gate Array, English contract field programmable gate array Write: FPGA) either other programmable logic device, discrete gate or transistor logic, discrete hardware components.It may be implemented Or disclosed each method, step and logic diagram in execution the embodiment of the present application.General processor can be microprocessor Or the processor is also possible to any conventional processor etc..The step of method in conjunction with disclosed in the embodiment of the present application, can be with Be embodied directly in hardware decoding processor and execute completion, or in decoding processor hardware and software module combination executed At.

In addition it should be noted that, the apparatus embodiments described above are merely exemplary, wherein described as separation The unit of part description may or may not be physically separated, component shown as a unit can be or It can not be physical unit, it can it is in one place, or may be distributed over multiple network units.It can be according to reality Border needs to select some or all of the modules therein to realize the purpose of the embodiment of the present application scheme.In addition, the application mentions In the Installation practice attached drawing of confession, the connection relationship between module indicates there is communication connection between them, specifically may be implemented For one or more communication bus or signal wire.

Through the above description of the embodiments, it is apparent to those skilled in the art that the application can be with It is realized with hardware realization or firmware realization or their combination mode.It when implemented in software, can be by above-mentioned function Storage in computer-readable medium or as on computer-readable medium one or more instructions or code transmitted.Meter Calculation machine readable medium includes computer storage media and communication media, and wherein communication media includes convenient for from a place to another Any medium of a place transmission computer program.Storage medium can be any usable medium that computer can access.With For this but be not limited to: computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storages, disk Storage medium or other magnetic storage apparatus or can be used in carry or store have instruction or data structure form expectation Program code and can be by any other medium of computer access.Furthermore.Any connection appropriate can become computer Readable medium.For example, if software is using coaxial cable, optical fiber cable, twisted pair, Digital Subscriber Line (DSL) or such as The wireless technology of infrared ray, radio and microwave etc is transmitted from website, server or other remote sources, then coaxial electrical The wireless technology of cable, optical fiber cable, twisted pair, DSL or such as infrared ray, wireless and microwave etc includes in affiliated medium In fixing.As used in this application, disk (Disk) and dish (disc) are logical including compression optical disc (CD), laser disc, optical disc, number With optical disc (DVD), floppy disk and Blu-ray Disc, the usually magnetic replicate data of which disk, and dish is then with laser come optical duplication Data.Combination above should also be as including within the protection scope of computer-readable medium.

In the above-described embodiments, can come wholly or partly by software, hardware, firmware or any combination thereof real It is existing.When implemented in software, it can entirely or partly realize in the form of a computer program product.

The computer program product includes one or more computer instructions.Load and execute on computers the meter When calculation machine program instruction, entirely or partly generate according to process or function described in the embodiment of the present application.The computer can To be general purpose computer, special purpose computer, computer network or other programmable devices.The computer instruction can be deposited Storage in a computer-readable storage medium, or from a computer readable storage medium to another computer readable storage medium Transmission, for example, the computer instruction can pass through wired (example from a web-site, computer, server or data center Such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wireless (such as infrared, wireless, microwave) mode to another website Website, computer, server or data center are transmitted.The computer readable storage medium can be computer and can deposit Any usable medium of storage either includes that the data storages such as one or more usable mediums integrated server, data center are set It is standby.The usable medium can be magnetic medium, (for example, floppy disk, hard disk, tape), optical medium (for example, DVD) or partly lead Body medium (such as solid state hard disk Solid State Disk (SSD)) etc..

Claims

1. a kind of communication means characterized by comprising

After the first logic processor enters virtualization mode, first logic processor interrupts IPI between obtaining processor Information, the IPI information include: the mark and virtual interrupt information of target virtual processor；

First logic processor carries out virtual processor address translation to the mark of the target virtual processor, obtains institute State the target logic processor where target virtual processor is currently run；

First logic processor sends the IPI information to the target logic processor.

2. the method according to claim 1, wherein the method also includes:

After first logic processor carries out virtual processor address translation to the mark of the target virtual processor, really The fixed target virtual processor is not when any one logic processor is run, described in the first logic processor storage IPI information, and exit the virtualization mode；

First logic processor described in the first logic processor notice monitor of virtual machine VMM stores the IPI information.

3. the method according to claim 1, wherein the method also includes:

When first logic processor, which sends the IPI information to the target logic processor, to fail, described first is patrolled It collects processor and stores the IPI information, and exit the virtualization mode；

First logic processor described in the first logic processor notice VMM stores the IPI information.

4. the method according to claim 1, wherein the method also includes:

First logic processor send the target virtual processor to the target logic processor where virtual machine The mark of VM.

5. method according to claim 1 to 4, which is characterized in that first logic processor is to described The mark of target virtual processor carries out virtual processor address translation, comprising:

First logic processor passes through inquiry virtual processor to the routing table of logic processor, to the destination virtual The mark of processor carries out virtual processor address translation.

6. according to the method described in claim 5, it is characterized in that, the routing table of the virtual processor to logic processor is deposited Storage is in the storage region of first logic processor；Or,

The routing table of the virtual processor to logic processor, which is stored in where first logic processor, can be used for object In the storage region for managing the processor of plug；Or,

7. according to the method described in claim 5, it is characterized in that, first logic processor has for modifying the void The interface of routing table of the quasi- processor to logic processor.

8. a kind of communication means characterized by comprising

After the second logic processor enters virtualization mode, second logic processor receives the first logic processor hair The processor sent interrupts IPI information, and the IPI information includes: the mark and virtual interrupt information of target virtual processor；

Second logic processor carries out at virtual interrupt injection the second virtual processor according to the virtual interrupt information Reason, second virtual processor is that second logic processor enters the virtual processor being currently running after Virtualization Mode.

9. according to the method described in claim 8, it is characterized in that, the method also includes:

When the mark of second virtual processor is not identical as the mark of the target virtual processor, second logic Processor stores the IPI information, and exits the virtualization mode.

10. method according to claim 8 or claim 9, which is characterized in that the method also includes:

After second logic processor receives the IPI information that the first logic processor is sent, second logic processor Determine the second virtual processor identify whether it is identical as the mark of the target virtual processor；

When the mark of second virtual processor is identical as the mark of the target virtual processor, triggering executes following step Rapid: second logic processor carries out at virtual interrupt injection the second virtual processor according to the virtual interrupt information Reason.

11. a kind of logic processor, which is characterized in that the logic processor is the first logic processor, first logic Processor includes:

Processing module interrupts IPI information, institute for after the first logic processor enters virtualization mode, obtaining processor State the mark and virtual interrupt information that IPI information includes: target virtual processor；

The processing module is also used to carry out virtual processor address translation to the mark of the target virtual processor, obtain The target virtual processor currently runs the target logic processor at place；

Sending module, for sending the IPI information to the target logic processor.

12. logic processor according to claim 11, which is characterized in that the processing module is also used to the mesh After the mark progress virtual processor address translation for marking virtual processor, determine the target virtual processor not any When one logic processor operation, the IPI information is stored, and exit the virtualization mode；

The sending module is also used to notify the first logic processor described in monitor of virtual machine VMM to store the IPI letter Breath.

13. logic processor according to claim 11, which is characterized in that the processing module is also used to when described the When one logic processor sends IPI information failure to the target logic processor, the IPI information is stored, and exit The virtualization mode；

The sending module is also used to notify the first logic processor described in VMM to store the IPI information.

14. logic processor according to claim 11, which is characterized in that the sending module is also used to the mesh Mark logic processor sends the mark of the virtual machine VM where the target virtual processor.

15. logic processor described in any one of 1 to 14 according to claim 1, which is characterized in that the processing module, tool Body is used for the routing table by inquiry virtual processor to logic processor, carries out to the mark to the target virtual processor Virtual processor address translation.

16. logic processor according to claim 15, which is characterized in that the virtual processor to logic processor Routing table is stored in the storage region of first logic processor；Or,

17. logic processor according to claim 15, which is characterized in that first logic processor has for repairing Change the virtual processor to logic processor routing table interface.

18. a kind of logic processor, which is characterized in that the logic processor is the second logic processor, second logic Processor includes:

Receiving module, for after the second logic processor enters virtualization mode, receiving what the first logic processor was sent Processor interrupts IPI information, and the IPI information includes: the mark and virtual interrupt information of target virtual processor；

Processing module, for being carried out at virtual interrupt injection according to the virtual interrupt information to second virtual processor Reason, second virtual processor is that second logic processor enters the virtual processor being currently running after Virtualization Mode.

19. logic processor according to claim 18, which is characterized in that the processing module is also used to when described the When the mark of two virtual processors is not identical as the mark of the target virtual processor, the IPI information is stored, and exit institute State virtualization mode.

20. logic processor described in 8 or 19 according to claim 1, which is characterized in that the processing module is also used to described Receiving module receive the first logic processor send IPI information after, determine the second virtual processor identify whether and institute The mark for stating target virtual processor is identical；

The processing module is also used to mark and the mark phase of the target virtual processor when second virtual processor Meanwhile triggering and executing following steps: the second virtual processor being carried out at virtual interrupt injection according to the virtual interrupt information Reason.

21. a kind of logic processor, which is characterized in that the logic processor includes: processing module, memory module；The place Mutual communication is carried out between reason module, the memory module；

The memory module is for storing instruction；

The processing module is used to execute the described instruction in the memory module, executes such as claim 1 to 7 or right and wants Method described in asking any one of 8 to 10.

22. a kind of computer readable storage medium, including instruction, when run on a computer, so that computer executes such as Method described in any one of claim 1 to 7 or claim 8 to 10.

23. a kind of computer program product comprising instruction, when run on a computer, so that computer executes such as right It is required that 1 to 7 or the described in any item methods of claim 8 to 10.