CN110148623A - Thin film transistor (TFT) and its manufacturing method, device, display base plate and device - Google Patents

Abstract

This application discloses a kind of thin film transistor (TFT) and its manufacturing method, device, display base plate and devices, belong to technical field of semiconductors.The active layer (012) of thin film transistor (TFT) (01) includes: the source region (0121) successively arranged, channel region (0122) and drain region (0123).Source region (012) includes the polysilicon doped with the first ion, and channel region (0122) includes the polysilicon doped with the second ion, and drain region (0123) includes the polysilicon doped with third ion.Wherein, the first ion and third ion are P-type ion, and the second ion is N-type ion；Alternatively, the first ion and third ion are N-type ion, and the second ion is P-type ion.The application reduces the leakage current of thin film transistor (TFT), improves the display effect of display device.

Description

Thin film transistor and its manufacturing method, device, display substrate and device

technical field

The present application relates to the technical field of semiconductors, in particular to a thin film transistor and its manufacturing method, device, display substrate and device.

Background technique

Thin film transistors are widely used in display devices and greatly improve the performance of the display devices. The thin film transistor includes: a gate and an active layer, wherein the active layer includes: a source region, a drain region, and a channel region, and the source region and the drain region contain N-type or P-type dopants, and the channel region is present symptoms.

By applying different electrical signals to the gate, the active layer can be controlled to be turned on and off, so as to achieve the purpose of turning on and off the thin film transistor. Wherein, when a conduction electrical signal is applied to the gate, a channel is formed in the channel region of the active layer, the source region and the drain region are electrically connected through the channel, the active layer is turned on, and the thin film transistor is in an open state. . When a turn-off electrical signal is applied to the gate, the channel in the channel region disappears, the source region and the drain region cannot be electrically connected, the active layer is turned off, and the thin film transistor is in an off state at this time.

However, in the related art, when a turn-off electrical signal is applied to the gate, the source region and the drain region can still transmit current through the channel region (the current is called leakage current), resulting in a decrease in the performance of the thin film transistor and affecting product characteristics.

Contents of the invention

The present application provides a thin film transistor and its manufacturing method, device, display substrate and device, which can solve the problem in the prior art that the thin film transistor cannot be closed normally due to the existence of leakage current. The technical solution is as follows:

In a first aspect, a structure of a thin film transistor is provided. The active layer of the thin film transistor includes: a source region, a channel region and a drain region arranged in sequence.

The source region includes polysilicon doped with first ions, the channel region includes polysilicon doped with second ions, and the drain region includes polysilicon doped with third ions;

Wherein, both the first ion and the third ion are P-type ions, and the second ion is N-type ion; or, both the first ion and the third ion are N-type ion, and the second ion is P-type ion.

Optionally, the thin film transistor further includes: a gate pattern; an orthographic projection area of the gate pattern on the active layer completely overlaps with the channel region.

The active layer also includes: a source connection region and a drain connection region;

The source connection region is located between the source region and the channel region, and the source connection region includes polysilicon, or, the source connection region includes polysilicon doped with fourth ions;

The drain connection region is located between the channel region and the drain region, and the drain connection region includes polysilicon, or the drain connection region includes polysilicon doped with fifth ions;

Wherein, when there is at least one connection region doped with ions in the source connection region and the drain connection region, for each connection region in the at least one connection region, the ion doping concentration of the connection region is less than that of the reference region in the active layer Ion doping concentration, the reference region is adjacent to the connection region, and the doped ions in the reference region and the doped ions in the connection region are both P-type ions or N-type ions.

In a second aspect, a method for manufacturing a thin film transistor is provided, and the method includes:

forming a polysilicon layer;

Doping various ions into the polysilicon layer to obtain an active layer;

Wherein, multiple ions include: first ions, second ions and third ions;

Both the first ion and the third ion are P-type ions, and the second ion is an N-type ion; or, both the first ion and the third ion are N-type ions, and the second ion is a P-type ion;

The active layer includes: a source region, a channel region and a drain region arranged in sequence; the source region includes polysilicon doped with first ions, the channel region includes polysilicon doped with second ions, and the drain region includes polysilicon doped with Polysilicon of the third ion.

Among them, various ions are doped into the polysilicon layer to obtain an active layer, including:

doping the polysilicon layer with second ions to obtain a channel region;

Doping the first ion and the third ion into the polysilicon layer doped with the second ion to obtain a source region and a drain region.

After doping the polysilicon layer with the second ions, the method further includes: forming a gate pattern on the polysilicon layer doped with the second ions, and the orthographic projection area of the gate pattern on the polysilicon layer completely overlaps with the channel region ;

Doping the polysilicon layer doped with the second ions with the first ions and the third ions includes: using the gate pattern as a mask, doping the polysilicon layer doped with the second ions with the first ions and the third ions ion.

It should be noted that the various ions also include: at least one ion in the fourth ion and the fifth ion, and the active layer also includes: a connection region corresponding to each ion in the at least one ion; wherein, the fourth ion corresponds to The source connection region is located between the source region and the channel region, the source connection region includes: polysilicon doped with the fourth ion; the drain connection region corresponding to the fifth ion is located between the channel region and the drain region, and the drain connection region includes : polysilicon doped with fifth ions; for each connection region in the source connection region and the drain connection region, the ion doping concentration of the connection region is less than the ion doping concentration of the reference region in the active layer, the reference region and the connection region Adjacent, and the doped ions in the reference region and the doped ions in the connecting region are both P-type ions or N-type ions;

Doping various ions into the polysilicon layer to obtain an active layer, including:

After doping the polysilicon layer doped with the second ion with the first ion and the third ion, doping at least one kind of ion into the polysilicon layer doped with the first ion, the second ion and the third ion, to obtain A linker region for each of the at least one ion.

After doping the polysilicon layer with second ions, the method further includes:

A conductive material layer and a photoresist pattern are sequentially formed on the polysilicon layer doped with second ions, the channel region is located in the orthographic projection area of the photoresist pattern on the polysilicon layer, and the area of the channel region is smaller than that of the photoresist The area of the orthographic projection area of the pattern on the polysilicon layer;

Using the photoresist pattern as a mask to expose, develop and cure the conductive material layer to obtain a gate pattern, and the positive projection area of the gate pattern on the polysilicon layer completely overlaps with the channel area;

removing the photoresist pattern;

Doping the first ion and the third ion into the polysilicon layer doped with the second ion includes: before removing the photoresist pattern, using the photoresist pattern as a mask, doping the polysilicon layer doped with the second ion doping the first ion and the third ion;

Doping at least one kind of ion into the polysilicon layer doped with the first ion, the second ion and the third ion includes:

After removing the photoresist pattern, using the gate pattern as a mask, doping at least one kind of ion into the polysilicon layer doped with the first ion, the second ion and the third ion.

In a third aspect, a thin film transistor device is provided, and the thin film transistor device includes the thin film transistor described in the first aspect.

In a fourth aspect, a display substrate is provided, which includes the thin film transistor described in the first aspect.

In a fifth aspect, a display device is provided, and the display device includes the display substrate described in the fourth aspect.

The beneficial effects brought by the technical solution provided by the application at least include:

In the active layer of the thin film transistor provided by the embodiment of the present invention, the type of ions doped in the channel region is different from the types of ions doped in the source region and the drain region, therefore, a gap between the channel region and the source region can be formed. A PN junction, a PN junction can also be formed between the channel region and the drain region, and the conduction directions of the two PN junctions are opposite. When one of the two PN junctions is turned on, the other is turned off. The turned-off PN junction has a high potential barrier so that electrons cannot pass through. At this time, there is no current transmission in the channel region, and the source region and the drain region cannot be electrically connected. In this way, the leakage current is basically eliminated, and the purpose of improving the display effect of the display device is realized.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the application. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic structural diagram of an active layer in a thin film transistor provided by an embodiment of the present invention;

Fig. 2 is a schematic diagram of a space charge region provided by an embodiment of the present invention;

3 is a schematic structural diagram of a PN junction provided by an embodiment of the present invention;

Fig. 4 is a schematic structural diagram of a diode provided by an embodiment of the present invention;

5 is a schematic diagram of the relationship curve of the voltage and current of the PN junction provided by the embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present invention;

7 is a schematic diagram of a working process of a thin film transistor provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of the working process of another thin film transistor provided by an embodiment of the present invention;

FIG. 9 is a schematic diagram of the working process of another thin film transistor provided by an embodiment of the present invention;

FIG. 10 is a schematic diagram of a voltage-current curve of a thin film transistor provided by an embodiment of the present invention;

Fig. 11 is a schematic structural diagram of an active layer in another thin film transistor provided by an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present invention;

FIG. 13 is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present invention;

FIG. 14 is a flowchart of another manufacturing method of a thin film transistor provided by an embodiment of the present invention;

FIG. 15 is a schematic diagram of a manufacturing process of a thin film transistor provided by an embodiment of the present invention;

Fig. 16 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

Fig. 17 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

Fig. 18 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

Fig. 19 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

Fig. 20 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

Fig. 21 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

Fig. 22 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

Fig. 23 is a flow chart of another manufacturing method of a thin film transistor provided by an embodiment of the present invention;

Fig. 24 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

Fig. 25 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

Fig. 26 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

Fig. 27 is a schematic diagram of the manufacturing process of another thin film transistor provided by an embodiment of the present invention;

FIG. 28 is a schematic diagram of a manufacturing process of another thin film transistor provided by an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.

In the related art, the channel region of the active layer in the thin film transistor is in an intrinsic state, and when an electrical shutdown signal is applied to the gate, the source region and the drain region can still transmit leakage current through the channel region, resulting in a decrease in the performance of the thin film transistor , affecting product characteristics. An embodiment of the present invention provides a thin film transistor, which can reduce the leakage current of the thin film transistor.

As an example, FIG. 1 is a schematic structural diagram of an active layer in a thin film transistor according to an embodiment of the present invention. The active layer 012 of the thin film transistor includes: a source region 0121 , a channel region 0122 and a drain region 0123 arranged in sequence. . The source region 0121 includes polysilicon doped with first ions, the channel region 0122 includes polysilicon doped with second ions, and the drain region 0123 includes polysilicon doped with third ions.

Wherein, both the first ion and the third ion are P-type ions, and the second ion is N-type ion; or, both the first ion and the third ion are N-type ion, and the second ion is P-type ion. It should be noted that the P-type ions are positive-valent ions (such as boron ions or arsenic ions or other ions); the N-type ions are negative-valent ions (such as phosphorus ions or gallium ions or other ions). The first ion and the third ion may be the same or different, as long as the first ion and the third ion are of the same type. In the embodiment of the present invention, the first ion and the third ion are both boron ions (P-type ions), and the second ions are phosphorus ions (N-type ions) as an example.

It should be noted that a semiconductor doped with P-type ions is called a P-type semiconductor, and there are a large number of holes in the P-type semiconductor; a semiconductor doped with N-type ions is called an N-type semiconductor, and there are a lot of electrons in the N-type semiconductor. . In the embodiment of the present invention, the channel region is a P-type semiconductor, and the source region and drain region are N-type semiconductors as an example. When the P-type semiconductor is adjacent to the N-type semiconductor, because there is a concentration difference between electrons and holes at the junction of the P-type semiconductor and the N-type semiconductor, electrons diffuse from the N-type semiconductor to the P-type semiconductor, making the N-type semiconductor The region close to the junction loses electrons and leaves positively charged impurity ions. The region where electrons are lost in the N-type semiconductor is called the N region; holes diffuse from the P-type semiconductor to the N-type semiconductor, and in the P-type semiconductor near the junction The region where the hole is lost and the negatively charged impurity ions are left, the region where the hole is lost in the P-type semiconductor is called the P region. At this time, the negatively charged impurity ions in the P region and the positively charged impurity ions in the N region form a space charge region as shown in Figure 2, and an internal electric field is formed in the space charge region, and the direction of the internal electric field is directed from the N region to P area.

The internal electric field formed in the space charge region can prevent carriers (electrons and holes) from diffusing, and can make the holes in the N-type semiconductor region drift to the P-type semiconductor region, and the electrons in the P-type semiconductor region drift to the N-type semiconductor region. drift, and this space charge region changes with the diffusion and drift of carriers. When the drift and diffusion of carriers in the P-type semiconductor region and the N-type semiconductor region reach a dynamic balance, the space charge region formed at the junction of the P-type semiconductor region and the N-type semiconductor region is also the PN junction shown in Figure 3 .

In the PN junction, the direction of the internal electric field is from the N-type semiconductor region to the P-type semiconductor region, and the conduction direction of the PN junction is from the P-type semiconductor to the N-type semiconductor. The structure including the PN junction shown in FIG. 3 may be the diode shown in FIG. 4 , which has unidirectional conductivity. FIG. 5 is a schematic diagram of a relationship curve between voltage and current of the PN junction shown in FIG. 3 . The abscissa in Figure 5 is the voltage U across the PN junction (the unit can be volts), the ordinate in Figure 5 is the current I in the PN junction (the unit can be ampere), and U _(BR) in Figure 5 is the PN junction When the absolute value of the reverse voltage on the PN junction is greater than the absolute value of the reverse breakdown voltage, the PN junction loses its unidirectional conduction characteristics. As shown in Figure 5, when a forward voltage is applied to both ends of the PN junction (that is, the potential of the P region is higher than that of the N region), the PN junction is turned on, and a current flows through the PN junction; When the reverse voltage (that is, the potential of the P region is lower than the potential of the N region), since the reverse voltage does not reach the reverse breakdown voltage U _(BR) of the PN junction, and the PN junction has a high potential barrier, the PN junction Carriers cannot move across this barrier, so the PN junction is turned off and no current flows in the PN junction.

As shown in FIG. 1 , in the embodiment of the present invention, the source region and the drain region of the active layer are doped with the same type of ions, but different from the type of ions doped in the channel region. Based on the relevant principles of PN junctions, it can be determined that a first PN junction can be formed between the channel region 0122 and the source region 0121, and a second PN junction can also be formed between the channel region 0122 and the drain region 0123, and the two PN junctions The conduction direction of the junction is opposite. When the potential applied to the source region 0121 is greater than the potential applied to the drain region 0123, the first PN junction is turned on and the second PN junction is turned off; when the potential applied to the source region 0121 is lower than the potential applied to the drain region 0123, The first PN junction is turned off and the second PN junction is turned on.

Optionally, in the active layer 012 of the thin film transistor provided in the embodiment of the present invention, the ion doping concentration of the source region 0121, the ion doping concentration of the channel region 0122 and the ion doping concentration of the drain region 0123 may be the same It can also be different, which is not limited in this embodiment of the present invention. In the embodiment of the present invention, the ion doping concentration of the source region 0121 is the same as that of the drain region 0123 , and the ion doping concentration of the source region 0121 is greater than that of the channel region 0122 as an example. Of course, it is also possible that the ion doping concentration of the source region 0121 is different from that of the drain region 0123, and both the ion doping concentration of the source region 0121 and the ion doping concentration of the drain region 0123 are greater than the ion doping concentration of the channel region 0122. doping concentration.

It should be noted that, usually, the potential barrier formed by the PN junction when a reverse voltage is applied is positively related to the ion doping concentration in the P-type semiconductor and the N-type semiconductor, that is, the higher the doping concentration of the P-type semiconductor or N-type semiconductor , the greater the potential barrier formed by the PN junction when a reverse voltage is applied. In this way, in the embodiment of the present invention, when the ion doping concentration of the N-type semiconductor (ie, the source region and the drain region) is greater than the ion doping concentration of the P-type semiconductor (ie, the channel region), the formed PN junction is applied The reverse voltage has a sufficiently large potential barrier, which can prevent electrons from passing through, and achieve the purpose of basically eliminating the leakage current in the channel region.

To sum up, in the active layer of the thin film transistor provided by the embodiment of the present invention, the type of ions doped in the channel region is different from the types of ions doped in the source region and the drain region. Therefore, the channel region and the source region A PN junction can be formed between the regions, and a PN junction can also be formed between the channel region and the drain region, and the conducting directions of the two PN junctions are opposite. When one of the two PN junctions is turned on, the other is turned off. The turned-off PN junction has a high potential barrier so that electrons cannot pass through. At this time, there is no current transmission in the channel region, and the source region and the drain region cannot be electrically connected. In this way, the leakage current is basically eliminated, and the purpose of improving the display effect of the display device is realized.

FIG. 6 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present invention. As shown in FIG. 6 , the thin film transistor includes: the active layer 012 and the gate pattern 014 in FIG. 1 . The orthographic projection area of the gate pattern 014 on the active layer 012 completely overlaps with the channel region 0122 .

It should be noted that when the orthographic projection area of the gate pattern 014 on the active layer 012 completely overlaps with the channel region 0122, the polysilicon layer can be doped with the gate pattern 014 as a mask to obtain an active layer 012 source region 0121 and drain region 0123. There is no need to use other masks to dope the polysilicon to obtain the source region 0121 and the drain region 0123 , which simplifies the manufacturing process of the thin film transistor. Optionally, the orthographic projection area of the gate pattern 014 on the active layer 012 may not completely coincide with the channel region 0122 , which is not limited in this embodiment of the present invention.

Please continue to refer to FIG. 6 , the thin film transistor may further include a gate insulating layer 013 , a source-drain insulating layer 015 and a source-drain pattern 016 . Wherein, the gate insulating layer 013 , the gate pattern 014 , the source-drain insulating layer 015 and the source-drain pattern 016 are sequentially arranged along a direction away from the active layer 012 . The source-drain pattern 016 may include: a source 0161 and a drain 0162, the source 0161 is electrically connected to the source region 0121 through the first via hole K1 penetrating the source-drain insulating layer 015 and the gate insulating layer 013, and the drain 0162 is electrically connected to the source region 0121 through the first via hole K1 penetrating the source-drain insulating layer 015 and the gate insulating layer 013. The drain insulating layer 015 and the second via hole K2 of the gate insulating layer 013 are electrically connected to the drain region 0123 .

The specific working process of the thin film transistor provided by the embodiment of the present invention will be described below by taking the channel region doped with P-type ions and the source and drain regions doped with N-type ions as an example.

For example, when no electric signal is applied to the gate of the thin film transistor, the first PN junction and the second PN junction formed in the active layer are shown in FIG. 7 . When the source region is applied with a positive potential and the drain region is applied with a negative potential, the current flows from the source region to the drain region, and the first PN junction is closed due to the reverse voltage applied (the potential of the P region is lower than that of the N region) off; the second PN junction is turned on due to the application of a forward voltage (the potential of the P region is higher than that of the N region). Due to the effect of the first PN junction, the source region cannot be electrically connected to the drain region, and the thin film transistor is in an off state.

When a turn-on electrical signal is applied to the gate (that is, the gate-source voltage is greater than the threshold voltage of the thin film transistor), the electron concentration in the region near the gate of the channel region increases to form a channel, as shown in FIG. 8 . At this time, due to the high electron concentration and low hole concentration in the channel, a PN junction cannot be formed with the source region or the drain region. Therefore, the source region can be electrically connected to the drain region through the channel formed in the channel region, and the thin film transistor is turned on.

When a turn-off electrical signal is applied to the gate (that is, the gate-source voltage is less than the threshold voltage), a large number of holes are accumulated in the channel region near the gate, as shown in FIG. 9 . Since the junction of the source region and the drain region has a high electron concentration and a higher hole concentration, the formed first PN junction has a higher potential barrier, therefore, under the action of the reverse voltage, the first PN junction is turned off, There is no leakage current transmission in the channel region, and the source region and the drain region cannot be electrically connected, and at this time, the thin film transistor is turned off.

When a turn-on or turn-off electrical signal is applied to the gate, the turn-on or turn-off effect of the thin film transistor on the current can be intuitively expressed by the voltage-current curve shown in Figure 10, and the abscissa in Figure 10 is the gate-source voltage V( The unit may be volt), and the ordinate is the current I in the channel region (the unit may be ampere). Moreover, in FIG. 10 , the threshold voltage (Vth for short) of the thin film transistor is 1 volt as an example.

As shown in Figure 10, when a turn-on signal is applied to the gate, the gate-source voltage (abbreviation: Vgs) is greater than the threshold voltage of 1 volt, the thin film transistor is turned on, and the current in the channel region increases significantly, and with the gate The source voltage continues to increase, and the current in the channel region increases rapidly. When a turn-off electrical signal is applied to the gate, the gate-source voltage is less than the threshold voltage of 1 volt, and the thin film transistor is turned off. At this time, the current in the channel region is as small as 10 ^-11 A, which can be ignored. It can be seen that the thin film transistor provided by the present application basically has no leakage current when it is turned off, and the thin film transistor has a better turn-off effect.

In addition, when the ions doped in the channel region of the thin film transistor are P-type ions, and the ions doped in the source region and the drain region are N-type ions, the working process of the thin film transistor is similar to the above situation. I won't go into details.

Optionally, the active layer in the thin film transistor in the above embodiment is the active layer shown in FIG. 1 as an example. Of course, the active layer in the thin film transistor may also have a different structure from the active layer in FIG. 1 .

As an example, FIG. 11 is a schematic structural diagram of an active layer in another thin film transistor according to an embodiment of the present invention. As shown in FIG. 11 , on the basis of FIG. 1 , the active layer 012 may further include: a source connection region 0124 and a drain connection region 0125 . The source connection region 0124 is located between the source region 0121 and the channel region 0122 . The drain connection region 0125 is located between the channel region 0122 and the drain region 0123 .

The source connection region 0124 may include polysilicon, or, the source connection region 0124 includes polysilicon doped with fourth ions. The drain connection region 0125 includes polysilicon, or, the drain connection region 0125 includes polysilicon doped with fifth ions.

It should be noted that, assuming that there is at least one (such as one or more) connection regions doped with ions in the source connection region and the drain connection region, for example, the source connection region is doped with fourth ions and the drain connection region is not doped, Either the drain connection region is doped with fifth ions and the source connection region is not doped, or the source connection region is doped with fourth ions and the drain connection region is doped with fifth ions. At this time, for each connection region in the at least one connection region, the ion doping concentration of the connection region is lower than the ion doping concentration of the reference region in the active layer, the reference region is adjacent to the connection region, and the reference region is doped with The ions and the doped ions in the connecting region are both P-type ions or N-type ions.

For example, if the active layer includes a source connection region, and the source connection region is doped with fourth ions, the reference region of the source connection region may be the source region or the channel region in the active layer. Wherein, when the source region is doped with P-type ions and the channel region is doped with N-type ions, the fourth ion can be a P-type ion, and its ion doping concentration is less than the ion doping concentration in the source region; or the fourth ion can be It is an N-type ion, and its ion doping concentration is lower than the ion doping concentration in the channel region. When the source region is doped with N-type ions and the channel region is doped with P-type ions, the fourth ion can be N-type ions, and its ion doping concentration is less than the ion doping concentration in the source region, or the fourth ion can be P type ions, and its ion doping concentration is less than the channel region ion doping concentration.

If the active layer includes a drain connection region, and the drain connection region is doped with fifth ions, the reference region of the drain connection region may be a channel region or a drain region in the active layer. Wherein, when the channel region is doped with P-type ions and the drain region is doped with N-type ions, the fifth ion can be P-type ions, and its ion doping concentration is less than the ion doping concentration in the channel region; or the fifth ion It can be N-type ions, and its ion doping concentration is lower than that of the ion doping concentration in the drain region. When the channel region is doped with N-type ions and the drain region is doped with P-type ions, the fifth ion may be N-type ions with an ion doping concentration lower than that in the channel region. Or the fifth ion may be a P-type ion, and its ion doping concentration is lower than that of the ion doping concentration in the drain region.

In the embodiment of the present invention, the active layer has a source connection region and a drain connection region, and the reference regions of the source connection region and the drain connection region are both channel regions, and the source connection region, the drain connection region and the channel region are doped The ions are all P-type ions as an example.

It should be noted that when the source connection region is added between the source region and the channel region, it is equivalent to adding an I region (intrinsic region) between the P region and the N region of the PN junction formed by the source region and the channel region. ), thus forming a PIN junction. When the drain connection region is added between the drain region and the channel region, an I region is added between the P region and the N region, which is equivalent to the PN junction formed between the drain region and the channel region, thereby forming a PIN junction. . Since the PIN junction and the PN junction also have unidirectional conductivity, when the active layer has a source connection region and a drain connection region, there is basically no leakage current in the channel region of the thin film transistor in an off state. At the same time, due to the increase of the intrinsic region, the recombination of electron-hole pairs (electrons from the N region and holes from the P region) can also be reduced, thereby increasing the number of carriers flowing in the active layer of the transistor in the on state. , to boost the transistor's on-state current.

The structure of the thin film transistor where the active layer shown in FIG. 11 is located may be as shown in FIG. 12 . As shown in FIG. 12 , the thin film transistor further includes a gate insulating layer 013 , a source-drain insulating layer 015 and a source-drain pattern 016 . The arrangement of the gate insulating layer 013, the source-drain insulating layer 015, and the source-drain pattern 016 can refer to the arrangement of the gate insulating layer, source-drain insulating layer, and source-drain pattern in FIG. I won't go into details.

In addition, in the embodiment of the present invention, the structure of the thin film transistor is the top gate structure shown in FIG. 6 and FIG. 12 as an example. Optionally, the structure of the thin film transistor may also be different from the top gate structure shown in FIG. 6 or FIG. , such as a thin film transistor structure may be a bottom gate structure.

To sum up, in the thin film transistor provided by the embodiment of the present invention, the active layer has a source connection region and a drain connection region. In this way, a PIN junction is formed in the connection area. Moreover, the PIN junction conducts in one direction and the potential barrier increases linearly, which can effectively prevent electrons from passing through when it is turned off, basically eliminate leakage current, and improve the display effect of the display device. At the same time, the PIN junction can well control the attenuation of the on-state current, reduce damage to the thin film transistor, and improve the service life of the thin film transistor.

Exemplarily, FIG. 13 is a flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present invention, which can be used to manufacture a thin film transistor provided by an embodiment of the present invention, such as the thin film transistor shown in FIG. 6 or FIG. 12 . As shown in Figure 13, the manufacturing method includes:

Step 1301, forming a polysilicon layer.

Step 1302, doping various ions into the polysilicon layer to obtain an active layer.

Wherein, the plurality of ions include: first ions, second ions and third ions. Both the first ion and the third ion are P-type ions, and the second ion is N-type ion; or, both the first ion and the third ion are N-type ion, and the second ion is P-type ion. The active layer includes: a source region, a channel region and a drain region arranged in sequence; the source region includes polysilicon doped with first ions, the channel region includes polysilicon doped with second ions, and the drain region includes polysilicon doped with Polysilicon of the third ion.

To sum up, in the thin film transistor manufactured by the method provided by the embodiment of the present invention, the type of ions doped in the channel region is different from the types of ions doped in the source region and the drain region. Therefore, the channel region and the source region A first PN junction can be formed between the regions, and a second PN junction can also be formed between the channel region and the drain region, and the conduction directions of the first PN junction and the second PN junction are opposite. When one of the two PN junctions is turned on, the other is turned off. The turned-off PN junction has a high potential barrier so that electrons cannot pass through. At this time, there is no current transmission in the channel region, and the source region and the drain region cannot be electrically connected. In this way, the leakage current is basically eliminated, and the purpose of improving the display effect of the display device is realized.

FIG. 14 is a flowchart of another method for manufacturing a thin film transistor provided by an embodiment of the present invention. This method can be used to manufacture the thin film transistor shown in FIG. 6. As shown in FIG. 14, the method can include:

Step 1401, forming a polysilicon layer.

When forming the polysilicon layer, an amorphous silicon material layer may first be formed on the base substrate, and then the amorphous silicon material layer is processed to obtain a polysilicon material layer. After that, the polysilicon material layer is processed by another patterning process to obtain the polysilicon layer 110 as shown in FIG. 15 .

Among them, when forming the amorphous silicon material layer on the substrate, methods such as coating, physical vapor deposition (English: Physical Vapor Deposition; abbreviation: PVD) or chemical vapor deposition (English: Chemical VaporDeposition; abbreviation: CVD) can be used. A layer of amorphous silicon material is formed on the base substrate to obtain an amorphous silicon material layer. Among them, PVD includes: physical deposition methods such as magnetron sputtering or thermal evaporation, and CVD includes chemical deposition methods such as plasma enhanced chemical vapor deposition (English: Plasma Enhanced Chemical Vapor Deposition; PECVD for short).

Step 1402 , forming a first pattern on the polysilicon layer, the first pattern has a hollow area.

After forming the polysilicon layer, a first pattern 210 as shown in FIG. 16 may be formed on the polysilicon layer. Moreover, the first pattern 210 has a hollow area 2101 , and the middle area in the polysilicon layer can be exposed through the hollow area 2101 in the first pattern.

For example, the material of the first pattern may be photoresist, metal or other materials.

On the one hand, if the material of the first pattern is photoresist, then in step 1402, a photoresist layer can be coated on the polysilicon layer first. Afterwards, the photoresist layer is exposed by using a mask plate, and then the exposed photoresist layer is developed to obtain a first pattern.

On the other hand, if the material of the first pattern is metal, then in step 1402, a metal material layer may be formed on the polysilicon layer first. Afterwards, the metal material layer is processed by a patterning process to obtain the first pattern.

It should be noted that, if the first pattern is made of other materials mentioned above, the process of forming the first pattern of other materials can refer to the process of forming the first pattern of metal material, which will not be repeated in this embodiment of the present invention.

Step 1403 , using the first pattern as a mask, doping the portion of the polysilicon layer not covered by the first pattern with second ions to obtain a channel region.

After the first pattern is formed, there are regions in the polysilicon layer not covered by the first pattern. At this time, in step 1403, the first pattern can be used as a mask to dope the region in the polysilicon layer to obtain the channel region 0122 as shown in FIG. 17 . There is still a region in the polysilicon layer that is not covered by the first pattern (such as region 01221 in FIG. 17 ), and in step 1403, this region in the polysilicon layer is not doped.

Optionally, the second ions may be P-type ions (such as boron ions or arsenic ions or other ions) or N-type ions (such as phosphorus ions or gallium ions or other ions). In the embodiments of the present invention, it is taken that the second ions are P-type ions as an example.

Step 1404, remove the first pattern.

After the channel region is obtained, the first pattern can be removed by a lift-off method, and the obtained structure is shown in FIG. 18 .

Step 1405 , sequentially forming a gate insulating material layer and a gate pattern on the polysilicon layer doped with the second ions.

For example, a gate insulating material layer and a conductive material layer may be sequentially formed on the polysilicon layer first; then, the conductive material layer is processed by a patterning process to obtain a gate pattern.

Wherein, the material of the gate insulating material layer may be silicon dioxide, nitrogen oxide or a composite material thereof, and the material of the conductive material layer may include metal or graphene.

For the method of forming the gate insulating material layer and the conductive material layer, please refer to the method for forming the amorphous silicon material layer in step 1401; for the process of forming the gate pattern by one-time patterning process for the conductive material layer, you can refer to the one-time patterning process in step 1401 The process of processing the polysilicon material layer to obtain the polysilicon layer.

In step 1405 , the gate insulating material layer 111 and the gate pattern 014 as shown in FIG. 19 can be obtained. The gate insulating material layer 111 covers the polysilicon layer, and the orthographic projection area of the gate pattern 014 on the polysilicon layer completely overlaps with the channel region 0122 .

In the actual manufacturing process, the orthographic projection area of the gate on the polysilicon layer may not completely coincide with the channel area. For example, the size of the orthographic projection area of the gate on the polysilicon layer may be slightly larger than the size of the channel region, or the size of the orthographic projection area of the gate on the polysilicon layer may be slightly smaller than the size of the channel region. No more explanations. For example, the size difference between the orthographic projection region of the gate on the polysilicon layer and the channel region may range from 0 micron to 1 micron, or from 0.6 micron to 0.8 micron. Wherein, the size of any area is: the diameter of the circumscribed circle of this area.

Step 1406 , using the gate pattern as a mask, doping the polysilicon layer doped with the second ions with the first ions and the third ions to obtain a source region and a drain region.

Since in step 1405, the orthographic projection of the formed gate pattern on the polysilicon layer covers the channel region, when doping the region other than the channel region in the polysilicon layer, the gate pattern can be used to cover the channel region. Doped. In step 1406, using the gate pattern as a mask, the polysilicon layer doped with the second ions is doped with the first ions and the third ions to obtain the source region 0121 and the drain region 0123 as shown in FIG. 20 . Moreover, as shown in FIG. 20 , the source region 0121 , the channel region 0122 and the drain region 0123 are arranged in sequence in the active layer 012 .

It should be noted that when the second ion doped in step 1403 is a P-type ion, the first ion and the third ion doped in step 1406 are both N-type ions; when the second ion doped in step 1403 When the ions are N-type ions, the first ions and the third ions doped in step 1406 are both P-type ions.

Step 1407 , forming a source-drain insulating material layer on the base substrate on which the gate pattern is formed.

For the process of forming the source-drain insulating material layer, reference may be made to the process of forming the non-polysilicon material layer in step 1401 , which will not be repeated in this embodiment of the present invention. The source-drain insulating material layer 112 formed in step 1407 can be shown in FIG. 21 , and the source-drain insulating material layer 112 covers the active layer 012 .

Step 1408 , forming a first via hole and a second via hole in the gate insulating material layer and the source-drain insulating material layer to obtain a gate insulating layer and a source-drain insulating layer.

After forming the source-drain insulating material layer, it is necessary to form the first via hole K1 and the second via hole K2 as shown in Figure 22 in the gate insulating material layer and the source-drain insulating material layer to obtain the gate insulating layer 013 and the source-drain Insulation layer 015. Wherein, the first via hole K1 and the second via hole K2 both penetrate the gate insulating layer 013 and the source-drain insulating layer 015, and the first via hole K1 communicates with the source region 0121 in the active layer 012, and the second via hole K2 communicates with the The drain region 0123 in the source layer 012.

Step 1409 , forming a source-drain pattern on the source-drain insulating layer.

After obtaining the gate insulating layer and the source-drain insulating layer, a source-drain pattern can be formed on the source-drain insulating layer. After step 1409 , the thin film transistor 01 as shown in FIG. 6 can be obtained. The source and drain patterns in the thin film transistor 01 include: a source pattern 0161 and a drain pattern 0162 . Wherein, the source pattern 0161 is electrically connected to the source region 0121 through the first via hole K1, and the drain pattern 0162 is electrically connected to the drain region 0123 through the second via hole K2.

It should be noted that in the embodiment of the present invention, the first ion and the third ion are doped into the polysilicon layer by using the gate pattern as a mask (please refer to step 1406 for details). Optionally, doping the polysilicon layer with the first ions and the third ions without using the gate pattern as a mask, and the step of doping the polysilicon layer with the first ions and the third ions may not be located in step 1406 .

For example, step 1406 may not be performed and between step 1404 and step 1405, a mask may be formed on the polysilicon layer doped with the second ion, and the polysilicon layer is doped with the first ion and the third ion through the mask , and then remove the mask.

For another example, step 1406 may not be performed, and after forming the gate insulating material layer and before forming the gate pattern, a mask may be formed on the gate insulating material layer, and the polysilicon layer is doped with the first ions and a third ion, after which the mask is removed.

For another example, step 1406 may not be performed, and between step 1407 and step 1408, a mask may be formed on the source-drain insulating material layer, and the polysilicon layer is doped with the first ions and the third ions through the mask, and then The mask is then removed.

To sum up, in the thin film transistor manufactured by the method provided by the embodiment of the present invention, the type of ions doped in the channel region is different from the types of ions doped in the source region and the drain region. Therefore, the channel region and the source region A first PN junction can be formed between the regions, and a second PN junction can also be formed between the channel region and the drain region, and the conduction directions of the first PN junction and the second PN junction are opposite. When one of the two PN junctions is turned on, the other is turned off. The turned-off PN junction has a high potential barrier so that electrons cannot pass through. At this time, there is no current transmission in the channel region, and the source region and the drain region cannot be electrically connected. In this way, the leakage current is basically eliminated, and the purpose of improving the display effect of the display device is achieved.

FIG. 23 is a flowchart of another manufacturing method of a thin film transistor provided by an embodiment of the present invention, which is used to manufacture the thin film transistor shown in FIG. 12. As shown in FIG. 23, the manufacturing method includes:

Step 2301, forming a polysilicon layer.

For step 2301, reference may be made to step 1401 in FIG. 14 , and details are not described here in this embodiment of the present invention.

Step 2302 , forming a first pattern on the polysilicon layer, the first pattern has a hollow area.

For step 2302, reference may be made to step 1402 in FIG. 14 , and details are not described here in this embodiment of the present invention.

Step 2303 , using the first pattern as a mask, doping the portion of the polysilicon layer not covered by the first pattern with second ions to obtain a channel region.

For step 2303, reference may be made to step 1403 in FIG. 14 , and details are not described here in this embodiment of the present invention.

Step 2304, remove the first pattern.

For step 2304, reference may be made to step 1404 in FIG. 14 , and details are not described here in this embodiment of the present invention.

Step 2305 , sequentially forming a gate insulating material layer, a conductive material layer and a photoresist pattern on the polysilicon layer doped with the second ions.

In step 2305, a gate insulating material layer, a conductive material layer and a photoresist layer are sequentially formed on the polysilicon layer doped with the second ions. Afterwards, the photoresist layer is exposed and developed to obtain a photoresist pattern. Wherein, the method for forming the gate insulating material layer, the conductive material layer and the photoresist layer may refer to the method for forming the amorphous silicon material layer in step 1401 in FIG. 14 .

The gate insulating material layer 111 , the conductive material layer 121 and the photoresist pattern 211 formed in step 2305 may be as shown in FIG. 24 . Wherein, the formed photoresist pattern 211 covers a partial area of the conductor material layer 121. At this time, the conductor material layer 121 has a coverage area 1211 covered by the photoresist pattern 211, and a non-covered area 1211 not covered by the photoresist pattern 211. Coverage area 1212. In addition, the orthographic projection area of the photoresist pattern 211 on the polysilicon layer is a partial area in the polysilicon layer, the channel region 0122 is located in the orthographic projection area of the photoresist pattern 211 on the polysilicon layer, and the area of the channel region 0122 is The area is smaller than the area of the orthographic projection of the photoresist pattern 211 on the polysilicon layer.

Step 2306 , using the photoresist pattern as a mask, exposing, developing and curing the conductive material layer to obtain a gate pattern, and the orthographic projection area of the gate pattern on the polysilicon layer completely overlaps with the channel area.

In step 2305, firstly, the photoresist pattern can be used as a mask to expose and develop the conductor material layer, so as to remove the uncovered area in the conductor material layer that is not covered by the photoresist pattern (such as the uncovered area in FIG. 24 ). District 1212). Moreover, the coverage area covered by the photoresist pattern in the conductive material layer (such as the coverage area 1211 in FIG. 24 ) is preserved.

Afterwards, the covering region 1211 in the conductor material layer can be cured, so that the size of the covering region 1211 is reduced and a gate pattern 014 as shown in FIG. 25 is formed, and the orthographic projection of the gate pattern 014 on the silicon layer region completely coincides with the channel region 0122.

Step 2307 , using the photoresist pattern as a mask, doping the polysilicon layer doped with the second ions with the first ions and the third ions to obtain a source region and a drain region.

In step 2306, the gate pattern is formed, and then the polysilicon layer doped with the second ion is doped with the first ion and the third ion using the photoresist as a mask to obtain the source region and the third ion as shown in FIG. 26 Drain area. At this time, the polysilicon layer includes: a source region 0121 , a channel region 0122 and a drain region 0123 arranged at intervals in sequence. Moreover, there is an undoped region 01211 between the source region 0121 and the channel region 0122 , and there is another undoped region 01231 between the drain region 0123 and the channel region 0122 .

Step 2308 , removing the photoresist pattern.

After obtaining the source region and the drain region, the photoresist pattern is removed, and the obtained structure is shown in FIG. 27 .

Step 2309, using the gate pattern as a mask, doping second ions into the polysilicon layer doped with first ions, second ions and third ions to obtain a source connection region doped with second ions, and doping Drain junction region doped with second ions.

Before step 2309, the polysilicon layer includes: a source region, a drain region, a channel region and two undoped regions, and the gate pattern only covers the channel region. In step 2309, the gate pattern can be used as a mask to dope the two undoped regions with second ions to obtain the source connection region 0124 and the drain connection region 0125 as shown in FIG. 28 .

Step 2310 , forming a source-drain insulating material layer on the base substrate on which the gate pattern is formed.

For step 2310, reference may be made to step 1406 in FIG. 14 , and details are not described here in this embodiment of the present invention.

Step 2311 , forming a first via hole and a second via hole in the gate insulating material layer and the source-drain insulating material layer to obtain a gate insulating layer and a source-drain insulating layer.

For step 2311, reference may be made to step 1407 in FIG. 14 , and details are not described here in this embodiment of the present invention.

Step 2312, forming a source-drain pattern on the source-drain insulating layer.

For step 2312, reference may be made to step 1408 in FIG. 14 , and details are not described here in this embodiment of the present invention. After step 2312, a thin film transistor as shown in FIG. 12 can be obtained.

Further, in step 2308, the photoresist pattern may not be removed, but in step 2308, the photoresist pattern is ashed, so that the size of the photoresist pattern is reduced to just cover the gate pattern. Afterwards, in step 2309 , the ashed photoresist pattern can be used as a mask to dope ions to one or more connection regions in the polysilicon layer doped with the first ions and the second ions. Afterwards, the photoresist pattern after the ashing treatment can be removed.

It should be noted that, in the embodiment shown in FIG. 23 , both the source connection region and the drain connection region are doped with ions as an example. In this case, in step 2309 , both undoped regions need to be doped with ions. Optionally, the source connection region or the drain connection region may also be doped with ions. In this case, in step 2309, only one of the two undoped regions needs to be doped with ions to obtain the source connection region and one connection region in the drain connection region, and the other undoped region in the two undoped regions is the other connection region in the source connection region and the drain connection region. Alternatively, neither the source connection region nor the drain connection region is doped with ions. In this case, the above step 2309 does not need to be performed, and in the two undoped regions formed in step 2308, one undoped region is the source connection region, and the other undoped region is the drain connection region.

In the embodiment shown in FIG. 23, it is also taken as an example that the reference regions of the source connection region and the drain connection region are both channel regions. At this time, the ions doped to each undoped region in step 2309 are the second ion. Optionally, when the source connection region is doped with ions, the reference region of the source connection region may not be the channel region (for example, the reference region is the source region), at this time, in step 2309, the corresponding undoped The ions doped in the impurity region are the first ions. When the drain connection region is doped with ions, the reference region of the drain connection region may not be a channel region (for example, the reference region is a drain region). The ion of is the third ion.

In addition, in the embodiment shown in FIG. 23, the active layer includes the source connection region and the drain connection region as an example. Of course, the active layer may also include only one connection region in the source connection region and the drain connection region. The present invention The embodiment does not limit this.

It should be noted that the step of doping the polysilicon layer with the first ions and the third ions in the embodiment of the present invention may not be performed at step 2307 .

For example, step 2307 may not be performed and between steps 2304 and 2305, a mask may be formed on the polysilicon layer doped with the second ions, and the polysilicon layer is doped with the first ions and the third ions through the mask. , and then remove the mask.

For another example, step 2307 may not be performed, and after forming the gate insulating material layer and before forming the conductive material layer, a mask may be formed on the gate insulating material layer, and the polysilicon layer is doped with the first ions and a third ion, after which the mask is removed.

For another example, step 2307 may not be performed, and between steps 2310 and 2311, a mask may be formed on the source-drain insulating material layer, and the polysilicon layer is doped with the first ions and the third ions through the mask, and then The mask is then removed.

To sum up, in the thin film transistor manufactured by the method provided by the embodiment of the present invention, the active layer has a source connection region and a drain connection region. In this way, a PIN junction is formed in the connection area. Moreover, the PIN junction conducts in one direction and the potential barrier increases linearly, which can effectively prevent electrons from passing through when it is turned off, basically eliminate leakage current, and improve the display effect of the display device. At the same time, the PIN junction can well control the attenuation of the on-state current, reduce damage to the thin film transistor, and improve the service life of the thin film transistor.

An embodiment of the present invention provides a thin film transistor device, and the thin film transistor device includes the thin film transistor provided by the embodiment of the present invention (the thin film transistor as shown in FIG. 6 or 12 ). The thin film transistor device may be an electronic component or chip.

An embodiment of the present invention provides a display substrate, and the display substrate includes the thin film transistor provided by the embodiment of the present invention (the thin film transistor as shown in FIG. 6 or 12 ).

An embodiment of the present invention provides a display device, and the display device includes the display substrate provided by the embodiment of the present invention.

The display device can be any product or component with a display function such as a liquid crystal panel, an electronic paper, an organic light-emitting diode panel, a light-emitting diode panel, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

It should be noted that in the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. Also it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. Further, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or one or more intervening layers or elements may be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or one or more intervening layers may also be present. or components. Like reference numerals designate like elements throughout.

In the present disclosure, the terms "first", "second", "third" and "fourth" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance. The term "plurality" means two or more, unless otherwise clearly defined.

It should be noted that, the method embodiment provided in the embodiment of the present invention can refer to the corresponding thin film transistor embodiment, which is not limited in the embodiment of the present invention. The order of the steps in the method embodiments provided by the embodiments of the present invention can be appropriately adjusted, and the steps can also be increased or decreased according to the situation. Any person familiar with the technical field can easily think of changes within the technical scope disclosed in the present invention. Methods should all be covered within the protection scope of the present invention, and thus will not be repeated here.

The above are only optional embodiments of the application, and are not intended to limit the application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the application shall be included in the protection of the application. within range.

Claims (11)

1. a kind of thin film transistor (TFT), which is characterized in that the active layer (012) of the thin film transistor (TFT) (01) includes: successively to arrange Source region (0121), channel region (0122) and drain region (0123)；

The source region (0121) includes the polysilicon doped with the first ion, the channel region (0122) include doped with second from The polysilicon of son, the drain region (0123) includes the polysilicon doped with third ion；

Wherein, first ion and the third ion are P-type ion, and second ion is N-type ion；Alternatively, First ion and the third ion are N-type ion, and second ion is P-type ion.

2. thin film transistor (TFT) according to claim 1, which is characterized in that the thin film transistor (TFT) further include: gate pattern (014)；The orthographic projection region of the gate pattern (014) on the active layer is all overlapped with the channel region (0122).

3. thin film transistor (TFT) according to claim 1 or 2, which is characterized in that the active layer further include: source bonding pad (0124) and bonding pad (0125) is leaked；

The source bonding pad (0124) is between the source region (0121) and the channel region (0122), the source bonding pad It (0124) include polysilicon, alternatively, the source bonding pad (0124) includes the polysilicon doped with the 4th ion；

The leakage bonding pad (0125) is between the channel region (0122) and the drain region (0123), the leakage bonding pad It (0125) include polysilicon, alternatively, leakage bonding pad (0125) includes the polysilicon doped with the 5th ion；

Wherein, when the source bonding pad (0124) and middle at least one company existed doped with ion of leakage bonding pad (0125) When meeting area, for each bonding pad at least one described bonding pad, the ion doping concentration of the bonding pad is less than described The ion doping concentration of reference area in active layer, the reference area is adjacent with the bonding pad, and adulterated in the reference area The ion adulterated in ion and the bonding pad is P-type ion or N-type ion.

4. a kind of manufacturing method of thin film transistor (TFT), which is characterized in that for any film of manufacturing claims 1 to 3 Transistor, which comprises

Form polysilicon layer；

Different kinds of ions is adulterated into the polysilicon layer, obtains active layer；

Wherein, the different kinds of ions includes: the first ion, the second ion and third ion；

First ion and the third ion are P-type ion, and second ion is N-type ion；Alternatively, described One ion and the third ion are N-type ion, and second ion is P-type ion；

The active layer includes: the source region successively arranged, channel region and drain region；The source region includes doped with first ion Polysilicon, the channel region includes the polysilicon doped with second ion, and the drain region includes doped with the third The polysilicon of ion.

5. according to the method described in claim 4, being had it is characterized in that, adulterating different kinds of ions into the polysilicon layer Active layer, comprising:

Second ion is adulterated into the polysilicon layer, obtains the channel region；

First ion and the third ion are adulterated into the polysilicon layer doped with second ion, obtain institute State source region and the drain region.

6. according to the method described in claim 5, it is characterized in that, adulterated into the polysilicon layer second ion it Afterwards, the method also includes: gate pattern, and the gate pattern are formed on the polysilicon layer doped with second ion Orthographic projection region on the polysilicon layer is all overlapped with the channel region；

First ion and the third ion are adulterated in the polysilicon layer to doped with second ion, are wrapped It includes: using the gate pattern as exposure mask, first ion is adulterated into the polysilicon layer doped with second ion With the third ion.

7. according to the method described in claim 5, it is characterized in that, the different kinds of ions further include: the 4th ion and the 5th from At least one of son ion, the active layer further include: the corresponding bonding pad of every kind of ion in at least one ion；Its In, for the corresponding source bonding pad of the 4th ion between the source region and the channel region, the source bonding pad includes: to mix The miscellaneous polysilicon for having the 4th ion；The corresponding leakage bonding pad of 5th ion be located at the channel region and the drain region it Between, the leakage bonding pad includes: the polysilicon doped with the 5th ion；For the source bonding pad and the leakage bonding pad In each bonding pad, the ion doping concentration of the bonding pad is less than the ion doping concentration of reference area in the active layer, The reference area is adjacent with the bonding pad, and the ion adulterated in the reference area and the ion adulterated in the bonding pad are equal For P-type ion or N-type ion；

Different kinds of ions is adulterated into the polysilicon layer, obtains active layer, further includes:

After adulterating first ion and the third ion into the polysilicon layer doped with second ion, Adulterated into the polysilicon layer doped with first ion, second ion and the third ion it is described it is at least one from Son obtains the corresponding bonding pad of every kind of ion at least one ion.

8. the method according to the description of claim 7 is characterized in that adulterated into the polysilicon layer second ion it Afterwards, the method also includes:

Conductive material layer and photoetching agent pattern, the channel region are sequentially formed on the polysilicon layer doped with second ion Positioned at the photoetching agent pattern in the orthographic projection region on the polysilicon layer, and the area of the channel region is less than the light The area in orthographic projection region of the photoresist pattern on the polysilicon layer；

The conductive material layer is exposed, developed and solidified using the photoetching agent pattern as exposure mask, obtains gate pattern, and Orthographic projection region of the gate pattern on the polysilicon layer is all overlapped with the channel region；

Remove the photoetching agent pattern；

First ion and the third ion are adulterated in the polysilicon layer to doped with second ion, are wrapped It includes: before removing the photoetching agent pattern, using the photoetching agent pattern as exposure mask, to doped with described in second ion First ion and the third ion are adulterated in polysilicon layer；

Described at least one is adulterated into the polysilicon layer doped with first ion, second ion and the third ion Kind ion, comprising:

After removing the photoetching agent pattern, using the gate pattern as exposure mask, to doped with first ion, described second At least one ion is adulterated in the polysilicon layer of ion and the third ion.

9. a kind of film transistor device, which is characterized in that the film transistor device includes any institute of claims 1 to 3 The thin film transistor (TFT) stated.

10. a kind of display base plate, which is characterized in that the display base plate includes any film crystal of claims 1 to 3 Pipe.

11. a kind of display device, which is characterized in that the display device includes display base plate described in any one of claim 10.