CN110134640B - Multi-core sensor data processing chip and operation method - Google Patents
Multi-core sensor data processing chip and operation method Download PDFInfo
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Abstract
The invention provides a multi-core sensor data processing chip and an operation method, wherein the data processing chip comprises a multi-core array area, an input module, an output module, a control module and the like, wherein the multi-core array area comprises a plurality of bus control cores, a plurality of data processing cores and a plurality of data buses; all bus control cores are connected with the data processing cores through a data bus; the bus control core dynamically adjusts the configuration of the data processing core among different data buses through the control module according to the input data information. The multi-core sensor data processing chip can dynamically layer the input sensor data, improves the flexibility and traceability of the cognitive function, and has high industrial utilization value.
Description
Technical Field
The invention belongs to the field of semiconductor memory integrated circuits, and relates to a multi-core sensor data processing chip and an operation method.
Background
Along with the development of science and technology, after a large number of sensors are accessed into a network, a very high requirement is put on sensor data processing, wherein several key problems are as follows:
1. how a large amount of data is processed in time;
2. the processing mode of the sensor data is closely related to the type, and different algorithms are needed for processing different types of data;
3. the sensor data stores very effective information, and although the data processing capacity is improved, the problems of large data volume and rich types can be solved to a certain extent, the realization of data cognition is still very difficult.
In this case, it has been difficult to meet our needs simply by developing a wide variety of data processing programs.
The human brain processes a large amount of information daily through various ways of vision, hearing, touch and the like, and the capability of reasoning, recognition, association, prediction and the like is difficult to match by a computer system, but the brain power consumption of an adult is estimated to be only about 20W, and the transmission speed of the information in the brain can only reach the millisecond level. How to obtain elicitations from the working modes of human brains, improve the operation modes of a computer system so as to achieve the aim of high-efficiency low-power consumption operation, and simultaneously process data according to the thinking mode of human beings, so that the problems of a plurality of researchers and companies to be solved are provided.
The brain science research results show that neurons in the brain of a human are connected with each other in a layered networking mode, and the cognitive process is completed through cooperation among the neurons in the layered networking mode. On one hand, the cooperative working mode enables neurons with response speed far lower than that of electronic devices to complete a large number of sensing tasks through parallel working, and many aspects are better than high-performance computers; on the other hand, by learning and hierarchical filtering, a large amount of invalid information is filtered, and valid information is kept to the end, so that the overload of the brain thinking process caused by excessive data is avoided, and meanwhile, the valid information is not submerged by a large amount of invalid information.
The neural network calculation forms a very mature and perfect theoretical system, simulates a parallel processing mechanism of the brain neural network, forms a multi-input multi-output system, and enables the system to have more and more accurate prediction capability through training of a large amount of data. This system was originally implemented in computer software, and more hardware systems utilized processor, FPGA (Field Programmable Gate Array ) etc. technologies to implement hardware acceleration of algorithms in order to increase computational efficiency. Furthermore, IBM corporation has started the Watson computer system project of artificial intelligence many years ago, and the newly developed second generation TrueNorth chip realizes a processing chip simulating one million neurons, the power consumption of which is only 70mW, and the development of the intelligent processing chip field is led, and the "cognitive computation" proposed by IBM corporation also becomes a research and development hotspot in academia and enterprise industry.
However, although the scheme solves the complex cognitive function by the homogeneous nodes, the autonomous functional differentiation process of the brain neurons is not shown, under the abstraction of the algorithm, the nodes have no functional significance, only have the logical significance of data, the formed result is that the whole system can only work in a black box mode, and when the result is not ideal, the problem of the whole cognitive process cannot be traced back. Although some means are available at present to artificially divide areas and functions, the method is improved to a certain extent, and the problem is not solved at all, which affects the application effect of the system.
Under the background, the invention provides hardware support for realizing node function differentiation in the process of processing chips to simulate the neural network to realize cognition by designing a flexible multi-layer chip topological structure.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a multi-core sensor data processing chip for improving the flexibility and traceability of the cognition of a computer system through sensor data processing in the prior art.
To achieve the above and other related objects, the present invention provides a multi-core sensor data processing chip, the chip including a multi-core array region, an input module, an output module, a control module, a chip input pin, a chip output pin, and a chip control pin, wherein:
the multi-core array area comprises M bus control cores, N data processing cores and M data buses, wherein M is an integer greater than 2, and N is an integer greater than 1; all bus control cores are connected with the data processing cores through data buses, and each data bus connects one bus control core with N data processing cores; each data processing core is connected with different bus control cores through different data buses; each bus is provided with an output end and an output end for each data processing core to connect with corresponding data processing cores;
the input module is provided with an input interface and an output interface, the input interface of the input module is connected with the input pin of the chip, and the output interface of the input module is connected with at least one of the data buses, which is called an input layer bus;
the output module is provided with an input interface and an output interface, the output interface of the output module is connected with the output pin of the chip, and the input interface of the output module is connected with at least one of the data buses, which is called an output layer bus;
the control module is connected with the data processing core, the bus control core, the input module and the output module, and generates corresponding control signals according to the output information of the data bus and outputs the corresponding control signals to the data processing core, the bus control core, the input module or the output module.
Optionally, each of the data processing cores has an output interface and an input interface, and is connected to the output and input terminals of the different data buses through an output selector and an input selector, respectively; the data processing core is selectively connected with one of the data buses through the output selector to carry out information forwarding output, or the data processing core is selectively connected with one of the data buses through the input selector to receive bus information.
Optionally, the data processing core includes bus control logic and corresponding data buffering, nonvolatile storage, and model matching logic.
Optionally, the bus control core includes an ARM controller, volatile dynamic data storage, nonvolatile code storage, data buffering, and bus control logic.
Optionally, the working modes of the bus control cores in the multi-core array area include:
sequentially polling whether the data processing cores with active output ends on the data bus have information output or not, and if so, starting an information reading time sequence to read information;
traversing all the data processing cores with active input ends on the data bus in sequence, starting a read prediction time sequence to read the prediction information of the output information of each data processing core with active input ends on the data bus, evaluating the prediction information after the prediction information is integrated, and starting a write evaluation time sequence to send the evaluation result to each data processing core with active input ends of the data bus.
Optionally, the working modes of the output interface and the input interface of the data processing core include:
when a data bus connected with an input interface of the data processing core starts an information reading time sequence, reading information from the data bus, detecting sender marks in the information, screening to obtain output information of one or more senders currently concerned by the node, comparing and matching the information with an existing change model through a learning algorithm, forming the closest model and corresponding parameters into cognitive information, temporarily storing the cognitive information in an output interface of the data processing core, simultaneously predicting future changes of the input information according to the model, and temporarily storing a prediction result in the input interface of the data processing core;
when a data bus connected with an input interface of the data processing core traverses to the data processing core and starts a read prediction time sequence, sending the prediction result to the data bus for the bus control core to read;
and when the data bus connected with the output interface of the data processing core traverses to the data processing core and starts a write evaluation time sequence, reading evaluation information from the data bus, detecting a target sender mark in the information, screening to obtain an evaluation result of the current prediction of the sender output information, and adjusting a cognitive algorithm by using the result.
Optionally, the input module acquires data from the chip input pin, converts the data into a unified information format, temporarily stores the information in an output interface of the input module, and transmits the information to the data bus when the input layer bus polls the module.
Optionally, when the output layer bus enters the information reading time sequence, the output module reads information from the data bus and forwards the information to the chip output pin.
Optionally, the functions of the control module include:
the method comprises the steps of communicating with a bus control core, obtaining comprehensive evaluation results of information output by active output ends on the data buses, dynamically determining the data processing cores distributed on the data buses according to the comprehensive evaluation results, and informing the active data processing core output ends and input ends of the bus control core;
communicating with said input selector, accessing said active input to an input interface of said data processing core, other inactive inputs being isolated from the connected data bus;
and communicating with the output selector, connecting the active output terminal to the output interface of the data processing core, and isolating other inactive output terminals from the connected data bus.
The invention also provides an operation method of the multi-core sensor data processing chip, wherein the multi-core sensor data processing chip adopts the multi-core sensor data processing chip according to any one of the above, and the operation method comprises the following steps:
the data information is input into the multi-core data processing chip through the input module;
the control module generates corresponding control signals according to the data bus output information to configure the connection relation between each data processing core and each data bus;
the data processing core adapts a data change model by adopting different matching models according to the data information on the connected data bus and outputs prediction information;
the bus control core reads the prediction information output by the data processing core on the data bus, and performs comprehensive evaluation to obtain a comprehensive evaluation result;
the bus control core informs the control module of adjusting the configuration of the data processing core among different data buses according to the comprehensive evaluation result; controlling the data processing core to perform a further matching model until an optimal matching result is obtained; and sending the matching result to an output module of the chip.
Drawings
FIG. 1 is a schematic diagram of an interconnect for a core array within a multi-core sensor data processing chip of the present invention.
FIG. 2 is a schematic diagram of an exemplary design of a data processing core according to the present invention.
FIG. 3 is a schematic diagram showing an example of the design of the bus control core of the present invention.
Fig. 4 shows a simplified example of the structure of the present invention.
Fig. 5 is a schematic diagram of the core connection logic of the present invention.
Fig. 6 shows a more flexible example structure of the present invention.
Fig. 7 is a schematic diagram of core connection logic for a first step configuration of cognitive functions according to the present invention.
Fig. 8 is a schematic diagram of the core connection logic of the second step configuration of cognitive function of the present invention.
Fig. 9 is a schematic diagram of the core connection logic of the third step configuration of the cognitive function of the present invention.
Fig. 10 is a schematic diagram of the core connection logic of the fourth step configuration of the cognitive function of the present invention.
Description of element reference numerals
1. Multi-core sensor data processing chip
2. Data processing core
3. Bus control core
4. Output module
5. Input module
6. Chip output pin
7. Chip input pin
8. Data bus
9. Data processing core output interface
10. Data processing core input interface
11. Output line connected to each data bus
12. Input lines coupled to each data bus
13. Output selector
14. Input selector
15. Control module
16. The control module is connected with control lines of other modules
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides a multi-core sensor data processing chip, please refer to FIG. 1, which is shown as an interconnection schematic diagram of the multi-core sensor data processing chip 1, comprising M bus control cores 3, N data processing cores 2, each bus control core is connected with a data bus 8, each data processing core is provided with an output interface 9, is gated through an output selector 13, and is connected with each data bus through a bus hanging wire 11; likewise, each data processing core also has an input interface 10 to which each data bus is connected by an input selector 14 gating bus bar 12.
The output module 4 has an input interface and an output interface, wherein the input interface is fixedly connected to a data bus, which is called the output layer bus; the output interface is led out through the output interface 6 of the chip and is connected with the input interfaces of other chips.
The input module 5 has an input interface and an output interface, wherein the output interface is fixedly connected to another data bus different from the input layer bus; the input interface is led out through the input interface 7 of the chip and is connected with the output interfaces of other chips.
The control module 15 connects all bus control cores 3, data processing cores 2, output modules 4 and input modules 5 within the chip via control lines 16.
In order to facilitate the description of the relative positional relationship between each core and each connection line, the bus control cores are sequentially named as B from top to bottom 1 、B 2 、……、B M The data processing cores are named as P from left to right in sequence 1 、P 2 、……、P N Wherein 1-M and 1-N are numbers.
After determining the connection topology of the data processor, the control module 15 configures the bus control core with an active input/output interface, an input selector and an output selector to realize that the data processor is connected between different data buses, obtains data from one data bus, and sends a cognitive result to another data bus to realize a hierarchical structure.
Specifically, each data processing core needs to perform model matching on data, so a simple data processing core structure is shown in fig. 2. The data processing core is provided with two sets of bus control logic and corresponding data buffering, and is used for completing bus operation, and the data buffering can be realized by adopting a volatile memory embedded SRAM; the nonvolatile memory is equipped for storing the change model, and the nonvolatile memory embedded EEPROM or embedded FLASH can be adopted; all matching processes can realize a model matching logic module by using synchronous digital logic because the logic is not complex.
Specifically, each bus control core needs to evaluate data and provide control information for the control module, and has a certain complex logic function, but has low requirement on data, so that a simple bus control core structure is shown in fig. 3, and can form a minimum computing system by using an ARM controller, an embedded SRAM volatile dynamic data storage, an embedded EEPROM or an embedded FLASH nonvolatile code storage, and realize access to a data bus through data buffering and bus control logic.
Other structures are common functional modules, and various solutions can be easily obtained by adopting the prior knowledge.
As an example, the multi-core array area includes M bus control cores 3 connected to M data buses 8, each of which is connected to N output suspension wires 11 and N input suspension wires 12, and is connected to N data processing cores 2 through an output selector 13 and an input selector 14, respectively.
In addition, the bus connected with the bus control core B1 is an output layer bus and is fixedly connected to the output module 4, and the bus control core B M Connected totalThe lines are input layer buses, fixedly connected to the input module 5. Other data buses may be referred to as hidden layer buses.
To illustrate this process, a simplified practical example is given, the structure of which is shown in fig. 4. In this figure, the number of bus control cores 3 is selected to be the minimum value 3, numbered B 1 、B 2 、B 3 The number of the data processing cores 2 is selected to be 3, and the number is P 1 、P 2 、P 3 . After configuration by the control module 15, the selection of the input selector and the output selector is shown by arrows in the figure, while the non-selected hanging lines in the figure are not shown for the sake of visualization. The selected hanging wire is the hanging wire of the active interface on the data bus.
In this connection configuration, the logical connection relationship is as shown in fig. 5. We can see that in this configuration the data processor node constitutes a two-layer structure, where P1 and P2 connect the input layer bus and the hidden layer bus and P3 connects the hidden layer bus and the output layer bus.
Under the connection relation, one application method is as follows: p1 and P2 acquire data from the input layer bus respectively, process the data according to two different modes, for example, P1 realizes the frequency change rule after the data is converted into the frequency domain, P2 realizes the average value change rule of the data, each data processing core adapts the data change model according to the two different modes and gives prediction, P1 predicts the possible value of the next data according to the change condition of the average value, and the matched average value change model and corresponding parameters are used as output to be sent to the data bus B2; similarly, P2 matches the data change model according to the frequency domain change model, makes predictions, and sends the model and parameters to data bus B2 as well. And P3 acquires the matching results from the B2 bus, finds the change rule of the models and parameters again as input, further matches the models, and outputs the matching results from the output port. Through the process, the data is subjected to hierarchical analysis and model matching, and each time the data is subjected to matching, the data quantity is greatly reduced due to the fact that the change rule model is output, and more complex and higher-level rule matching can be performed. The more the number of layers, the more complex the matched model can be, the more realistic the obtained cognitive result is, and the data volume is greatly reduced.
However, the connection relation can be easily reconfigured and modified by the control module, and the dynamic modification of the connection relation can be more flexible for configuring resources.
A relatively complex implementation may be shown in the chip of fig. 6. The number of bus control cores and the number of data processing cores are increased to 4, and the configuration is similar to that described above, so that the input layer bus is B4, the output layer bus is B1, and the hidden layer bus is two of B2 and B3.
When data is input into the chip initially, the chip does not know the change rule of sensor data, the control module configures the connection relationship, configures all data processing cores between the input layer bus B4 and the hidden layer B3, automatically changes the functions into different functions and performs model matching on the data, and at the moment, the connection relationship diagram is shown in fig. 7.
After a period of matching adjustment, the bus control core B3 finds that P2 and P4 can perform better model matching on the data, but the cognitive result still changes, so that the control module is informed to detach P1 and P3 from between the two data buses and configure between the output layer bus B1 and the hidden layer B3, as shown in fig. 8. And P1 and P3 are functionally differentiated, and model matching is carried out on the cognitive result change rule matched with P2 and P4 in different modes.
After a period of matching adjustment, the bus control core B1 finds P1 to complete the model matching of the layer, and informs the control module to dismount P3 as a standby resource to be idle. As shown in fig. 9.
The actual situation changes, the change rule of the data changes, new factors are added, at the moment, the B1 bus control core discovers that the final cognition result is inaccurate, the control module is informed to configure P3 between the hidden layer bus B2 and the output layer bus B1, and the output of P1 is connected to the hidden layer bus B2, one layer of processing is added due to the change, a more complex data change model can be supported, and the optimal cognition result is obtained through matching adjustment for a period of time as shown in fig. 10.
In this embodiment, the connection structure of the chip multi-core array can be dynamically adjusted to autonomously realize the functional differentiation of the data processing core; when the model matching result changes, the whole model matching process can be traced, and the matching model and parameters can be adjusted, so that the flexibility of the chip for completing the cognitive function on the changed data is further improved. The multi-core sensor data processing chip can dynamically layer the input sensor data, and improves the flexibility and traceability of the cognitive function. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. The utility model provides a many core sensor data processing chip which characterized in that, the chip includes many core array district, input module, output module, control module and chip input pin, chip output pin and chip control pin, wherein:
the multi-core array area comprises M bus control cores, N data processing cores and M data buses, wherein M is an integer greater than 2, and N is an integer greater than 1; all bus control cores are connected with the data processing cores through data buses, and each data bus connects one bus control core with N data processing cores; each data processing core is connected with different bus control cores through different data buses; each bus is provided with an output end and an input end for each data processing core to connect with corresponding data processing cores; each data processing core is provided with an output interface and an input interface, and is respectively connected with different data buses through an output selector and an input selector to carry out information forwarding output, or the data processing core is selectively connected with one data bus through the input selector to receive bus information, the input module is provided with an input interface and an output interface, the input interface of the input module is connected with an input pin of the chip, and the output interface of the input module is connected with at least one data bus and is called an input layer bus;
the output module is provided with an input interface and an output interface, the output interface of the output module is connected with the output pin of the chip, and the input interface of the output module is connected with at least one of the data buses, which is called an output layer bus;
the control module is connected with the data processing core, the bus control core, the input module and the output module, and generates corresponding control signals according to the output information of the data bus and outputs the corresponding control signals to the data processing core, the bus control core, the input module or the output module; after the control module determines the connection topology of the chip, the control module configures an active input/output interface, an active input selector and an active output selector for the bus control core to realize the connection of the chip among different data buses, obtains data from one data bus and sends a cognitive result to the other data bus.
2. The multi-core sensor data processing chip of claim 1, wherein: the data processing core includes bus control logic and corresponding data buffering, nonvolatile storage, and model matching logic.
3. The multi-core sensor data processing chip of claim 1, wherein: the bus control core comprises an ARM controller, volatile dynamic data storage, nonvolatile code storage, data buffering and bus control logic.
4. The multi-core sensor data processing chip of claim 1, wherein: the working modes of the bus control cores in the multi-core array area comprise:
sequentially polling whether the data processing cores with active output ends on the data bus have information output or not, and if so, starting an information reading time sequence to read information;
traversing all the data processing cores with active input ends on the data bus in sequence, starting a read prediction time sequence to read the prediction information of the output information of each data processing core with active input ends on the data bus, evaluating the prediction information after the prediction information is integrated, and starting a write evaluation time sequence to send the evaluation result to each data processing core with active input ends of the data bus.
5. The multi-core sensor data processing chip of claim 1, wherein: the working modes of the output interface and the input interface of the data processing core comprise:
when a data bus connected with an input interface of the data processing core starts an information reading time sequence, reading information from the data bus, screening sender marks in detected information, obtaining output information of one or more senders currently concerned by a node, comparing and matching the information with an existing change model through a learning algorithm, forming the closest model and corresponding parameters into cognitive information, temporarily storing the cognitive information in an output interface of the data processing core, simultaneously predicting future changes of the input information according to the model, and temporarily storing a prediction result in the input interface of the data processing core;
when a data bus connected with an input interface of the data processing core traverses to the data processing core and starts a read prediction time sequence, sending the prediction result to the data bus for the bus control core to read;
and when the data bus connected with the output interface of the data processing core traverses to the data processing core and starts a write evaluation time sequence, reading evaluation information from the data bus, detecting a target sender mark in the information, screening to obtain an evaluation result of the current prediction of the sender output information, and adjusting a cognitive algorithm by using the result.
6. The multi-core sensor data processing chip of claim 1, wherein: the input module acquires data from the chip input pin, converts the data into a unified information format, temporarily stores the information in an output interface of the input module, and transmits the information to the data bus when the input layer bus polls the module.
7. The multi-core sensor data processing chip of claim 1, wherein: and when the output layer bus enters the information reading time sequence, the output module reads information from the data bus and forwards the information to the chip output pin.
8. The multi-core sensor data processing chip of claim 1, wherein: the functions of the control module include:
the method comprises the steps of communicating with a bus control core, obtaining comprehensive evaluation results of information output by active output ends on the data buses, dynamically determining the data processing cores distributed on the data buses according to the comprehensive evaluation results, and informing the active data processing core output ends and input ends of the bus control core;
communicating with said input selector, accessing said active input to an input interface of said data processing core, other inactive inputs being isolated from the connected data bus;
and communicating with the output selector, connecting the active output terminal to the output interface of the data processing core, and isolating other inactive output terminals from the connected data bus.
9. A method of operating a multi-core sensor data processing chip employing the multi-core sensor data processing chip of any one of claims 1-8, characterized by: the operation method comprises the following steps:
the data information is input into the multi-core sensor data processing chip through the input module;
the control module generates corresponding control signals according to the data bus output information to configure the connection relation between each data processing core and each data bus;
the data processing core adapts a data change model by adopting different matching models according to the data information on the connected data bus and outputs prediction information;
the bus control core reads the prediction information output by the data processing core on the data bus, and performs comprehensive evaluation to obtain a comprehensive evaluation result;
the bus control core informs the control module of adjusting the configuration of the data processing core among different data buses according to the comprehensive evaluation result; controlling the data processing core to perform a further matching model until an optimal matching result is obtained; and sending the matching result to an output module of the chip.
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