CN110120242B - Memory test method and device, computer equipment and storage medium - Google Patents
Memory test method and device, computer equipment and storage medium Download PDFInfo
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- CN110120242B CN110120242B CN201910366150.7A CN201910366150A CN110120242B CN 110120242 B CN110120242 B CN 110120242B CN 201910366150 A CN201910366150 A CN 201910366150A CN 110120242 B CN110120242 B CN 110120242B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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Abstract
The application relates to a memory testing method, a memory testing device, computer equipment and a storage medium. The method comprises the following steps: firstly, acquiring a test signal; firstly, carrying out a first built-in self-test on an area without data to obtain a test result of the first built-in self-test; when the first built-in self-test passes, transferring data in the area with the data to the area without the data, writing a second test signal into the test control module, testing the area with the data, and acquiring the test result of the memory according to the test result. According to the memory testing method, the built-in self-testing test of the chip is controlled through the test control module, and meanwhile, the areas with data and the areas without data are respectively tested, so that the built-in self-testing test of the internal memory is optimized, and the testing time of the built-in self-testing test is shortened.
Description
Technical Field
The present application relates to the field of chip testing technologies, and in particular, to a memory testing method and apparatus, a computer device, and a storage medium.
Background
With the rapid development of the integrated circuit industry, the logic scale of the chip is rapidly increased, and the demand of the RAM (Random Access Memory) of the chip is increased. The ram is mainly used for loading various programs and data for direct operation and application of the chip. The proportion of the chip RAM in the chip design is increasing, so the RAM yield and reliability are becoming more and more important. However, since the RAM is inside the chip, few chip RAMs can be directly connected through chip pins, which increases the test difficulty of the RAM inside the chip; and as the technology of the integrated circuit industry is improved and the feature size is reduced, the RAM on the chip is more and more dense, and the failure types are more and more. This greatly increases the cost of testing and the reliability risk that makes it difficult for the original testing method to deal with these new challenges.
In recent years, MBIST (Memory built-In Self Test) is a circuit widely used for testing a Memory, and is widely used In integrated circuit design due to the characteristics that the MBIST occupies a small area, is low In Test development cost, and determines whether the RAM is defective by reading and writing the RAM by using a failure algorithm. However, the testing time of the RAM of the traditional MBIST is long, and the testing efficiency is low.
Disclosure of Invention
Therefore, it is necessary to provide a memory testing method, device, computer device, and storage medium capable of efficiently testing a memory, in order to solve the problems of long testing time and low testing efficiency of the conventional MBIST.
The memory test method is characterized by being applied to a memory test system, wherein the memory test system comprises a test control module and a memory built-in self-test circuit which are connected with each other, and the memory built-in self-test circuit is connected with a memory to be tested;
the memory test method comprises the following steps:
acquiring a first test signal and a second test signal, wherein the first test signal is used for carrying out memory built-in self-test on an area which does not store data in a memory to be tested, and the second test signal is used for carrying out memory built-in self-test on an area which stores data in the memory to be tested;
inputting a first test signal to a built-in self-test circuit of a memory through the test control module, and carrying out a first built-in self-test on the area without data to obtain a test result of the first built-in self-test;
when the first built-in self test passes, transferring the data in the area with the data to the area without the data;
and inputting a second test signal to the memory built-in self-test circuit through the test control module, carrying out a second built-in self-test on the area with the data, and acquiring a test result of the memory according to the result of the second built-in self-test.
In one embodiment, the inputting a first test signal to a memory built-in self-test circuit through the test control module, performing a first built-in self-test on the area where no data exists, and after obtaining a test result of the first built-in self-test, further includes:
and when the first built-in self-test fails, judging that the memory to be tested is unqualified.
In one embodiment, the memory built-in self-test circuit includes a test vector generation circuit, a built-in self-test control circuit, and a response analyzer, and the inputting a first test signal to the memory built-in self-test circuit through the test control module includes:
inputting the first test signal to a test vector generating circuit, and controlling the test vector generating circuit to generate a corresponding test vector;
sending the test vector to the built-in self-test control circuit, and inputting the test vector to the area without data through the built-in self-test control circuit;
and obtaining the test response of the area without data to the test vector through the response analyzer, and obtaining the test result of the first built-in self-test according to the test response.
In one embodiment, the obtaining, by the response analyzer, a test response of the area where no data exists to the test vector, and the obtaining, according to the test, a test result of the first built-in self test correspondingly includes:
obtaining the test response of the area without data to the test vector through the response analyzer;
and comparing the normal response of the pre-stored normal memory to the test vector with the test response, judging that the first built-in self-test passes when the normal response is the same as the test response, and judging that the test does not pass when the normal response is not the same as the test response.
In one embodiment, the comparing the normal response of the pre-stored normal memory to the test vector with the test response, determining that the area without data exists is qualified when the normal response is the same as the test response, and determining that the area without data exists is not qualified when the normal response is not the same as the test response, further includes:
and acquiring address information of an abnormal area of the memory according to the difference between the normal response and the test response, and generating a memory test report corresponding to the address information of the abnormal area of the memory.
In one embodiment, the migrating the data in the area with data to the area without data when the first built-in self test passes includes:
when the first built-in self test passes, reading data in an area where data are stored according to a processor pointer, writing the data into the area where the data are not stored, and jumping the processor pointer to a storage address of the area where the data are not stored.
A memory test apparatus applied to a memory test system including the memory test apparatus, a test control module, and a memory built-in self test circuit, the apparatus comprising:
the signal acquisition module is used for acquiring a first test signal and a second test signal, wherein the first test signal is used for carrying out memory built-in self-test on an area which does not store data in the memory to be tested, and the second test signal is used for carrying out memory built-in self-test on the area which stores data in the memory to be tested;
the first test control module is used for inputting a first test signal to the memory built-in self-test circuit through the test control module, carrying out a first built-in self-test on the region without data and obtaining a test result of the first built-in self-test;
the data migration module is used for migrating the data in the area with the stored data to the area without the stored data when the first built-in self test passes;
and the second test control module is used for inputting a second test signal to the memory built-in self-test circuit through the test control module, carrying out a second built-in self-test on the area with the data, and acquiring the test result of the memory according to the result of the second built-in self-test.
In one embodiment, the memory test device further comprises a fault interruption determination module, wherein the fault interruption determination module is used for determining that the memory to be tested is unqualified when the first built-in self-test fails.
A computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
acquiring a first test signal and a second test signal, wherein the first test signal is used for carrying out memory built-in self-test on an area which does not store data in a memory to be tested, and the second test signal is used for carrying out memory built-in self-test on an area which stores data in the memory to be tested;
inputting a first test signal to a built-in self-test circuit of a memory through the test control module, and carrying out a first built-in self-test on the area without data to obtain a test result of the first built-in self-test;
when the first built-in self test passes, transferring the data in the area with the data to the area without the data;
and inputting a second test signal to the memory built-in self-test circuit through the test control module, carrying out a second built-in self-test on the area with the data, and acquiring a test result of the memory according to the result of the second built-in self-test.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
acquiring a first test signal and a second test signal, wherein the first test signal is used for carrying out memory built-in self-test on an area which does not store data in a memory to be tested, and the second test signal is used for carrying out memory built-in self-test on an area which stores data in the memory to be tested;
inputting a first test signal to a built-in self-test circuit of a memory through the test control module, and carrying out a first built-in self-test on the area without data to obtain a test result of the first built-in self-test;
when the first built-in self test passes, transferring the data in the area with the data to the area without the data;
and inputting a second test signal to the memory built-in self-test circuit through the test control module, carrying out a second built-in self-test on the area with the data, and acquiring a test result of the memory according to the result of the second built-in self-test.
According to the memory testing method, the device, the computer equipment and the storage medium, the built-in self-testing test of the chip is controlled through the test control module, and meanwhile, the area with data and the area without data are respectively tested, so that the built-in self-testing test of the internal memory is optimized, and the testing time of the built-in self-testing test is shortened.
Drawings
FIG. 1 is a diagram of an exemplary embodiment of a memory test method;
FIG. 2 is a flow chart illustrating a method for testing a memory according to one embodiment;
FIG. 3 is a flow chart illustrating a method for testing a memory device according to another embodiment;
FIG. 4 is a schematic sub-flow chart of step S400 of FIG. 2 in one embodiment;
FIG. 5 is a schematic sub-flow chart of step S400 of FIG. 2 in another embodiment;
FIG. 6 is a block diagram of a memory test device in one embodiment;
FIG. 7 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The memory test method provided by the present application can be applied to a memory test system of a chip 100 shown in fig. 1, and is implemented by a processor 120, and is used for testing a RAM of the chip, where the memory test system includes the processor 120, a test control module 140, and a memory built-in self test circuit 160. The processor 120 acquires a first test signal and a second test signal for performing a memory built-in self test on the memory to be tested; the processor 120 writes the first test signal into the test control module 140, and the test control module 140 is configured to input a control signal to the memory built-in self-test circuit 160 and control the memory built-in self-test circuit to perform a memory test on the memory 180; first, the processor 120 inputs a first test signal to the memory built-in self-test circuit 160 through the test control module 140, and performs a first built-in self-test on the region 181 which does not store data to obtain a test result of the first built-in self-test; when the first built-in self test passes, the processor 120 migrates the program in the area 183 in which the data is stored to the area 181 in which the data is not stored, writes the second test signal into the test control module 140, inputs the second test signal to the memory built-in self test circuit 160 through the test control module 140, performs the second built-in self test on the area 183 in which the data is stored, and obtains the test result of the memory 180 according to the result of the second built-in self test.
As shown in fig. 2, in one embodiment, the memory test method of the present application is implemented by a processor, and specifically includes the following steps:
s200, a first test signal and a second test signal are obtained, the first test signal is used for carrying out memory built-in self-test on the area of the memory to be tested, which does not store data, and the second test signal is used for carrying out memory built-in self-test on the area of the memory to be tested, which stores data.
The Memory to be tested is a random access Memory contained In a chip, and the built-In Self-Test of the Memory is a Memory Build-In Self Test technology, referred to as an MBIST for short, which is one of BIST technologies. BIST is a technique for implanting functional circuits in a circuit at design time to provide self-test functionality, thereby reducing the dependency of device testing on Automatic Test Equipment (ATE). BIST is a dft (design for testability) technology that can be applied to almost all circuits and is therefore widely used in the semiconductor industry. The first test signal and the second test signal are respectively used for testing an area in which data are stored and an area in which data are not stored. The first Test signal and the second Test signal may be IJTAG (Internal, Joint Test Action Group) signals. The first test signal is generated based on different test algorithms and is used for being input into the test vector generation circuit to generate a plurality of test vectors for testing the memory. The processor is connected with the pins of the chip, and the processor can acquire a first test signal and a second test signal input from the outside through the pins of the chip. Firstly, a memory test processor in a chip can acquire a first test signal and a second test signal input from the outside through pins of the chip.
S400, inputting a first test signal to the memory built-in self-test circuit through the test control module, and performing a first built-in self-test on the area without data to obtain a test result of the first built-in self-test.
The Test control module is used for controlling a memory built-in self-Test circuit in the chip to perform built-in self-Test, and the Test control module can be connected with the memory built-in self-Test circuit through a Test Access Port (TAP) of the memory built-in self-Test circuit to Test the memory built-in self-Test circuit. The main function of the test control module is to restore the data communicated on the original interface by the read-write mode of the controller. The memory built-in self-test circuit is a circuit used for carrying out built-in self-test on the memory of a chip in the chip.
The processor may write a first test signal for testing an area where no data exists to the test control module after receiving the test signal from the outside of the chip. And then, after the first test signal is input into the test control module, the first test signal can be restored through the test control module and input into the memory built-in self-test circuit, and after the memory built-in self-test circuit obtains the first test signal input by the test control module, the memory built-in self-test circuit carries out built-in self-test on the area without data in the memory according to the first test signal and obtains a response test result.
S600, when the first built-in self test passes, transferring the data in the area with the data to the area without the data.
The memory of the specific chip may include data such as a program, and when a first built-in self test for testing an area where no data is stored passes, that is, when it is determined that the area where no data is stored is a good product that can be read and written normally, the processor may read the data in the area where data is stored and write the data in the area where no data is stored in the memory to be tested, that is, migrate the data in the area where data is stored to the area where no data is stored.
And S800, inputting a second test signal to the memory built-in self-test circuit through the test control module, carrying out a second built-in self-test on the area with the data, and acquiring a test result of the memory according to the result of the second built-in self-test.
And then, carrying out a second built-in self-test on the area which is provided with the data and is subjected to the migration program, and acquiring a built-in self-test result of the whole chip memory according to a test result of the second built-in self-test. Since the code inside the memory cannot be overwritten during the built-in self test, it is necessary to prevent data from being overwritten during the test by migrating the data in the area where the data is stored by the processor. When the first built-in test passes and the second built-in self test also passes, the current memory to be tested can be judged to pass the test, and when the first built-in test passes but the second built-in self test does not pass, the current memory to be tested is judged to have problems and fail the test.
According to the memory testing method, the device, the computer equipment and the storage medium, the built-in self-testing test of the chip is controlled through the test control module, and meanwhile, the area with data and the area without data are respectively tested, so that the built-in self-testing test of the internal memory is optimized, and the testing time of the built-in self-testing test is shortened.
As shown in fig. 3, in one embodiment, after S400, the method further includes:
s500, when the first built-in self test fails, the memory to be tested is judged to be unqualified.
When the first built-in self test of the area without data does not pass, the current memory to be tested can not be read and written, the memory to be tested is judged to be unqualified, the test process of the memory is ended, when the first built-in self test does not pass, the current memory can be judged to have certain problems, the test can be directly ended, the current memory to be tested is judged to be unqualified, whether the memory to be tested is qualified or not in the first built-in self test process is judged, the second test of the memory to be tested which fails in the first test is avoided, the whole test process can be effectively shortened, and the test efficiency is improved.
As shown in fig. 4, in one embodiment, the memory built-in self-test circuit includes a test vector generation circuit, a built-in self-test control circuit, and a response analyzer, and S400 includes:
s410, inputting a first test signal to the test vector generating circuit, and controlling the test vector generating circuit to generate a corresponding test vector;
s430, sending the test vector to the built-in self-test control circuit, and inputting the test vector to an area without data through the built-in self-test control circuit;
s450, a test response of the area without the data to the test vector is obtained through the response analyzer, and a test result of the first built-in self-test is obtained according to the test response.
The test vector refers to data used for carrying out specified mode test on the memory, and is generated based on the first test signal input simulated by the test control module. The test vector generating circuit can generate various test vectors for testing the memory based on the first test signal, test various memory failure types and obtain more accurate test effect. The built-in self test control circuit can be usually realized by a state machine to control the read-write operation of the memory, the response analyzer can be realized by a comparator or an MISR (Multi-Input Signature Register) circuit, and the response analyzer compares the actual memory model response with the known normal memory response and detects the device error. Built-in self-test testing of the memory may be achieved by individual devices in the built-in self-test circuit. Similarly, the second built-in self test may also be performed by the same procedure.
As shown in fig. 5, in one embodiment, S450 includes:
s452, acquiring a test response of the area without data to the test vector through a response analyzer;
s454, comparing the normal response and the test response of the pre-stored normal memory to the test vector, when the normal response is the same as the test response, determining that the first built-in self-test passes, and when the normal response is not the same as the test response, determining that the test does not pass.
The processor can acquire the actual response of the memory to be tested to the test vector through the response analysis module, and compare the pre-stored response to analyze and acquire the actual test result of the memory to be tested. When the two responses are consistent, namely the response of the memory to be tested in the test process is the same as the response of the normal memory to the test vector, the memory to be tested can be judged to have no problem, the test is passed, and when the responses are different, the memory to be tested is judged to have the problem, and the test is not passed. In one embodiment, the response analysis module includes an exclusive-or comparator, and the exclusive-or comparator performs an exclusive-or operation on the test response data of the memory and the pre-stored ideal response, thereby determining whether the actual response is correct. Whether the current memory to be tested has a failure problem or not can be effectively confirmed through comparison.
In one embodiment, S450 is followed by:
and acquiring the address information of the abnormal area of the memory according to the difference between the normal response and the test response, and generating a memory test report corresponding to the address information of the abnormal area of the memory.
When the response of the memory to be tested to the test vector is different from the response of the normal memory, the response analysis module can also analyze according to the difference of the two responses, and according to the different responses, the specific address space of the failure part in the memory to be tested is positioned to generate a corresponding memory test report. The tester can clearly know the problems of the memory through the memory test report, and the test efficiency is improved.
In one embodiment, S600 includes:
when the first built-in self test passes, reading data in the area where the data are stored according to the processor pointer, writing the data into the area where the data are not stored, and jumping the processor pointer to the storage address of the area where the data are not stored.
And when the processor migrates the data in the area in which the data is stored into the area in which the data is not stored, the pointer of the processor is simultaneously jumped to the corresponding position after the area in which the data is not stored is moved, so that the memory originally storing the program can also carry out the built-in self-test of the memory.
In one embodiment, the memory test method is applied to a memory test system, the memory test system comprises a test control module and a memory built-in self-test circuit, the memory built-in self-test circuit is connected with a memory to be tested, and the memory built-in self-test circuit comprises a test vector generation circuit, a built-in self-test control circuit and a response analyzer. The method comprises the following steps: and acquiring a first test signal and a second test signal, wherein the first test signal is used for carrying out memory built-in self-test on the area which does not store data in the memory to be tested, and the second test signal is used for carrying out memory built-in self-test on the area which stores data in the memory to be tested. Inputting a first test signal to a test vector generating circuit, and controlling the test vector generating circuit to generate a corresponding test vector; sending a test vector to the built-in self-test control circuit, and inputting the test vector to an area without data through the built-in self-test control circuit; and obtaining the test response of the area without data to the test vector through a response analyzer, and obtaining the test result of the first built-in self-test according to the test response. And simultaneously, according to the difference between the normal response and the test response, acquiring the address information of the abnormal area of the memory, and generating a memory test report corresponding to the address information of the abnormal area of the memory. And when the first built-in self test fails, judging that the memory to be tested is unqualified. When the first built-in self test passes, reading data in the area where the data are stored according to the processor pointer, writing the data into the area where the data are not stored, and jumping the processor pointer to the storage address of the area where the data are not stored. Writing a second test signal into the test control module, inputting the second test signal into the test vector generating circuit, and controlling the test vector generating circuit to generate a corresponding test vector; sending a test vector to the built-in self-test control circuit, and inputting the test vector to an area without data through the built-in self-test control circuit; obtaining the test response of the area without data to the test vector through a response analyzer; and comparing the normal response and the test response of the pre-stored normal memory to the test vector, judging that the second built-in self-test passes when the normal response and the test response are the same, and judging that the second built-in self-test does not pass when the normal response and the test response are not the same. And acquiring the test result of the memory according to the result of the second built-in self test.
It should be understood that although the various steps in the flow charts of fig. 2-5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-5 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
As shown in fig. 6, the present application also provides a memory test apparatus, including:
the signal acquiring module 200 is configured to acquire a first test signal and a second test signal, where the first test signal is used to perform a memory built-in self-test on a region where data is not stored in the memory to be tested, and the second test signal is used to perform a memory built-in self-test on a region where data is stored in the memory to be tested;
the first test control module 400 is configured to input a first test signal to the memory built-in self-test circuit through the test control module, perform a first built-in self-test on a region where data is not stored, and obtain a test result of the first built-in self-test;
a data migration module 600, configured to migrate data in an area where data is stored to an area where data is not stored when the first built-in self test passes;
the second test control module 800 is configured to input a second test signal to the memory built-in self test circuit through the test control module, perform a second built-in self test on the area where the data is stored, and obtain a test result of the memory according to a result of the second built-in self test.
In one embodiment, the device further comprises a fault interruption determination module, and the fault interruption determination module is used for determining that the memory to be tested is unqualified when the first built-in self-test fails.
In one embodiment, the memory built-in self-test circuit includes a test vector generation circuit, a built-in self-test control circuit, and a response analyzer, and the first test control module 400 is specifically configured to: inputting a first test signal to a test vector generating circuit, and controlling the test vector generating circuit to generate a corresponding test vector; sending a test vector to the built-in self-test control circuit, and inputting the test vector to an area without data through the built-in self-test control circuit; and obtaining the test response of the area without data to the test vector through a response analyzer, and obtaining the test result of the first built-in self-test according to the test response.
In one embodiment, the first test control module 400 is further configured to: obtaining the test response of the area without data to the test vector through a response analyzer; and comparing the normal response and the test response of the pre-stored normal memory to the test vector, judging that the first built-in self-test passes when the normal response is the same as the test response, and judging that the test does not pass when the normal response is not the same as the test response.
In one embodiment, the first test control module 400 is further configured to: and acquiring the address information of the abnormal area of the memory according to the difference between the normal response and the test response, and generating a memory test report corresponding to the address information of the abnormal area of the memory.
In one embodiment, the data migration module is configured to: when the first built-in self test passes, reading data in the area where the data are stored according to the processor pointer, writing the data into the area where the data are not stored, and jumping the processor pointer to the storage address of the area where the data are not stored.
For the specific definition of the memory test device, reference may be made to the definition of the memory test method above, and details are not repeated here. The various modules in the memory test device described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 7. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a memory testing method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:
acquiring a first test signal and a second test signal, wherein the first test signal is used for carrying out memory built-in self-test on an area which does not store data in a memory to be tested, and the second test signal is used for carrying out memory built-in self-test on an area which stores data in the memory to be tested;
inputting a first test signal to the built-in self-test circuit of the memory through the test control module, and carrying out a first built-in self-test on the area without data to obtain a test result of the first built-in self-test;
when the first built-in self test passes, transferring the data in the area with the data to the area without the data;
and inputting a second test signal to the built-in self-test circuit of the memory through the test control module, carrying out a second built-in self-test on the area in which the data is stored, and acquiring a test result of the memory according to the result of the second built-in self-test.
In one embodiment, the processor, when executing the computer program, further performs the steps of: and when the first built-in self test fails, judging that the memory to be tested is unqualified.
In one embodiment, the processor, when executing the computer program, further performs the steps of: inputting a first test signal to a test vector generating circuit, and controlling the test vector generating circuit to generate a corresponding test vector; sending a test vector to the built-in self-test control circuit, and inputting the test vector to an area without data through the built-in self-test control circuit; and obtaining the test response of the area without data to the test vector through a response analyzer, and obtaining the test result of the first built-in self-test according to the test response.
In one embodiment, the processor, when executing the computer program, further performs the steps of: obtaining the test response of the area without data to the test vector through a response analyzer; and comparing the normal response and the test response of the pre-stored normal memory to the test vector, judging that the first built-in self-test passes when the normal response is the same as the test response, and judging that the test does not pass when the normal response is not the same as the test response.
In one embodiment, the processor, when executing the computer program, further performs the steps of: and acquiring the address information of the abnormal area of the memory according to the difference between the normal response and the test response, and generating a memory test report corresponding to the address information of the abnormal area of the memory.
In one embodiment, the processor, when executing the computer program, further performs the steps of: when the first built-in self test passes, reading data in the area where the data are stored according to the processor pointer, writing the data into the area where the data are not stored, and jumping the processor pointer to the storage address of the area where the data are not stored.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
acquiring a first test signal and a second test signal, wherein the first test signal is used for carrying out memory built-in self-test on an area which does not store data in a memory to be tested, and the second test signal is used for carrying out memory built-in self-test on an area which stores data in the memory to be tested;
inputting a first test signal to the built-in self-test circuit of the memory through the test control module, and carrying out a first built-in self-test on the area without data to obtain a test result of the first built-in self-test;
when the first built-in self test passes, transferring the data in the area with the data to the area without the data;
and inputting a second test signal to the built-in self-test circuit of the memory through the test control module, carrying out a second built-in self-test on the area in which the data is stored, and acquiring a test result of the memory according to the result of the second built-in self-test.
In one embodiment, the computer program when executed by the processor further performs the steps of: and when the first built-in self test fails, judging that the memory to be tested is unqualified.
In one embodiment, the computer program when executed by the processor further performs the steps of: inputting a first test signal to a test vector generating circuit, and controlling the test vector generating circuit to generate a corresponding test vector; sending a test vector to the built-in self-test control circuit, and inputting the test vector to an area without data through the built-in self-test control circuit; and obtaining the test response of the area without data to the test vector through a response analyzer, and obtaining the test result of the first built-in self-test according to the test response.
In one embodiment, the computer program when executed by the processor further performs the steps of: obtaining the test response of the area without data to the test vector through a response analyzer; and comparing the normal response and the test response of the pre-stored normal memory to the test vector, judging that the first built-in self-test passes when the normal response is the same as the test response, and judging that the test does not pass when the normal response is not the same as the test response.
In one embodiment, the computer program when executed by the processor further performs the steps of: and acquiring the address information of the abnormal area of the memory according to the difference between the normal response and the test response, and generating a memory test report corresponding to the address information of the abnormal area of the memory.
In one embodiment, the computer program when executed by the processor further performs the steps of: when the first built-in self test passes, reading data in the area where the data are stored according to the processor pointer, writing the data into the area where the data are not stored, and jumping the processor pointer to the storage address of the area where the data are not stored.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A memory test method is characterized in that the memory test method is applied to a memory test system and used for testing an RAM (random access memory), the memory test system comprises a test control module and a memory built-in self-test circuit which are connected with each other, the memory built-in self-test circuit is connected with a memory to be tested, the test control module is connected with the memory built-in self-test circuit through a test access port, and the memory built-in self-test circuit comprises a test vector generation circuit, a built-in self-test control circuit and a response analyzer;
the memory test method comprises the following steps:
acquiring a first test signal and a second test signal, wherein the first test signal is used for carrying out memory built-in self-test on an area which does not store data in a memory to be tested, and the second test signal is used for carrying out memory built-in self-test on an area which stores data in the memory to be tested;
inputting a first test signal to a built-in self-test circuit of a memory through the test control module, and carrying out a first built-in self-test on the area without data to obtain a test result of the first built-in self-test;
when the first built-in self test passes, transferring the data in the area with the data to the area without the data;
inputting a second test signal to a built-in self-test circuit of the memory through the test control module, carrying out a second built-in self-test on the area with the data, and acquiring a test result of the memory to be tested according to the result of the second built-in self-test;
the step of inputting a first test signal to a memory built-in self-test circuit through the test control module, and the step of performing a first built-in self-test on the area without data includes:
restoring the first test signal in a read-write mode through the test control module, inputting the first test signal to a test vector generating circuit, and controlling the test vector generating circuit to generate a corresponding test vector, wherein the test vector generating circuit is used for generating a test vector for testing the memory to be tested according to the first test signal, and the test vector is used for testing the failure type of the memory;
sending the test vector to the built-in self-test control circuit, and inputting the test vector to the area without data through the built-in self-test control circuit;
and obtaining the test response of the area without data to the test vector through the response analyzer, and obtaining the test result of the first built-in self-test according to the test response.
2. The method of claim 1, wherein the inputting a first test signal to the memory built-in self test circuit through the test control module, performing a first built-in self test on the area without data stored therein, and after obtaining a test result of the first built-in self test, further comprises:
and when the first built-in self-test fails, judging that the memory to be tested is unqualified.
3. The method of claim 1, wherein the response analyzer comprises a comparator and a MISR circuit.
4. The method of claim 1, wherein obtaining, by the response analyzer, test responses of the areas without stored data to the test vectors, and obtaining test results of the first built-in self test according to the test responses comprises:
obtaining the test response of the area without data to the test vector through the response analyzer;
and comparing the normal response of the pre-stored normal memory to the test vector with the test response, judging that the first built-in self-test passes when the normal response is the same as the test response, and judging that the test does not pass when the normal response is not the same as the test response.
5. The method of claim 4, wherein comparing the normal response of the pre-stored normal memory to the test vector with the test response, determining that the area without data is qualified when the normal response is the same as the test response, and determining that the area without data is unqualified when the normal response is not the same as the test response, further comprises:
and acquiring address information of an abnormal area of the memory according to the difference between the normal response and the test response, and generating a memory test report corresponding to the address information of the abnormal area of the memory.
6. The method of claim 1, wherein migrating data in the area with data to an area without data when the first built-in self test passes comprises:
when the first built-in self test passes, reading data in an area where data are stored according to a processor pointer, writing the data into the area where the data are not stored, and jumping the processor pointer to a storage address of the area where the data are not stored.
7. A memory test device, applied to a memory test system for testing a RAM, the memory test system including a memory test device, a test control module, and a memory built-in self test circuit, the test control module being connected to the memory built-in self test circuit through a test access port, the memory built-in self test circuit including a test vector generation circuit, a built-in self test control circuit, and a response analyzer, the device comprising:
the signal acquisition module is used for acquiring a first test signal and a second test signal, wherein the first test signal is used for carrying out memory built-in self-test on an area which does not store data in the memory to be tested, and the second test signal is used for carrying out memory built-in self-test on the area which stores data in the memory to be tested;
the first test control module is used for inputting a first test signal to the memory built-in self-test circuit through the test control module, carrying out a first built-in self-test on the region without data and obtaining a test result of the first built-in self-test;
the data migration module is used for migrating the data in the area with the stored data to the area without the stored data when the first built-in self test passes;
the second test control module is used for inputting a second test signal to the memory built-in self-test circuit through the test control module, carrying out a second built-in self-test on the area with the data, and acquiring a test result of the memory to be tested according to a result of the second built-in self-test;
the first test control module is specifically configured to:
restoring the first test signal in a read-write mode through the test control module, inputting the first test signal to a test vector generating circuit, and controlling the test vector generating circuit to generate a corresponding test vector, wherein the test vector generating circuit is used for generating a test vector for testing the memory to be tested according to the first test signal, and the test vector is used for testing the failure type of the memory;
sending the test vector to the built-in self-test control circuit, and inputting the test vector to the area without data through the built-in self-test control circuit;
and obtaining the test response of the area without data to the test vector through the response analyzer, and obtaining the test result of the first built-in self-test according to the test response.
8. The apparatus of claim 7, further comprising a fault interruption determination module configured to determine that the memory under test fails when the first built-in self test fails.
9. A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor implements the steps of the method of any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 6.
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| CN113391184A (en) * | 2020-03-11 | 2021-09-14 | 长鑫存储技术有限公司 | Control chip test method and related equipment |
| CN113393893A (en) | 2020-03-11 | 2021-09-14 | 长鑫存储技术有限公司 | Memory test method and related equipment |
| CN113393888A (en) | 2020-03-11 | 2021-09-14 | 长鑫存储技术有限公司 | Memory test method and related equipment |
| CN111933206B (en) * | 2020-07-31 | 2021-06-18 | 上海安路信息科技股份有限公司 | Built-in self-test method and test system for DDR physical layer address command path |
| CN113190389B (en) * | 2021-04-14 | 2024-10-29 | 西安紫光国芯半导体股份有限公司 | Self-test method, test device, and computer-readable storage medium |
| CN117242526A (en) * | 2021-06-30 | 2023-12-15 | 华为技术有限公司 | Method and device for testing memory |
| CN118072806A (en) * | 2022-12-30 | 2024-05-24 | 深圳市速腾聚创科技有限公司 | Memory detection method, integrated circuit device, storage medium, and laser radar |
| CN116758968B (en) * | 2023-08-16 | 2023-12-08 | 英诺达(成都)电子科技有限公司 | Built-in self-test method for memory and circuit and chip thereof |
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