CN110113050B

CN110113050B - Mismatch error correction method applied to successive approximation analog-to-digital converter

Info

Publication number: CN110113050B
Application number: CN201910367262.4A
Authority: CN
Inventors: 樊华; 雷鹏; 冯全源; 蔡经纬; 李大刚; 胡达千; 岑远军
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2019-05-05
Filing date: 2019-05-05
Publication date: 2021-07-06
Anticipated expiration: 2039-05-05
Also published as: CN110113050A

Abstract

The invention discloses a mismatch error correction method applied to a successive approximation analog-to-digital converter. The capacitors of the capacitor DAC array are divided into unit capacitor arrays, the unit capacitors are sequentially divided into four groups, and the capacitors are selected at intervals of each group to form capacitors such as MSB and MSB-1 of the capacitor DAC array. Dynamic parameters such as SNDR and SFDR of the traditional correction algorithm and the novel correction algorithm are simulated through MATLAB, and the dynamic performance of the SAR ADC is further improved by the obtained novel correction algorithm.

Description

Mismatch error correction method applied to successive approximation analog-to-digital converter

Technical Field

The invention relates to the field of microelectronics and solid electronics, in particular to a capacitor array setting method in a resistance-capacitance type successive approximation analog-digital converter in the field.

Background

With the rapid development of modern science and technology, the integrated circuit technology has been developed rapidly, the Analog signal processing technology and the Digital signal processing technology have become mature, and at the same time, it is important to seek high-precision technology for the bridge between the Analog world and the Digital world, i.e., the Analog-to-Digital Converter (ADC) and the Digital-to-Analog Converter (DAC). The analog-to-digital converter is mainly classified into a successive approximation analog-to-digital converter (SAR ADC), an integral analog-to-digital converter (ADC), a Flash comparison analog-to-digital converter (Flash ADC), a Pipeline analog-to-digital converter (Pipeline ADC), and the like. Due to the feature size reduction of CMOS in recent years, the speed of the device is faster and faster, and the sampling rate of SAR ADC can reach dozens of MS/s or even GS/s. In addition, the SAR ADC has low power consumption and low cost, and is therefore favored by some portable systems.

Affecting the accuracy of capacitive SAR ADCs includes mainly capacitance mismatch problems, parasitic capacitance problems, and the like, in addition to noise. These factors are the short boards that SAR ADC pursues high precision and low power consumption, so that reaching acceptable precision and power consumption at a certain sampling speed becomes a difficult problem that must be overcome. The capacitance mismatch problem is mainly caused by some non-negligible error between the sampling capacitance value and the ideal value of the capacitance DAC array due to process errors, and such error not only causes the reduction of the dynamic performance of the SAR ADC, but also causes the failure of conversion. Therefore, the invention provides a correction method based on capacitor array reordering combination aiming at the problem of capacitor mismatch.

Patent CN108880546 discloses a conventional capacitor array calibration method applied to successive approximation analog-to-digital converter, which divides all capacitors into unit capacitors, then adopts odd number selection method to form the highest-level capacitor of successive approximation analog-to-digital converter for the sorted unit capacitor array, and then adopts odd number selection method to form other-level capacitors of successive approximation analog-to-digital converter for the selected unit capacitors in the remaining unit capacitors each time. Because of manufacturing process errors, which cause the actual capacitance to deviate from the ideal capacitance, it is generally modeled as a statistic conforming to a gaussian distribution by the amount of error. For a conventional binary capacitor array, the high-order capacitors are equivalent to the combination of unit capacitors, and the value of the unit capacitors may be smaller (or larger) due to the existence of capacitance mismatch, so that the high-order capacitors combined by the unit capacitors are also smaller (or larger) in overall value, and for the binary DAC array, the conversion process is directly affected, which results in reduced dynamic performance. For the capacitor array of the sequencing reconstruction, the unit capacitors with the error amount larger than zero and the error amount smaller than zero are combined to form a new element with the error amount near zero, and then the high-order capacitor with the integral error amount near zero is obtained according to the combination mode. The capacitor array which is reconstructed by sequencing enables unit capacitors with large positive and negative difference of error quantity to be subjected to complementary combination, so that the error quantity of new elements combined by the unit capacitors tends to be zero, and the influence caused by capacitor mismatch can be reduced. In addition, the conventional capacitor array correction algorithm proposed in patent CN108880546 is significantly improved in dynamic performance compared to the conventional capacitor array without correction by combining the new elements in a first-and-last manner, but because the standard deviation of the two unit capacitors forming the new elements is different, the capacitance formed by combining the new elements does not reach the ideal value, and therefore has a certain influence on the dynamic performance. Therefore, the invention provides a novel correction algorithm based on the traditional correction algorithm to further improve the dynamic performance.

Disclosure of Invention

The invention provides a capacitance array correction method based on statistics, aiming at the problem that the dynamic performance of an SAR ADC is reduced due to capacitance mismatch in the existing SAR ADC design.

The technical scheme of the invention is a mismatch error correction method applied to a successive approximation analog-to-digital converter, which comprises the following steps:

step 1: for the SAR ADC fully-differential structure, the positive side capacitor DAC array and the negative side capacitor DAC array are in a mirror image complementary relation; the positive side capacitor DAC array and the negative side capacitor DAC array are formed by n-2^mThe unit capacitors, n and m are positive integers;

step 2: sequencing the n unit capacitors from small to large, and numbering the n unit capacitors as 1, 2 and 3 … … n;

and step 3: dividing the unit capacitor array after the arrangement into four groups including a first group, a second group and a third group in sequence, wherein each group is provided with n/4 unit capacitors, and selecting the unit capacitors with odd numbers in the first group and the fourth group and the unit capacitors with even numbers in the second group and the third group as the MSB capacitors of the capacitor DAC array;

and 4, step 4: selecting half of the unit capacitors from the rest unit capacitors in each group at intervals, and combining the four groups of selected unit capacitors into the MSB-1 capacitor of the capacitor DAC array;

and 5: sequentially selecting the subsequent capacitors of the DAC array according to the method in the step 4 until only two unit capacitors of each group are left, selecting and combining the first unit capacitor in each group into an MSB- (m-3) capacitor, combining the last unit capacitors of the first group and the third group into an MSB- (m-2) capacitor, and respectively using the last unit capacitors of the second group and the fourth group as the MSB- (m-1) capacitor and the LSB;

step 6: and (5) according to the method from the step 1 to the step 5, the capacitor obtained by recombining the unit capacitors is used as a capacitor DAC array of the SAR ADC.

Compared with a non-sequencing method, the capacitor array correction method of the packet sequencing better avoids the dynamic performance influence caused by the capacitor mismatch of the SAR ADC, improves the dynamic parameters such as the stray-free dynamic range (SFDR) to a certain extent, and does not cause redundant waste in area and power consumption. The traditional capacitor array correction algorithm combined end to end may cause the value of the new element after combination to be still deviated from the ideal value due to the mismatch of the standard deviation of the two unit capacitors, thereby causing the dynamic performance to be not enhanced perfectly. Therefore, the novel correction algorithm realizes further increase of dynamic performance by adopting a mode of selecting unit capacitors at grouping intervals.

Drawings

Fig. 1 is a schematic diagram of a SAR ADC structure.

Fig. 2 is a schematic diagram of the sorting grouping part from step 1 to step 3 of the present invention.

Fig. 3 is a schematic diagram of the sorting grouping part from step 4 to step 6 according to the present invention.

Fig. 4 is a schematic diagram of a reconstruction part of the algorithm proposed by the present invention.

Figure 5 shows the simulation result of the 14-bit FFT corresponding to the correction algorithm proposed in patent CN 108880546.

Fig. 6 is a 14-bit FFT simulation result corresponding to the novel capacitance reconstruction algorithm of the present invention.

Figure 7 shows the simulation result of 16-bit FFT corresponding to the correction algorithm proposed in patent CN 108880546.

Fig. 8 is a 16-bit FFT simulation result corresponding to the novel capacitance reconstruction algorithm of the present invention.

Figure 9 shows the simulation result of 18-bit FFT corresponding to the correction algorithm proposed in patent CN 108880546.

Fig. 10 is a 18-bit FFT simulation result corresponding to the novel capacitance reconstruction algorithm of the present invention.

Detailed Description

The correction method for sequencing and reconstructing the capacitor array, which is provided by the invention, takes a 16-bit mixed capacitor resistance type SAR ADC consisting of a high eight-bit capacitor DAC and a low eight-bit resistor DAC as an architecture, and carries out simulation comparison with the traditional capacitor array by utilizing MATLAB.

The invention mainly aims at the problem of capacitance mismatch in a capacitance DAC array, so that all capacitances of the capacitance DAC array of the hybrid SAR ADC are replaced by the combination of unit capacitances C, for example, the most significant bit MSB capacitance is 32C, and the most significant bit MSB capacitance is expressed as the combination of 32 unit capacitances C. However, errors in manufacturing process cause certain errors between the actual value and the ideal value of the unit capacitor in the capacitor DAC array, thereby causing the dynamic performance of the SAR ADC to be reduced. This problem can be improved by ordering the reconstruction method (the specific operation is shown in fig. 2).

Firstly, sorting the whole 128 unit capacitors from small to large due to process errors of the unit capacitors, and naming C1, C2 and the like, so that the sorted unit capacitor array is divided into four groups; then, obtaining four groups of unit capacitors by extracting each group at intervals and combining the unit capacitors into an MSB capacitor, then selecting and combining the unit capacitors in the rest unit capacitor arrays of each group at intervals into an MSB-1 capacitor, repeating the steps until only two unit capacitors remain in each group, combining the first unit capacitor of each group into an MSB-4, and combining the rest unit capacitors of the first group and the third group into an MSB-5; and finally, taking the rest unit capacitances of the second group and the fourth group as MSB-6 and LSB respectively. The specific unit capacitance distribution of the tuning capacitor DAC array is shown in fig. 4.

Setting the capacitance mismatch rate of MATLAB to be 0.0015; the 14-bit MATLAB simulation results are shown in table 1, and the corresponding FFT simulations are shown in fig. 5 and 6; the MATLAB simulation results of the 16-bit conventional correction algorithm and the novel correction algorithm are shown in table 2, and the corresponding FFT simulations are shown in fig. 7 and 8; the 18-bit MATLAB simulation results are shown in table 3, and the corresponding FFT simulations are shown in fig. 9 and 10.

Performance parameter comparison of the 114-bit conventional correction algorithm to the novel correction algorithm

	Conventional correction algorithm	Novel correction algorithm
			ENOB	13.78	13.96
SNDR(dB)	84.72	85.82
			SFDR(dB)	93.95	102.37

Performance parameter comparison of table 216-bit conventional correction algorithm and novel correction algorithm

	Conventional correction algorithm	Novel correction algorithm
			ENOB	15.13	15.7
SNDR(dB)	92.90	96.25
			SFDR(dB)	101.24	107.14

Performance parameter comparison of the 318-bit conventional correction algorithm and the novel correction algorithm

	Conventional correction algorithm	Novel correction algorithm
			ENOB	16.36	17.08
SNDR(dB)	100.26	104.33
			SFDR(dB)	104.17	109.41

Claims

1. A mismatch error correction method for a successive approximation analog to digital converter, the method comprising:

step 1: for the SAR ADC fully-differential structure, the positive side capacitor DAC array and the negative side capacitor DAC array are in a mirror image complementary relation; the positive side capacitor DAC array and the negative side capacitor DAC array are formed by n =2^mThe unit capacitors, n and m are positive integers;

and 4, step 4: selecting half of the unit capacitors from the first starting interval in each group of the rest unit capacitors in step 3, and combining the four groups of the selected unit capacitors into the MSB-1 capacitor of the capacitor DAC array;

step 6: taking the capacitor obtained by recombining the unit capacitors as a capacitor DAC array of the SAR ADC according to the method of the step 1 to the step 5; and (4) adopting the newly obtained capacitor DAC array of the SAR ADC as a capacitor array of the successive approximation analog-to-digital converter to perform analog-to-digital conversion.