CN110109852B - Method for realizing TCP _ IP protocol by hardware - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/09—Mapping addresses
- H04L61/10—Mapping addresses of different types
- H04L61/103—Mapping addresses of different types across network layers, e.g. resolution of network layer into physical layer addresses or address resolution protocol [ARP]
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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- H04L61/09—Mapping addresses
- H04L61/25—Mapping addresses of the same type
- H04L61/2503—Translation of Internet protocol [IP] addresses
- H04L61/255—Maintenance or indexing of mapping tables
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- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
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- H—ELECTRICITY
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Abstract
The invention provides a system and a method for realizing a TCP _ IP protocol by hardware, which comprises an embedded CPU core, a configuration register, an engine module, a DDR3 interface controller and an MAC controller, wherein the embedded CPU core is used for establishing and maintaining a TCP/UDP connection and controlling the engine module; the configuration register is used for providing ToE network card information; the TCP _ UDP engine is used for moving the data to the DDR memory space of the network card; the IP engine is used for processing IP layer transactions; the ICMP engine is used for generating and analyzing the received control message packet; the ARP engine is used for converting the IP address into an MAC address; the RARP engine is used for mapping the MAC address to the IP address; the DDR3 interface controller is externally connected with a DDR memory; the MAC controller is used to send and receive ethernet frames. The invention establishes connection by the way that the embedded CPU core executes software, and can realize the establishment of any number of connections.
Description
Technical Field
The invention relates to the field of computer bus interfaces, in particular to a hardware system method for realizing a TCP _ IP protocol.
Background
The ethernet interface is one of the main interfaces of a computer, and is used for connecting the computer to a local area network or the internet. When a computer transmits data through the ethernet, the Transmission Protocol used is a TCP/IP (Transmission Control Protocol/Internet Protocol) Protocol. The TCP/IP protocol is generally implemented by software, and executing the TCP/IP protocol software occupies a large amount of computing resources of a host CPU (Central Processing Unit). In one way, 1-bit network data transmission consumes 1Hz of CPU processing power. When the network transmission rate of a computer is increased from 100Mbps to 1Gbps, even 10Gbps, a large amount of computing power of the CPU is consumed in the transmission process of network data. To reduce the load on the host CPU, ToE (TCP offload Engine) technology has been proposed in the industry, i.e., hardware is used to implement the TCP/IP protocol functions in whole or in part.
The traditional network card realizes the function of a data link layer in a TCP/IP network hierarchical structure, and the novel ToE network card realizes all the functions of a transmission layer, a network layer, a data link and the like in the TCP/IP network hierarchical structure. Regarding the implementation of the ToE network card, there have been some technical solutions, such as "system of trillion network TCP protocol offload engine TOE implemented based on FPGA (patent application number: 201620032397.7)", "multi-channel processing method in TCP/IP offload engine (patent application number: 201611110885.6)", "semi-offload method, design and system (patent application number: 201310260360.0)", and the like. From the disclosures of these patent applications, these ToE implementations all suffer from drawbacks, such as a limited number of connections supported, or a partial implementation of ToE functionality, resulting in an incomplete offload of the host operating system's TCP/IP protocol stack.
Specifically, for the comparison document 1: the technical scheme is that the system for unloading the engine TOE of the TCP protocol stack of the gigabit network based on the FPGA is realized by adopting a hardware logic mode according to the process of establishing connection and transmitting data by a TCP/IP protocol stack. The disadvantage of this solution is that only one connection can be established at a time, and parallel processing of multiple connections is not supported. This arrangement is effective in applications where multiple connections are not required.
For reference 2: a multi-channel processing method in a TCP/IP offload engine supports multiple channels by adding a channel number to the header of a TCP packet on a connection basis. Each channel is a virtual connection, the purpose of which is to increase the number of connections. But this scheme would modify the standard format of TCP packets and only work in certain situations.
When the local computer communicates with the remote server through the network, the local computer needs to create a connection every time the local computer starts a network communication process, for example, 5 web pages of a website are opened on the local computer, 5 iexpcore processes are started, and each process needs to create a TCP connection. Until the local computer closes the ie browser program of a website, the corresponding TCP connection is disconnected. Therefore, it is still very desirable to support multiple parallel connections in practical applications.
The invention provides an ToE network card implementation scheme, which can completely uninstall a TCP/IP protocol stack of a host operating system, can support any number of connections, and is suitable for developing gigabit or ten-gigabit network card equipment.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a system and a method for realizing a TCP _ IP protocol by hardware.
The system for realizing the TCP _ IP protocol by hardware comprises an embedded CPU core, a configuration register, a TCP _ UDP engine, an IP engine, an ICMP engine, an ARP engine, an RARP engine, a DDR3 interface controller and an MAC controller, wherein:
the embedded CPU core is used for establishing and maintaining TCP/UDP connection and controlling a TCP _ UDP engine, an IP engine, an ICMP engine, an ARP engine and an RARP engine;
the configuration register is used for providing ToE basic configuration/control/status information of the network card;
the TCP _ UDP engine is used for moving the data to be sent by the CPU of the host computer to the DDR memory space of the ToE network card;
the IP engine is used for processing IP layer transactions;
the ICMP engine is used for generating a control message packet so as to analyze the received control message packet;
the ARP engine is used for converting the IP address into an MAC address;
the RARP engine is used for mapping the MAC address to the IP address;
the DDR3 interface controller is externally connected with a DDR memory;
the MAC controller is used to send and receive ethernet frames.
Preferably, the ethernet frame comprises 1518 bytes, wherein:
the Ethernet header is provided with 14 bytes;
the IP header is provided with 20 bytes;
the TCP header is provided with 20 bytes;
the application data is provided with 1460 bytes;
the ethernet trailer is provided with 4 bytes.
Preferably, the external DDR memory is a DDR memory with the capacity of 512MB or more.
Preferably, the MAC controller is a gigabit MAC controller.
The invention also provides a method for realizing the TCP _ IP protocol by hardware, which comprises the following steps:
data moving step: when the host application layer program sends data, the embedded CPU core initializes DMA in a TCP _ UDP engine according to an ToE network card command, the DMA moves the sent data from a host memory to a DDR memory of a ToE network card, and the sending data is filled into an Ethernet frame according to the data structure of the Ethernet frame;
and (3) classification step: when receiving Ethernet frame data, the MAC controller classifies the Ethernet frames, and respectively sends the Ethernet frames to an ARP engine, an ICMP engine, an IP engine or a TCP _ UDP engine according to the classification result, and each engine respectively analyzes the Ethernet frame data;
a storage allocation step: when the network card is initialized, the embedded CPU core divides a storage area in the DDR memory and stores descriptor information;
describing the attached table addressing step: addressing the descriptor based on a Hash function;
a connection establishment step: the embedded CPU kernel establishes TCP or UDP connection, and one table item is allocated in the connection descriptor table every time one connection is established;
and an Ethernet frame sending step: after the ethernet frame data structure is filled, the state of the ethernet frame data structure is changed to Ready, and the MAC controller automatically sends out the ethernet frame in the state of Ready.
Preferably, the storage allocation step comprises: space for 8 x 2K descriptors is allocated in DDR memory, the descriptors being organized in 2048 sets of 8 descriptors per Set.
Preferably, the describing additional table addressing step comprises: hash calculation is carried out according to the source port number, the source IP address, the destination port number and the destination IP address, a Set number of 11-bit access descriptors is generated, and the descriptors are addressed according to the comparison of the source port number, the source IP address, the destination port number and the destination IP address with 8 descriptors in the Set; if none of the 8 descriptors miss, then the secondary descriptor table is consulted.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention creates connection by the way that the embedded CPU core executes software, each connection uses a connection descriptor to describe the state information and attribute information of the connection, the connection descriptor is temporarily stored in the DDR memory of ToE network cards, and any number of connections can be created as long as the DDR memory capacity of ToE network cards is large enough.
2. The connection descriptor is addressed in a Hash index mode, and the access to the connection descriptor is convenient.
3. The invention adopts a fixed data structure body to be stored in the DDR memory, reduces the data moving cost when the data is processed in different protocol layers, and facilitates the data management of hardware.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a block diagram of the ToE network card controller of the present invention;
FIG. 2 is a diagram of an Ethernet frame data structure in accordance with the present invention;
FIG. 3 is a schematic diagram of a connection descriptor according to the present invention;
fig. 4 is an organizational diagram of the connection descriptor table of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Fig. 1 shows a block diagram of the ToE network card according to the present invention. The main working method for realizing the ToE function is as follows:
the method for realizing the TCP unloading engine comprises two parts: ToE network card hardware part and ToE network card driver software part. Wherein ToE the driver of the network card provides API (application Programming interface) interface of traditional TCP/IP protocol, the access of the operating system or application program to TCP/IP protocol will be converted by the driver of ToE network card, access ToE the hardware part of the network card; ToE the hardware part of the network card includes: an embedded CPU core, a configuration register, a TCP _ UDP engine, an IP engine, an ICMP (Internet Control Message Protocol) engine, an ARP (Address Resolution Protocol) engine, an RARP (Reverse Address Resolution Protocol) engine, a DDR3 interface controller, and a gigabit/gigabit MAC controller, wherein: the embedded CPU core is responsible for establishing and maintaining TCP/UDP connection and controlling modules such as a TCP _ UDP engine and the like; the configuration register is used as a PCI configuration space register of the network card equipment and provides basic configuration/control/state information of the network card; the TCP _ UDP engine is responsible for moving the data to be sent by the CPU of the host computer to the DDR memory space of the ToE network card and dividing the data into Ethernet frames according to the Ethernet frame format; having extracted data from the received ethernet frame, transmitted to the DDR memory space of the host CPU; in addition, the TCP _ UDP engine is also responsible for filling in information related to TCP/UDP in the ethernet frame, such as source port number, destination port number, sequence number, etc.; the IP engine is responsible for processing transactions related to the IP layer, such as padding IP header information related to the IP layer in the transmitted ethernet frame, calculating a checksum, extracting IP header information from the received ethernet frame, performing a check calculation, and the like; the ICMP engine is responsible for generating a control message packet so as to analyze the received control message packet; the ARP engine is responsible for translating IP addresses into MAC addresses. An address translation table is arranged in an ARP engine, the latest IP address and MAC address mapping table entries are cached, if the address translation table is not inquired, an ARP Ethernet frame is automatically generated, broadcasted to a local area network, and the received ARP frame is analyzed; the RARP engine is responsible for mapping the MAC address to the IP address; the DDR3 interface controller is responsible for externally connecting a large-capacity (512 MB or more) DDR memory, the DDR memory buffers sent and received Ethernet frames, and buffers a CPU kernel program and various descriptor tables; the gigabit/gigabit MAC controller is responsible for sending and receiving ethernet frames.
The key point of the invention is the organization of TCP/UDP data packets, IP packets and Ethernet frames. ToE the network card uses ethernet frame as the basic unit for data transmission and reception management, and fig. 2 shows the data structure of an ethernet frame. The data structure of the Ethernet frame is fixed, and the TCP _ UDP engine respectively fills the content of the corresponding part in the Ethernet frame according to the IP engine, the MAC controller, the embedded CPU core and the like, or analyzes the content of the corresponding part of the received Ethernet frame; the fixed Ethernet frame data structure is used as a management unit for transmitting and receiving data so as to reduce data moving overhead when the data is processed in different protocol layers and facilitate hardware management of the data;
when the host application layer program sends data, the embedded CPU core initializes DMA in a TCP _ UDP engine according to an ToE network card command, the DMA is responsible for moving the sent data from a host memory to a DDR memory of a ToE network card, and the sending data is filled into an Ethernet frame according to the data structure of the Ethernet frame;
when receiving the Ethernet frame data, the MAC controller firstly classifies the Ethernet frames, and respectively sends the Ethernet frames to an ARP engine, an ICMP engine, an IP engine or a TCP _ UDP engine according to the classification result, and each engine respectively analyzes the Ethernet frame data. If the data packet is a TCP _ UDP data packet, reporting the main CPU in an interrupt mode, calling ToE a driver function of the network card by the main CPU, controlling the embedded CPU core by the driver function, configuring DMA in the TCP _ UDP by the embedded CPU core, extracting the data in the Ethernet frame, and transmitting the data to a system memory of the host;
the embedded CPU core is responsible for establishing TCP or UDP connections. Each connection is represented by a connection descriptor, the format of which is shown in fig. 3. When the network card is initialized, the embedded CPU core divides a storage area in the DDR memory and stores descriptor information. The descriptors in the DDR memory are organized in an 8 x 2K array, as shown in FIG. 4.
When the embedded CPU core is initialized, 8 x 2K descriptor space is distributed in the DDR memory, and the descriptors are organized according to 2048 sets and 8 descriptors in each Set. When the descriptor is addressed, Hash calculation is carried out according to the source port number, the source IP address, the destination port number and the destination IP address, a Set number of an 11-bit access descriptor is generated, and then the descriptor is compared with 8 descriptors in the Set according to the source port number, the source IP address, the destination port number and the destination IP address, so that the descriptor is addressed; if none of the 8 descriptors miss, then the secondary descriptor table is consulted.
The first level connection descriptor table has 8 x 2K items, and can have a second level connection descriptor table and a third level connection descriptor table, so that any number of connection numbers can be supported;
the TCP/UDP connection is established by the embedded CPU core, and one table item is allocated in the connection descriptor table every time one connection is established. After the connection is established, the TCP _ UDP engine applies for distributing the storage space of the Ethernet frame data structure according to the content of the descriptor table and moves data between the memory of the host system and the DDR memory of the network card;
after the contents of the ethernet frame data structure are filled, the state of the frame data structure changes to Ready. Whenever there is an ethernet frame in the state Ready, the MAC controller will automatically send out the ethernet frame.
The invention can be realized by adopting a field programmable gate array FPGA, and can also be realized by developing a special ToE network card controller chip. Meanwhile, according to needs, a PCIe network card board can be developed based on an FPGA or ToE network card controller chip, and the FPGA or ToE network card controller chip can also be placed on a target system application board (such as a system mainboard).
According to the technical scheme of the invention, a universal ToE network card can be designed. When the FPGA or the special chip realizes the ToE network card function, a matched ToE network card driving program needs to be provided.
Applicants have successfully developed an FPGA-based PCIe 4x interface ToE network card that can support 16K TCP/UDP connections. Through tests, in a gigabit local area network environment, the transmission rate can reach 100MB/s for the transmission of large files (4 GB).
In the invention, because the computing performance of the embedded CPU core is limited, some processing in the transmission and receiving processes of the TCP/IP data packet, such as the division of the TCP/UDP data packet into frames, the CRC check of an IP head, an ARP protocol, an ICMP protocol and the like, is realized by adopting a customized logic and is used as a hardware acceleration processing module. In order to facilitate the acceleration processing modules to identify and process the transmitted or received data, the scheme requires that the data is organized according to a standard format defined by a TCP/IP protocol and stored in a DDR memory in a fixed data structure body. Because the maximum length of the network transmission Ethernet frame is 1518 bytes, the scheme takes the maximum frame length 1518 bytes as a structural body and is used as a buffer carrier for sending and receiving data. That is, the data structure (data buffer, or data Buf) of the transmission and reception data is fixed to 1518 bytes, and the number of valid bytes therein is determined by the length field of the header. When the application program sends and receives data, a space is allocated in the system memory to cache the sent or received data. Data transfer between the system memory and the DDR memory of the ToE network card is completed through the DMA embedded in the ToE network card. The DMA is responsible for dividing data into data Buf structures in addition to data movement. This is a feature of the present invention.
The invention improves ToE network card data receiving and transmitting performance by customizing hardware acceleration module and optimizing data receiving and transmitting organization structure.
The invention focuses on the definition and organization of the data structure body, and the performance of transmitting data by the network card is improved ToE by optimizing the organization of the data structure body. The prior art is not seen to disclose this aspect at present.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (6)
1. A method for realizing a TCP _ IP protocol by hardware is characterized in that the method for realizing the TCP _ IP protocol by the hardware is realized based on a system for realizing the TCP _ IP protocol by the hardware, and the method for realizing the TCP _ IP protocol by the hardware comprises the following steps:
data moving step: when the host application layer program sends data, the embedded CPU core initializes DMA in a TCP _ UDP engine according to an ToE network card command, the DMA moves the sent data from a host memory to a DDR memory of a ToE network card, and the sending data is filled into an Ethernet frame according to the data structure of the Ethernet frame;
and (3) classification step: when receiving Ethernet frame data, the MAC controller classifies the Ethernet frames, and respectively sends the Ethernet frames to an ARP engine, an ICMP engine, an IP engine or a TCP _ UDP engine according to the classification result, and each engine respectively analyzes the Ethernet frame data;
a storage allocation step: when the network card is initialized, the embedded CPU core divides a storage area in the DDR memory and stores descriptor information;
describing the attached table addressing step: addressing the descriptor based on a Hash function;
a connection establishment step: the embedded CPU kernel establishes TCP or UDP connection, and one table item is allocated in the connection descriptor table every time one connection is established;
and an Ethernet frame sending step: after the Ethernet frame data structure is filled, the state of the Ethernet frame structure is changed into Ready, and the MAC controller automatically sends out the Ethernet frame in the Ready state;
the system for realizing the TCP _ IP protocol by hardware comprises an embedded CPU core, a configuration register, a TCP _ UDP engine, an IP engine, an ICMP engine, an ARP engine, an RARP engine, a DDR3 interface controller and an MAC controller, wherein:
the embedded CPU core is used for establishing and maintaining TCP/UDP connection and controlling a TCP _ UDP engine, an IP engine, an ICMP engine, an ARP engine and an RARP engine;
the configuration register is used for providing ToE basic configuration/control/status information of the network card;
the TCP _ UDP engine is used for moving the data to be sent by the CPU of the host computer to the DDR memory space of the ToE network card;
the IP engine is used for processing IP layer transactions;
the ICMP engine is used for generating a control message packet and analyzing the received control message packet;
the ARP engine is used for converting the IP address into an MAC address;
the RARP engine is used for mapping the MAC address to the IP address;
the DDR3 interface controller is externally connected with a DDR memory;
the MAC controller is used to send and receive ethernet frames.
2. The method of claim 1, wherein the step of allocating memory comprises: space for 8 x 2K descriptors is allocated in DDR memory, the descriptors being organized in 2048 sets of 8 descriptors per Set.
3. The method of claim 1, wherein the step of describing the addressing of the attached tables comprises: hash calculation is carried out according to the source port number, the source IP address, the destination port number and the destination IP address, a Set number of 11-bit access descriptors is generated, and the descriptors are addressed according to the comparison of the source port number, the source IP address, the destination port number and the destination IP address with 8 descriptors in the Set; if none of the 8 descriptors miss, then the secondary descriptor table is consulted.
4. The hardware implemented TCP _ IP protocol method of claim 1, wherein the ethernet frame comprises 1518 bytes, wherein:
the Ethernet header is provided with 14 bytes;
the IP header is provided with 20 bytes;
the TCP header is provided with 20 bytes;
the application data is provided with 1460 bytes;
the ethernet trailer is provided with 4 bytes.
5. The method for realizing the TCP _ IP protocol by hardware according to claim 1, wherein the external DDR memory is a DDR memory with a capacity of 512MB or more.
6. The method of claim 1, wherein the MAC controller is a gigabit/ten gigabit MAC controller.
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