CN110085134B

CN110085134B - Display device

Info

Publication number: CN110085134B
Application number: CN201910277765.2A
Authority: CN
Inventors: 奚鹏博
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2018-04-18
Filing date: 2019-04-08
Publication date: 2021-08-27
Anticipated expiration: 2039-04-08
Also published as: CN110085134A

Abstract

A display device includes a plurality of display elements. The display elements are arranged in an array and connected to each other. One of the display elements transmits the alternating current signal to the other of the display elements. The display element includes an alternating current signal line for transmitting an alternating current signal, first and second connection wires vertically crossing each other, a pixel including a driving transistor and a light emitting element, and first and second shield wires. The pixels are arranged at the crossed position of the first connecting wire and the second connecting wire. The first shielding wire is arranged between the alternating current signal line and the pixel. The second shielding wire is arranged between the alternating current signal wire and the pixel. The first shielding wire and the second shielding wire are at a voltage level of a drain terminal of the driving transistor.

Description

Display device

Technical Field

The present disclosure relates to a display device, and more particularly, to a tiled display device.

Background

With the development of science and technology, the demand of the tiled large-size display device is more and more extensive. However, the existence of a large amount of ac signals in the display area of the tiled display device causes noise to affect the driving current of the leds.

Therefore, how to reduce the interference of the ac signal with the panel display is one of the issues in the art.

Disclosure of Invention

One embodiment of the present disclosure relates to a display device including a plurality of display elements. The display elements are arranged in an array and connected to each other. One of the display elements transmits the alternating current signal to the other of the display elements. The display element includes an alternating current signal line for transmitting an alternating current signal, first and second connection wires vertically crossing each other, a pixel including a driving transistor and a light emitting element, and first and second shield wires. The pixels are arranged at the crossed position of the first connecting wire and the second connecting wire. The first shielding wire is arranged between the alternating current signal line and the pixel. The second shielding wire is arranged between the alternating current signal wire and the pixel. The first shielding wire and the second shielding wire are at a voltage level (level) of the drain terminal of the driving transistor.

One embodiment of the present disclosure relates to another display device including a plurality of display elements. The display elements are arranged in an array and connected to each other. One of the display elements transmits the alternating current signal to the other of the display elements. The display element includes first and second connection wires, a pixel, and a shield layer. The first and second connecting wires are vertically staggered with each other to define a plurality of spacing blocks. The pixel comprises a driving transistor and a light-emitting element which are arranged at the crossed and overlapped part of the first connecting lead and the second connecting lead. The shielding layer is configured in the spacing block. The first and second connecting wires and the pixel are not overlapped with the shielding layer in the vertical projection direction. The shield layer is at the voltage level of the drain terminal of the drive transistor.

Drawings

Fig. 1A is a schematic diagram illustrating a display device according to some embodiments of the present disclosure.

FIG. 1B is a schematic diagram illustrating a pixel, according to some embodiments of the present disclosure.

Fig. 2A is a signal diagram illustrating a display element according to some embodiments of the present disclosure.

Fig. 2B is a signal diagram illustrating another display element according to some other embodiments of the present disclosure.

FIG. 3 is a schematic diagram illustrating a display element according to some embodiments of the present disclosure.

Fig. 4 shows a schematic cross-sectional view of the display element of the embodiment of fig. 3 along the cut line a4-a 4'.

Fig. 5 shows a schematic cross-sectional view of the display element of the embodiment of fig. 3 along the cut line a5-a 5'.

Fig. 6 shows a schematic cross-sectional view of the display element of the embodiment of fig. 3 along the cut line a6-a 6'.

Fig. 7A, 7B are schematic diagrams illustrating another display element according to some embodiments of the present disclosure.

Description of reference numerals:

100: display element

120: auxiliary circuit

900: display device

D1: display area

PX: pixel

SR: shift temporary storage device

And MUX: multiplexer

PAD: AC signal source

HL, VL-S, VL-D: connecting wire

GL: scanning line

DL: data line

T1, T2: transistor with a metal gate electrode

C1: capacitor with a capacitor element

VDD: high voltage of system

ACL: AC signal line

MESH: shielding layer

R1, RING: annular lead

DIN: data signal

CS: control signal

CK: clock signal (clock signal)

G [ N-1], G [ N +1 ]: scanning signal

ML1, ML 2: shielded conductor

O1: contact point

LED: light emitting element

And (3) ANO: anode terminal

CAT: cathode terminal

GS: substrate

AS: semiconductor layer

M1, M2: conductive layer

BP1, BP2, BP 3: insulating layer

N1, N2, N3, N4, N5: opening of the container

A4-A4 ', A5-A5 ', A6-A6 ': tangent line

X, Y, Z: direction of rotation

Detailed Description

The following embodiments are described in detail with reference to the drawings, but the embodiments are only for explaining the disclosure and not for limiting the disclosure, and the description of the structural operation is not for limiting the execution sequence thereof, and any structure with equivalent technical effects produced by the recombination of elements is included in the scope of the disclosure.

Please refer to fig. 1A. Fig. 1A is a schematic diagram illustrating a display device 900 according to some embodiments of the present disclosure. As shown in fig. 1A, the display device 900 includes a plurality of display elements. The display elements are arranged in an array and connected to each other. The display element includes a pixel PX, a connection wire HL, and a connection wire VL. Structurally, the connecting wires HL and VL are vertically crossed, and the pixel PX is disposed at the position where the connecting wires HL and VL are crossed and overlapped. In other words, the connecting wires HL and VL form a grid shape, defining a plurality of cross points and a plurality of space blocks. The pixels PX are located at the staggered points to form a matrix arrangement.

Specifically, as shown in fig. 1B, the pixel PX includes transistors T1, T2, a capacitor C1, and a light emitting element LED. The connection line HL in fig. 1A includes the scan line GL in fig. 1B. The scan line GL is electrically coupled to the control terminal of the transistor T1. The connecting line VL in fig. 1A includes a clock signal line and the data line DL in fig. 1B. The data line DL is electrically coupled to the first terminal of the transistor T1. The second terminal of the transistor T1 is electrically coupled to the first terminal of the capacitor C1 and the control terminal of the transistor T2. The second terminal of the transistor T2 is electrically coupled to the second terminal of the capacitor C1 and the anode terminal of the light emitting device LED.

In operation, the transistor T1 is configured to receive a scan signal from the scan line GL, receive a data signal from the data line DL, and selectively turn on according to the scan signal to output the data signal to the transistor T2. The transistor T2 is configured to receive the system high voltage VDD from the first terminal, receive the data signal from the control terminal, and selectively turn on according to the data signal to output a driving current to the light emitting device LED. The light emitting element performs light emitting display according to the driving current.

In some embodiments, as shown in FIG. 1A, the display device 900 further includes an auxiliary signal source PAD or an auxiliary circuit 120 (e.g., a shift register SR, a multiplexer MUX). The auxiliary signal source PAD is configured to output an ac signal through the ac signal line ACL. The auxiliary circuit 120 is configured to receive or transmit an ac signal through the ac signal line ACL. In some other embodiments, the display elements in the display device 900 may include electrostatic Discharge (ESD) elements. Specifically, the display device 900 is a tiled display device, and is formed by tiling a plurality of display elements. The display elements of the display device 900 may be bezel-less displays. For example, as shown in FIG. 1A, the range D1 constructed by a plurality of display elements in the display device 900 is the display area. In other words, the ac signal source PAD and the auxiliary circuit 120 for transmitting the auxiliary signal in the display device 900 are disposed in the display area D1.

To explain further, as shown in fig. 1A, the ac signal source PAD may be disposed at the edge of the display area D1 in the display device 900. The auxiliary circuits 120 such as the shift register SR and the multiplexer MUX are disposed in the center of the display device. In some embodiments, the display elements including the shift register SR are located on both sides of the display device 900. The display elements including the multiplexer MUX are located at the upper or lower side of the display device 900.

It is to be noted that the pixel PX, the ac signal source PAD, and the auxiliary circuit 120 shown in fig. 1A are merely examples for convenience of illustration, and the size, number, and distribution thereof are not intended to limit the present disclosure.

Please refer to fig. 2A and fig. 2B. Fig. 2A, 2B are signal diagrams illustrating display elements according to some embodiments of the present disclosure. As shown in fig. 2A, the multiplexer MUX is used to transmit the multiplexer control signal CS and the data signal DIN through the ac signal line ACL. For example, the multiplexer MUX in the center of the display element receives the multiplexer control signal CS from the ac signal source PAD or the adjacent display element through the ac signal line ACL on the left side, and receives the data signal DIN from the ac signal source PAD or the adjacent display element through the ac signal line ACL on the upper side. The multiplexer MUX transmits the data signal DIN to the corresponding pixel PX according to the multiplexer control signal CS.

As shown in FIG. 2B, the shift register SR transmits the clock signal CK and the scanning signals G [ N-1], G [ N ] and G [ N +1] through the AC signal line ACL. For example, the shift register SR receives the clock signal CK and the scanning signal G [ N-1] from the AC signal source PAD or the adjacent display element through the lower AC signal line ACL. The shift register SR transmits the scanning signal G [ N ] to the next adjacent display element through the right AC signal line ACL according to the clock signal CK, and transmits the scanning signal G [ N +1] to the upper adjacent display element through the upper AC signal line ACL according to the clock signal CK.

In other words, since the AC signals (e.g., the clock signal CK, the data signal DIN, the scan signal G [ N ]) are transmitted between the display elements, various AC signals exist in the display area D1 of the display device 900. When an ac signal is transmitted between the pixels PX, a voltage difference between the source terminal and the gate terminal of the driving transistor of the pixel PX may be disturbed by the ac signal due to a coupling effect (coupled effect), thereby affecting the driving current output from the driving transistor, resulting in a decrease in stability of the driving current.

Please refer to fig. 3. Fig. 3 is a schematic diagram illustrating a display element 100 according to some embodiments of the present disclosure. In the embodiment shown in fig. 3, similar components to those in the embodiments of fig. 1A, fig. 2A and fig. 2B are denoted by the same reference numerals, and the operation and connection relationship thereof are already described in the previous paragraphs, and are not repeated herein. As shown in fig. 3, the display element 100 of the present disclosure includes an alternating-current signal line ACL, connection wirings HL, VL, a pixel PX, shielding wirings ML1, and ML 2. In some embodiments, the display device 100 further includes an auxiliary circuit 120.

Structurally, the shield wire ML1 is disposed between the ac signal line ACL and the pixel PX. The shield wire ML2 is disposed between the ac signal line ACL and the pixel PX. In some embodiments, as shown in fig. 3, the shield wire ML1 is parallel to the ac signal line ACL and the connection wire HL on the XY plane and is disposed between the ac signal line ACL and the connection wire HL. Shield lead ML2 is parallel to and disposed between ac signal line ACL and connection lead VL.

Wherein the shield wire ML1 and the shield wire ML2 are at a voltage level of a drain terminal of the driving transistor of the pixel PX. In some embodiments, the shielding wires ML1 and ML2 are electrically connected to the drain terminal of the driving transistor of the pixel PX, and the shielding wires ML1 and ML2 are at a system low voltage level (OVSS) or a ground level (0V).

In this way, since the shielding wires ML1 and ML2 separate the pixel PX from the ac signal line ACL, and since the shielding wires ML1 and ML2 are at the system low voltage level, the ac signal is shielded by the shielding wires ML1 and ML2, so that the source terminal of the driving transistor of the pixel PX is not disturbed.

For detailed configurations of the shield wires ML1 and ML2, please refer to fig. 4, 5, and 6. Fig. 4 shows a schematic cross-sectional view of the display element 100 of the embodiment of fig. 3 along the cut line a4-a 4'. As shown in FIG. 3, the tangent line A4-A4' is parallel to the Y direction. In fig. 4, a relative relationship on the YZ plane of the driving transistor, the light emitting element LED, the connection wirings HL, VL-D, VL-S, the shield wiring ML1, the alternating-current signal line ACL, the substrate GS, and the insulating layers BP1, BP2, BP3 in the pixel PX is shown. The connection wire HL, the shield wire ML1, and the ac signal line ACL are located on the same XY plane in the Z direction. The connecting leads VL-D, VL-S lie in the same XY plane in the Z direction.

Structurally, specifically, in the vertical projection direction (i.e., Z direction), the driving transistor is disposed on the substrate GS, and the light emitting element LED is disposed on the substrate GS and the driving transistor. For example, AS shown in fig. 4, the semiconductor layer AS is disposed on the substrate GS. The insulating layer BP1 is disposed on the substrate GS and the semiconductor layer AS, and the insulating layer BP1 covers at least a portion of the semiconductor layer AS. The connection wire HL is disposed on the semiconductor layer AS and the insulating layer BP1 and electrically connected to the gate terminal of the driving transistor. The insulation layer BP2 is disposed on the connection wires HL and the insulation layer BP 1. The connecting wires VL-D, VL-S are disposed on the insulating layer BP2 and electrically connected to the drain terminal and the source terminal of the driving transistor, respectively. The insulating layer BP2 was etched to form openings N1 and N2, so that the connection wires VL-D, VL-S were connected to the semiconductor layer AS via the openings N1 and N2, respectively. The insulation layer BP3 is disposed on the connecting wires VL-D, VL-S. The light emitting element LED is disposed on the insulating layer BP 3. The insulating layer BP3 is etched to form an opening N3 so that the anode terminal ANO of the light emitting element LED is connected to the connection wire VL-D via the opening N3. The cathode terminal CAT of the light emitting element LED is electrically connected to a cathode wire (not shown) of the display element.

In this embodiment, as shown in fig. 4, the display device 100 further includes a substrate GS, a first conductive layer M1, and a second conductive layer M2. In some embodiments, patterned metal wires, such as the connection wire HL, the shielding wire ML1, and the ac signal line ACL, are disposed in the first conductive layer M1 between the insulating layers BP1 and BP2 of the first conductive layer M1. The insulating layer BP2 is stacked on the first conductor layer M1. The second conductive layer M2 is disposed substantially on the insulating layer BP2, and patterned metal wires, for example, the connecting wires VL-D and VL-S, are disposed in the second conductive layer M2 and disposed on the second conductive layer M2 between the insulating layers BP2 and BP 3.

As shown in fig. 4, the shield wire ML1 is between the pixel PX and the alternating-current signal line ACL. In other words, the shield wire ML1 is between the connection wire VL and the alternating-current signal line ACL.

In some embodiments, the substrate GS may be implemented by a glass substrate, a plastic substrate, or other suitable rigid or flexible substrate. The connection wires HL, the shield wire ML1, and the alternating-current signal line ACL in the first conductor layer M1 and the connection wires VL-D and VL-S in the second conductor layer M2 may be implemented by metal or other conductive materials. The Light emitting element LED may be implemented by a Light-emitting diode (LED), a sub-millimeter Light emitting diode (mini LED), or a micro LED.

Fig. 5 shows a schematic cross-sectional view of the display element 100 of the embodiment of fig. 3 along the cut line a5-a 5'. In the embodiment shown in fig. 5, similar components to those in the embodiment of fig. 4 are denoted by the same reference numerals, and the structures and the connection relationships thereof are already described in the previous paragraphs, and are not repeated herein. As shown in FIG. 3, the tangent line A5-A5' is parallel to the X direction. In fig. 5, a relative relationship in the XZ plane of the driving transistor, the light emitting element LED, the connection wires HL, VL-D, VL-S, the shield wire ML2, the alternating-current signal line ACL, the substrate GS, and the insulating layers BP1, BP2, BP3 in the pixel PX is shown. The connecting wires VL-D, VL-S, the shield wire ML2, and the ac signal line ACL are located on the same XY plane in the Z direction. Specifically, the connection lead wires VL-D, VL-S, the shield lead wire ML2, and the ac signal line ACL are disposed on the second conductor layer M2 between the insulating layers BP2 and BP 3. As shown in fig. 5, the shield wire ML2 is between the pixel PX and the alternating-current signal line ACL. In other words, the shield wire ML2 is between the connection wire VL and the alternating-current signal line ACL.

Please refer to fig. 3 and fig. 6 together. Fig. 6 shows a schematic cross-sectional view of the display element 100 of the embodiment of fig. 3 along the cut line a6-a 6'. In the embodiment shown in fig. 6, similar components to those in the embodiments of fig. 4 and fig. 5 are denoted by the same reference numerals, and the structures and the connection relationships thereof have been described in the previous paragraphs, and are not repeated herein. As shown in FIG. 3, tangent line A5-A5' is at an angle of about 45 degrees to the X or Y direction. In fig. 6, the relative relationship of the driving transistor, the light emitting element LED, the connection wirings HL, VL-D, VL-S, the shield wirings ML1, ML2, the transistors in the auxiliary circuit 120, the substrate GS, and the insulating layers BP1, BP2, BP3 in the pixel PX is shown. The source terminal, the gate terminal, and the drain terminal of the transistor in the auxiliary circuit 120 are electrically connected to the ac signal line ACL, respectively.

The connection wire HL, the shield wire ML2, and the partial ac signal line ACL are located on the same XY plane in the Z direction. The connecting wires VL-D, VL-S, the shield wire ML2, and the partial ac signal line ACL are located on the other XY plane in the Z direction. Specifically, the connection wire HL, the shield wire ML2, and the partial ac signal line ACL are disposed on the first conductor layer M1 between the insulating layers BP1 and BP 2. The connection lead lines VL-D, VL-S, the shield lead line ML2, and the partial ac signal line ACL are disposed on the second conductor layer M2 between the insulating layers BP2 and BP 3.

In addition, as shown in fig. 3, in some embodiments, the shielding wires ML1 and ML2 are electrically coupled through the contact point O1. Specifically, as shown in fig. 6, the insulating layer BP2 is etched into an opening N4 so that the shield wire ML2 is connected to the shield wire ML1 via the opening N4.

In other words, as shown in fig. 3, a plurality of loop-shaped wires R1 are formed where the shielding wires ML1 and ML2 overlap in the vertical projection direction (i.e., the Z direction). The ring-shaped conductive lines R1 surround the pixels PX, respectively. In this way, since the annular wire R1 separates the pixel PX from the ac signal line ACL and since the annular wire R1 is at the system low voltage level or the ground level, the ac signal is shielded by the annular wire R1, and it is ensured that the source terminal of the driving transistor of the pixel PX is not disturbed.

It should be noted that the shielding wires ML1, ML2 and the ring-shaped wire R1 shown in fig. 3 are only examples for convenience of illustration, and the shape, size, distribution range and connection manner thereof can be designed by those skilled in the art according to the actual requirements, and are not limited thereto.

Please refer to fig. 7A. Fig. 7A is a schematic diagram illustrating another display element 100 according to some embodiments of the present disclosure. As shown in fig. 7A, the display element 100 includes connection wirings HL, VL, a pixel PX, and a shield layer MESH. In some embodiments, the display element 100 further includes an ac signal line ACL and an auxiliary circuit 120.

Structurally, similar to the embodiment of fig. 3, the connecting wires HL and VL are vertically staggered to form a grid shape, defining a plurality of staggered points and a plurality of spaced blocks. The pixels PX are arranged at the staggered points to form a matrix arrangement. The ac signal line ACL is partially located in the spacer block. The auxiliary circuit 120 is disposed in the spacer block. Compared with the embodiment shown in fig. 3, in the present embodiment, the shielding layer MESH is disposed in the spacer block. In other words, in the vertical projection direction (i.e., Z direction), the connecting wires HL and VL and the pixel PX do not overlap with the shielding layer MESH.

In addition, the shield layer MESH is at a voltage level of a drain terminal of the driving transistor of the pixel PX. In some embodiments, the shielding layer MESH is electrically connected to a drain terminal of the driving transistor of the pixel PX. In other words, the shield layer MESH is at a system low voltage level (OVSS) or a ground level (0V).

In this way, the shielding layer MESH is filled in the region outside the pixel PX, the auxiliary circuit 120 and the connecting wires HL and VL, so that the source terminal or the gate terminal of the driving transistor of the pixel PX can be prevented from being electrically interfered by the coupling of the ac signal.

Please refer to fig. 7B. Fig. 7B is a schematic diagram illustrating another display element 100, according to some embodiments of the present disclosure. In the embodiment shown in fig. 7B, similar elements to those in the embodiment of fig. 7A are denoted by the same reference numerals, and the operation and structure thereof are already described in the previous paragraphs, which are not repeated herein. As shown in fig. 7B, the display element 100 further includes a RING-shaped wire RING. Structurally, the RING wire RING is disposed around the pixels PX.

In addition, the RING wire RING is also at the voltage level of the drain terminal of the driving transistor of the pixel PX. In some embodiments, the RING wire RING is electrically connected to the drain terminal of the driving transistor of the pixel PX. In some other embodiments, the RING wire RING is electrically connected to the shielding layer MESH through a contact (not shown). In other words, the RING wire RING is also at system low voltage level (OVSS) or ground level (0V).

In this way, the source terminal or the gate terminal of the driving transistor of the pixel PX is not electrically interfered by the ac signal through the RING wire RING surrounding the pixel PX.

It should be noted that, in the case of no conflict, the features and circuits in the respective drawings, embodiments and embodiments of the present disclosure may be combined with each other. The circuits shown in the figures are for illustration purposes only and are simplified to simplify the explanation and facilitate understanding, and are not intended to limit the present disclosure. In addition, each device, unit and element in the above embodiments may be implemented by various types of digital or analog circuits, may be implemented by different integrated circuit chips, or may be integrated into a single chip. The foregoing is merely exemplary and the disclosure is not limited thereto.

In summary, the present disclosure enables the shielding wire, the ring-shaped wire and/or the shielding layer at a system low voltage level or a ground level to shield the ac signal without causing the source terminal or the gate terminal of the driving transistor to be disturbed by coupling by separating the driving transistor of the pixel PX from the ac signal line ACL through the shielding wire, the ring-shaped wire and/or the shielding layer by applying the above-described respective embodiments.

Although the present disclosure has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be determined by that of the appended claims.

Claims

1. A display device, comprising:

a plurality of display elements arranged in an array and interconnected, one of the plurality of display elements transmitting an alternating current signal to another of the plurality of display elements, any one of the plurality of display elements comprising:

an AC signal line for transmitting the AC signal;

a first connecting wire and a second connecting wire vertically staggered with each other;

a pixel, which is arranged at the position where the first connecting wire and the second connecting wire are mutually staggered and overlapped, and comprises a driving transistor and a light-emitting element;

a first shielding wire, which is configured between the AC signal line and the pixel;

a second shielding wire, which is configured between the AC signal line and the pixel; and

wherein the first shielding wire and the second shielding wire are at a voltage level of a drain terminal of the driving transistor.

2. The display device according to claim 1, wherein the first shielding wire is disposed between the ac signal line and the first connecting wire, and the second shielding wire is disposed between the ac signal line and the second connecting wire.

3. The display device of claim 1, wherein one of the plurality of display elements further comprises:

an auxiliary circuit coupled to the AC signal line for receiving or transmitting the AC signal via the AC signal line.

4. The display device according to claim 1, wherein each of the plurality of display elements further comprises a substrate, a first conductive layer and a second conductive layer, wherein the first connecting wire is disposed on the first conductive layer and electrically coupled to the gate terminal of the driving transistor, and the second connecting wire is disposed on the second conductive layer and electrically coupled to the source terminal of the driving transistor.

5. The display device according to claim 4, wherein the first shielding wire is disposed on the first conductive layer, the second shielding wire is disposed on the second conductive layer, and the ac signal line is disposed on the first conductive layer or the second conductive layer.

6. The display device of claim 5, wherein the first shielding conductive line and the second shielding conductive line are electrically coupled through a contact point.

7. The display device according to claim 6, wherein a plurality of loop-shaped wires are formed where the plurality of first shield wires and the plurality of second shield wires overlap in a vertical projection direction, the plurality of loop-shaped wires surrounding the plurality of pixels, respectively.

8. A display device, comprising:

the first connecting wires and the second connecting wires are vertically staggered with each other to define a plurality of interval blocks;

a plurality of pixels, wherein the pixels are arranged at the position where the first connecting wires and the second connecting wires are mutually staggered and overlapped, and each pixel comprises a driving transistor and a light-emitting element; and

a shielding layer disposed in the plurality of spacer blocks, the shielding layer being at a voltage level of drain terminals of the plurality of driving transistors,

wherein the plurality of first connecting wires, the plurality of second connecting wires and the plurality of pixels do not overlap with the shielding layer in a vertical projection direction.

9. The display device of claim 8, wherein one of the plurality of display elements further comprises:

an AC signal line partially located in the plurality of spacer blocks; and

and the auxiliary circuit is arranged in the plurality of spacing blocks and is coupled with the alternating current signal line for transmitting the alternating current signal through the alternating current signal line.

10. The display device of claim 8, wherein one of the plurality of display elements further comprises:

a ring conductor disposed around one of the plurality of pixels, the ring conductor being at a voltage level of a drain terminal of the drive transistor.