CN110073333A - Restore method, system and the FPGA device of the logic in fpga chip - Google Patents
Restore method, system and the FPGA device of the logic in fpga chip Download PDFInfo
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Abstract
A method of restoring or upgrade the logic in fpga chip.Two memories of first memory and second memory are introduced in FPGA device.In general, either user modification logic or chain of command upgrading logic be all second memory is first written, and save in first memory be then modification or upgrading before logic.If the modified logic of user or the logic of chain of command upgrading be loaded into after fpga chip enumerate it is unsuccessful, using the logic in the first logic reduction fpga chip in first memory.Although static logic can rapidly restore the logic in fpga chip using the above method because open may bring risk to user.To ensure that effective operation of fpga chip.
Description
The present embodiments relate to computer technology, especially a kind of method, system and FPGA device for restoring the logic in fpga chip.
In history, benefit from the lasting evolution of semiconductor technology, the handling capacity and system performance of Computer Architecture are continuously improved, every 18 months energy double (well-known " Moore's Law ") of the performance of processor, so that the performance of processor can satisfy the demand of application software.But semiconductor technology improvement in recent years has reached physics limit, processor performance can not be increased again according to Moore's Law, and another aspect data, which increase, to be required calculated performance to be more than the speed increased by " Moore's Law ".Processor itself is unable to satisfy the performance requirement of high-performance calculation (HPC:High Performance Compute) and parallel computation (figure, image and artificial intelligence) application software, leads to occur notch between demand and performance.In order to make up the notch, a kind of solution is to promote process performance using the Heterogeneous Computing mode of dedicated coprocessor by hardware-accelerated.
Field programmable gate array (Field Programmable Gate Array, FPGA) is used widely in Heterogeneous Computing because of advantages such as its programmability, low-power consumption.For example, when introducing FPGA, FPGA would generally be logically divided into static part and dynamic part by cloud service provider in public cloud.Wherein, static part is commonly used in realizing some basic functions, for example, DDR, DMA etc., and dynamic logic is then for realizing some service logics, such as picture encoding and decoding, encryption and decryption etc..From a security standpoint, static part logic is not usually open to user, and collects demand by cloud service provider, carries out universality design according to demand；And dynamic part can then be opened to user, user oneself can write the logic with change static part.With using the user of cloud service to increase, to meet the needs of users, the static part in FPGA needs the basic function realized can be more and more.What is generallyd use due to static logic is general-purpose interface, and distributing is more complicated, is reduced so as to cause the operational efficiency of FPGA.
If also opening static logic to user, is write and changed according to demand by user oneself, then the safety of FPGA device can not just ensure.Therefore, it while how opening static logic to user, and can guarantee the safety of FPGA device, become a problem in urgent need to solve.
Summary of the invention
In view of this, this application provides method, system and the FPGA devices of the logic in a kind of recovery fpga chip, to restore the logic in fpga chip.
The first aspect of the application provides a kind of method for restoring the logic in fpga chip, and this method is applied to FPGA device.The FPGA device includes the FGPA chip, first memory, second memory, wherein the first memory is stored with the first logic, and second logic is stored in the second memory, and second logic is the logic after the first logical renewal.This method comprises the following steps: the FPGA device receives the first load instruction that BMC is sent,
The first load instruction, which is used to indicate, is loaded into the fpga chip for first logic；The FPGA device disconnects the data channel between the fpga chip and the second memory according to the first load instruction, connects the data channel between the fpga chip and the first memory；First logic is loaded into the fpga chip by the data channel by the FPGA device.
Two memories of first memory and second memory are introduced in above-mentioned FPGA device.In general, either user modification logic or chain of command upgrading logic be all second memory is first written, and save in first memory be then modification or upgrading before logic.If the modified logic of user or the logic of chain of command upgrading be loaded into after fpga chip enumerate it is unsuccessful, using the logic in the first logic reduction fpga chip in first memory.Although static logic can rapidly restore the logic in fpga chip using the above method because open may bring risk to user.To ensure that effective operation of fpga chip.
In a kind of possible realization of the first aspect, the FPGA device further includes read-write controller and multiplexer MUX.Wherein, first load is received by the read-write controller to instruct.Then, the read-write controller sends first passage switching command to the MUX according to the first load instruction, and the first passage switching command is used to indicate the MUX and carries out channel switching.That is, switching the data channel between the MUX and first and second memory.After the MUX receives the first passage switching command, according to the first passage switching command, the data channel between the fpga chip and the second memory is disconnected, connects the data channel between the FPGA and the first memory.Channel is namely switched to first memory.The read-write controller sends the first load signal to the fpga chip after channel switching is completed, and the first load signal is for triggering the fpga chip load logic.First logic is loaded into fpga chip by the fpga chip according to the first load data channel of the signal by the fpga chip and the first memory.
In this concrete implementation, the cooperation of read-write controller and multiplexer is utilized dexterously to realize the switching between channel in FPGA device.It is a kind of mode of highly effective.
The first realization with reference to first aspect, in second of realization of first aspect, read-write controller receives the resetting instruction that the BMC is sent.Read-write controller indicates according to the resetting, and Xiang Suoshu multiplexer sends second channel switching command, and the second channel switching command is used to indicate the MUX and switches data channel between the MUX and first and second memory.The MUX disconnects the data channel between the fpga chip and the first memory according to the second channel switching command, connects the data channel between the FPGA and the second memory.
It is understood that in embodiments herein, channel is also switched back into second memory after fpga chip can be to logic before modification, to load continuing to modify and providing basis for the second logic or user again.Improve the flexibility of modification fpga chip.
Second of realization with reference to first aspect, in the third realization of first aspect, the fpga chip receives the second load instruction, and load request signal is sent to the read-write controller according to the second load instruction, the logic in the second load instruction instruction fpga chip load store device.The read-write controller receives the load request signal, and responds the load request signal and return to the second load signal to the fpga chip, and the second load signal is for triggering FPGA load logic.Second logic is loaded on the fpga chip according to the second load signal by the data channel between the FPGA and the second memory by the fpga chip.
Due to loading failure be it is unpredictable, when the switchback second memory of channel, user can need must load the second logic again, avoid the second logic can not being implemented because of accidentalia.
The third realization with reference to first aspect, is realized at the 4th kind of first aspect, first logic and described the
Two logics are PCIe static logic.And this method further includes following step.The fpga chip sends load to CPU and completes signal after the completion of second logic.Correspondingly, after the CPU receives load completion signal, the channel PCIe between the fpga chip and the CPU is enumerated.After enumerating successfully, the fpga chip loads non-PCIe static logic and dynamic logic by the channel PCIe between the CPU.
After the completion of the load of PCIe static logic, remaining static logic and dynamic logic are loaded on fpga chip by in-band method, greatly improve the speed of load.
The third realization with reference to first aspect, in the 5th kind of realization of first aspect, when the first memory is provided with write-protect, this method further includes following steps.The read-write controller receives first and writes data command; described first, which writes data command instruction, has data to that the first memory is written, and writes the instruction that data command sends third channel switching command to the multiplexer and sends closing write-protect to the first memory according to described first.The MUX disconnects the data channel between the fpga chip and second reservoir, connects the data channel between the FPGA and the first memory according to the channel switching command.The first memory closes write-protect according to the instruction for closing write-protect.
To avoid the malice to the first logic from distorting, in this implementation, first memory is provided with write-protect, when the data of chain of command are written, just closes its write-protect.
During above-mentioned the second to five kind with reference to first aspect is realized, the Read Controller is CPLD, and the MUX is SPI MUX, and the data channel is the channel SPI.
The second aspect of the application provides a kind of FPGA device, and the FPGA device includes FGPA chip, first memory, second memory, read-write controller and multiplexer.Wherein, the first memory is stored with the first logic, and second logic is stored in the second memory, and second logic is the logic after the first logical renewal.The read-write controller is for receiving the first load instruction, the first load instruction, which is used to indicate, is loaded into the fpga chip for first logic, and first passage switching command is sent to multiplexer according to the first load instruction and sends the first load signal to the fpga chip after channel switching is completed, wherein, the first passage switching command is used to indicate the MUX and switches data channel between the MUX and first and second memory, and the first load signal is for triggering the fpga chip load logic.The MUX is used to disconnect the data channel between the fpga chip and the second memory according to the first passage switching command, connect the data channel between the FPGA and the first memory.The fpga chip, for, by the data channel between the fpga chip and the first memory, first logic being loaded into fpga chip according to the first load signal.
It can be able to achieve in conjunction with one kind of second aspect, the read-write controller is also used to receive resetting instruction, second channel switching command is sent to the multiplexer according to resetting instruction, the second channel switching command is used to indicate the MUX and switches data channel between the MUX and first and second memory.And the MUX is also used to disconnect the data channel between the fpga chip and the first memory according to the second channel switching command, connect the data channel between the FPGA and the second memory.
In conjunction with the first possible realization of second aspect, in second of possible realization of second aspect, the fpga chip is for receiving the second load instruction, load request signal is sent to the read-write controller according to the second load instruction, the logic in the second load instruction instruction fpga chip load store device.The read-write controller is also used to receive load request signal, and responds the load request signal and return to the second load signal to the fpga chip, and the second load signal triggers FPGA load logic.The read-write controller sends load signal to the fpga chip, and the load signal triggers FPGA load logic.The fpga chip passes through the FPGA and institute according to the second load signal
The data channel between second memory is stated, second logic is loaded on the fpga chip.
In conjunction with second of possible realization of second aspect, in the third possible realization of second aspect, first logic and second logic are PCIe static logic, after second logic loads successfully, the fpga chip, which is also used to send load to CPU, completes signal, and after the CPU is enumerated successfully, non-PCIe static logic and dynamic logic are loaded by the channel PCIe between the fpga chip and CPU.
In conjunction with the third possible realization of second aspect; in the 4th kind of possible realization of second aspect; when the first memory is provided with write-protect; the read-write controller is also used to receive first and writes data command; described first, which writes data command instruction, has data to that the first memory is written, and writes the instruction that data command sends third channel switching command to the multiplexer and sends closing write-protect to the first memory according to described first.The MUX is also used to disconnect the data channel between the fpga chip and second reservoir according to the third channel switching command, connects the data channel between the fpga chip and the first memory.The first memory is also used to close write-protect according to the instruction for closing write-protect.
The third aspect of the application provides a kind of computer system, which includes central processing unit CPU, Baseboard Management Controller BMC and on-site programmable gate array FPGA equipment.The FPGA device includes the FGPA chip, first memory, second memory, wherein the first memory is stored with the first logic, and second logic is stored in the second memory, and second logic is the logic after the first logical renewal.The CPU is used for after enumerating the channel the PCIe failure between the CPU and FPGA device, enumerates failure news to BMC transmission.The BMC sends the first load instruction to FPGA device for enumerating failure news according to, and the first load instruction, which is used to indicate, is loaded into the fpga chip for first logic.The FPGA device is for receiving the first load instruction, the data channel between the fpga chip and the second memory is disconnected according to the first load instruction, the data channel between the fpga chip and the first memory is connected, and first logic is loaded by the fpga chip by the data channel.
Alternatively, in above-mentioned implementation, what the CPU was sent to BMC is escape instruction, and the escape instruction is used to indicate the logic loaded in the first memory；Correspondingly, the BMC is used to send the first load to the FPGA device according to escape instruction and instruct.
In a kind of possible implementation in conjunction with the third aspect, the FPGA device is also used to after having loaded first logic, and Xiang Suoshu CPU sends the first load and completes signal.After the CPU is also used to receive the first load completion signal, the channel PCIe between the CPU and FPGA device is enumerated, and enumerate successful message to BMC transmission after enumerating successfully.The BMC is also used to enumerate successful message according to the FPGA device and sends resetting instruction.The FPGA device is also used to disconnect the data channel between the fpga chip and the first memory according to the resetting instruction, connects the data channel between the FPGA and the second memory.
Alternatively, in a kind of this implementation, after enumerating successfully, what the CPU was sent to the BMC is the instruction for restoring former connection, and correspondingly, the BMC is also used to send resetting instruction to the FPGA device according to the instruction for restoring former connection.
In conjunction with the first realization of the third aspect, in second of realization of the third aspect, the BMC is also used to receive resetting success response from the FPGA device, and sends confirmation signal to the CPU to confirm that the data channel has switched.The CPU is also used to send the second load instruction to the FPGA device according to the confirmation signal, indicates the logic in the FPGA device load store device.The FPGA device is also used to after receiving the second load instruction, and by the data channel between the FPGA and the second memory, second logic is loaded on the fpga chip.
In conjunction with second of realization of the third aspect, in the third realization of the third aspect, the FPGA device is also used to after the completion of the second logic loads, the second load, which is sent, to the CPU completes signal, and after enumerating successfully, non-PCIe static logic and dynamic logic are loaded by the channel PCIe between the CPU.The CPU is also used to after receiving second load and completing signal, enumerates the channel PCI e between the FPGA device and the CPU.
In conjunction with second of the realization or the third realization of the third aspect, in the 4th kind of realization of the third aspect, the BMC is also used to complete signal according to the third load received, first is sent to the FPGA device and writes data command to indicate to have data to be written the first memory, and writes data command according to sending second to CPU from the confirmation signal that the FPGA device receives.The CPU is also used to after the FPGA device loads second logic and enumerates successfully, the third load, which is sent, to the BMC completes signal, and data command is write according to receive from BMC described second, second logic is written in Xiang Suoshu first memory.The FPGA device is also used to write data command according to described first, disconnect the data channel between the fpga chip and the second memory, the data channel between the fpga chip and the first memory is connected, and sends confirmation signal to the BMC after switching is completed.
In conjunction with the 4th kind of realization of the third aspect, in the 5th kind of realization of the third aspect, when the first memory is provided with write-protect, the BMC, which is also used to be loaded according to the third, completes signal, and Xiang Suoshu FPGA device sends write-protect out code.The FPGA device is also used to close the write-protect of the first memory according to the write-protect out code, and switches and send the confirmation signal to the BMC after completion and write-protect are closed.Two memories of first memory and second memory are introduced in above-mentioned FPGA device.In general, either user modification logic or chain of command upgrading logic be all second memory is first written, and save in first memory be then modification or upgrading before logic.If the modified logic of user or the logic of chain of command upgrading be loaded into after fpga chip enumerate it is unsuccessful, using the logic in the first logic reduction fpga chip in first memory.Although static logic can rapidly restore the logic in fpga chip using the above method because open may bring risk to user.To ensure that effective operation of fpga chip.
In order to illustrate the technical solution of the embodiments of the present invention more clearly, the drawings to be used in the embodiments are briefly described below.
Fig. 1 be the present embodiments relate to a kind of cloud structure schematic diagram；
Fig. 2 be the present embodiments relate to a kind of Computer Systems Organization schematic diagram；
Fig. 3 be the present embodiments relate to a kind of recovery fpga chip in logic flow diagram；
Fig. 4 be the present embodiments relate to a kind of upgrading fpga chip in logic flow diagram.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution provided in an embodiment of the present invention is described.
By taking public cloud as an example, as shown in Figure 1, publicly-owned cloud network includes the cloud environment of multiple client, multiple servers composition, these clients are connected through the internet in cloud environment, by server providing services in cloud environment.Illustratively, server (such as server 1) in cloud environment can as shown in Figure 2 (wherein, solid line is data channel, and dotted line is then signaling), it include: FPGA device, CPU, Baseboard Management Controller (baseboard management controller, BMC), read-write controller, wherein, FPGA device includes fpga chip, first memory and second memory, and first
It is stored with the first logic in memory, the second logic is stored in second memory, the second logic is the version after the first logical renewal.
In fact, chain of command is by defining some numerical calculation tasks using the Portal of cloud environment in linking Internet cloud environment in the initial stage.Then, which is compiled into the configuration file comprising information such as component connection types in cloud environment or bit stream is loaded into fpga chip.So far, the initial configuration to fpga chip is completed.For convenience, hereinafter this kind of configuration files or bit stream are known as logic, including static logic and dynamic logic by us.Wherein, static logic includes PCIe static logic and non-PCIe static logic.Initial p CIe static logic therein is written into above-mentioned first memory and second memory.Initial p CIe static logic is first written in second memory the data channel that can be first passed through between fpga chip and second memory, and the process being specifically written can refer to following step 302-304；After writing, CPU is sent completely instruction to BMC, shows that the operation of data write-in is completed.Connection after BMC receives completion instruction, between instruction FPGA device switching fpga chip and the first second memory, that is to say, that fpga chip is connected on first memory；Then, then by the connection between fpga chip and the first memory, initial p CIe static logic is written on first memory, the process being written here refers to following step 302-304, unlike, at this point, data write-in is first memory.That is, what is saved on initial stage, first memory and second memory is all initial p CIe static logic.
In addition, the sequence of above-mentioned write-in first memory and second memory can exchange, in the embodiment of the present invention with no restriction.It should be noted that if it is rear write-in first memory, then after writing, it is also necessary to which the channel of fpga chip and first memory disconnects, and the channel between fpga chip and second memory is opened.In this way, when user wants the logic of modification fpga chip or when chain of command is wanted to update the logic of fpga chip, updated PCIe static logic can be written in second memory by the channel between fpga chip and second memory, while user being avoided to modify the logic in first memory again.In order to which the logic preferably guaranteed on first memory is not maliciously tampered, the write-protect of first memory can also be opened after initial p CIe static logic is written on first memory.Correspondingly, if subsequent need that data are written, it is also desirable to first write-protect be closed.
It is understood that the initial p CIe static logic of above-mentioned chain of command publication is an example of first logic, and the updated PCIe static logic that above-mentioned user or chain of command provide is then an example of the second logic.
After the second logic is loaded into fpga chip, as usual, CPU can enumerate the channel PCIe between the CPU and FPGA device.In server provided in an embodiment of the present invention, the PCI e static logic on fpga chip can be restored as soon as possible after above-mentioned CPU is enumerated unsuccessfully.
Specifically, the CPU in the server is used for after enumerating the channel the PCIe failure between the CPU and FPGA device, failure news is enumerated to BMC transmission.The BMC is used to enumerate failure news according to this and sends the first load instruction to FPGA device, and the first load instruction, which is used to indicate, is loaded into the fpga chip for first logic.Because BMC is received after this enumerates failure news, it is known that need the logic of fpga chip being restored to the first logic, so having sent the first above-mentioned load instruction to FPGA device.Alternatively, it is also possible to after enumerating failure, CPU sends escape instruction to BMC, and escape instruction is used to indicate the logic loaded in the first memory, namely first logic, then BMC is instructed according to the escape sends the first load to the FPGA device and instructs.The FPGA device is for receiving the first load instruction, the data channel between the fpga chip and the second memory is disconnected according to the first load instruction, the data channel between the fpga chip and the first memory is connected, and first logic is loaded by the fpga chip by the data channel.The FPGA device can also send load to CPU and complete signal after having loaded first logic, enumerate in order to which CPU receives execution PCIe after signal is completed in the load.By enumerating
Method, CPU determines whether the CPU can be with normal communication with the channel PCIe between fpga chip.
Pass through above-mentioned scheme, although user can according to need the logic of modification fpga chip, including modifying static logic therein, but when loading the failure of updated PCIe static logic, it can be convenient and be promptly restored to the PCIe static logic on fpga chip on initial PCIe static logic.Equally, above-mentioned scheme is also applied for the scene of chain of command upgrading fpga chip logic, new edition PCIe static logic after chain of command upgrading can be first written in second memory, after loading the failure of new edition PCIe static logic, promptly the PCIe static logic on fpga chip is restored to by above-mentioned scheme on the PCIe static logic of the last revision of chain of command publication.
In specific application scenarios, above-mentioned FPGA device further includes read-write controller and multiplexer (Multiplexer, MUX), and the switching between first memory and second memory can be realized by read-write controller and MUX.The process of switching is as follows:
The read-write controller is for receiving the first load instruction, the first load instruction, which is used to indicate, is loaded into the fpga chip for first logic, and first passage switching command is sent to multiplexer according to the first load instruction and sends the first load signal to the fpga chip, wherein, the first passage switching command is used to indicate the MUX and switches data channel between the MUX and first and second memory, and the first load signal is for triggering the fpga chip load logic.The MUX is used to disconnect the data channel between the fpga chip and the second memory according to the first passage switching command, connect the data channel between the FPGA and the first memory.The fpga chip, for according to the first load data channel of the signal by the fpga chip and the first memory, first logic to be loaded into fpga chip.
In order to determine whether CPU can be with being restored to the communication of the fpga chip after the first logic, the fpga chip also needs after having loaded first logic, signal is completed to the first load of CPU transmission, is enumerated in order to which CPU receives execution PCI e after signal is completed in first load.If enumerating success, mean that CPU can be with normal communication with fpga chip.After this, user or chain of command can maintain the statusquo, and use initial logic.User or chain of command can continue to the more new version before load, and the latter makes an amendment the logic for loading failure before, including revision PCI e static logic part therein, form new more new version after modification, and load the new more new version.Relative to the initial PCIe static logic of chain of command publication, these versions are all updated versions, are hereinafter collectively referred to as updated PCIe static logic.There are in second memory for the PCIe static logic provided due to user, PCIe static logic after chain of command upgrading is also to pre-exist in second memory, therefore, it in order to which updated PCIe static logic to be loaded on fpga chip, needs fpga chip being connected to second memory.
That is, CPU is also used to after the channel PCIe between the CPU and FPGA device enumerates successfully, successful message is enumerated to BMC transmission.The BMC is also used to enumerate successful message according to and sends resetting instruction to FPGA.Alternatively, what CPU was sent to BMC is the instruction for restoring former connection, and the BMC sends the resetting to FPGA according to the instruction for restoring former connection and indicates.Here former connection i.e. the connection of fpga chip and second memory.The FPGA device is also used to disconnect the data channel between the fpga chip and the first memory according to the resetting instruction, connects the data channel between the FPGA and the second memory.Specific to FPGA device inside, the read-write controller is also used to receive resetting instruction, second channel switching command is sent to the multiplexer according to resetting instruction, the second channel switching command is used to indicate the MUX and switches data channel between the MUX and first and second memory.The MUX is according to being also used to disconnect the data channel between the fpga chip and the first memory according to the second channel switching command, connect the data channel between the fpga chip and the second memory.
After the fpga chip is already connected to second memory, the logic on second memory can be loaded again.Therefore, during one of the embodiment of the present invention can be able to achieve, the BMC is also used to receive resetting success response from the FPGA device, and sends confirmation signal to the CPU to confirm that the data channel has switched.The CPU is also used to send the second load instruction to the FPGA device according to the confirmation signal, indicates the logic in the FPGA device load store device.The FPGA device is also used to after receiving the second load instruction, and by the data channel between the FPGA and the second memory, second logic is loaded on the fpga chip.
Specific to FPGA device inside, when user or chain of command need to reload the second logic in second memory, the fpga chip is also used to receive the second load instruction, load request signal is sent to the read-write controller according to the second load instruction, the logic in the second load instruction instruction fpga chip load store device.Wherein, which can be after the confirmation signal that the CPU is sent according to BMC to FPGA device transmission.The confirmation signal can be the BMC from the FPGA device receive it is described resetting success response after to the CPU send.Correspondingly, the read-write controller is also used to receive load request signal, and responds the load request signal and return to the second load signal to the fpga chip, and the second load signal triggers FPGA load logic.Second logic is loaded on the fpga chip according to the second load signal by the data channel between the FPGA and the second memory by the fpga chip.
Further, the FPGA device is also used to after the completion of the second logic loads, and Xiang Suoshu CPU sends the second load and completes signal.The CPU is also used to after receiving second load and completing signal, enumerates the channel PCIe between the fpga chip and the CPU.The FPGA device is also used to after enumerating successfully, loads non-PCIe static logic and dynamic logic by the channel PCIe between the CPU.Specific to FPGA device inside, the fpga chip is also used to send second load to CPU and completes signal, and after the CPU is enumerated successfully, loads non-PCIe static logic and dynamic logic by the channel PCIe between the fpga chip and CPU.So far, user completes the modification or upgrading to logic in FPGA.For chain of command, in addition to the logic in upgrading second memory, it is also necessary to upgrade the logic in first memory.
Further, the BMC is also used to complete signal according to the third load received, first is sent to the FPGA device and writes data command to indicate to have data to be written the first memory, and writes data command according to sending second to CPU from the confirmation signal that the FPGA device receives.The CPU is also used to after the FPGA device loads second logic and enumerates successfully, the third load, which is sent, to the BMC completes signal, and data command is write according to receive from BMC described second, second logic is written in Xiang Suoshu first memory.The FPGA device is also used to write data command according to described first, disconnect the data channel between the fpga chip and the second memory, the data channel between the fpga chip and the first memory is connected, and sends confirmation signal to the BMC after switching is completed.
When the first memory is provided with write-protect, the BMC is also used to complete signal according to the third load received, and Xiang Suoshu FPGA device sends write-protect out code.The FPGA device is also used to close the write-protect of the first memory according to the write-protect out code, and switches and send the confirmation signal to the BMC after completion and write-protect are closed.
In a concrete implementation, above-mentioned read-write controller can be Complex Programmable Logic Devices (complex programmable logic device, CPLD), above-mentioned multiplexer then can be Serial Peripheral Interface (SPI) multiplexer (Serial Peripheral Interface Multiplexer, SPI MUX), and above-mentioned data channel can be the channel SPI, first memory and second memory can be flash memory (Flash Memory).
Above-mentioned BMC and CPU can be from non-volatile memory device reading program to realize above-mentioned function.Due to
CPLD is a kind of editable logical device, can realize above-mentioned function by editing logic therein.
The embodiment of the invention also provides a kind of methods of the logic in recovery fpga chip.This method is applied in the server in Fig. 2.Just as mentioned above, the initial p CI e static logic of chain of command publication is stored in initial stage, first memory Flash A and second memory FlashB.Also, in the initial stage, SIP MUX can save modified logic for user with the channel the SPI connection between Flash B, such F l ashB.And SPI MUX is closed with the channel SPI between Flash A, user can not access.In order to preferably guarantee that user can not arbitrarily write data in FlashA, BMC can issue a command to CPLD, and instruction CPLD opens the write-protect of FlashA.In this way, can not just write data to FlashA.If user is in need, the logic of FPGA can be modified and modified PCIe static logic is written in Flash B.At this point, what is stored in Flash B is no longer initial p CIe static logic but the modified PCIe static logic of user.As shown in Figure 3.Method provided in this embodiment includes the following steps:
302, CPU call FPGA driver and PCIe driver, find fpga chip and write data command to fpga chip transmission by the channel PCIe, data to be written are carried in the data command.Here data can be aforementioned customer-furnished PCIe static logic, be also possible to the PCIe static logic provided by chain of command.In practical applications, it may be necessary to by repeatedly writing data command, PCIe static logic could be all written in fpga chip.
304, after fpga chip receives data write instruction, by the data buffer storage received in storage equipment, for example, in bipolar read-only memory (bipolar read only memory, BROM), after the data in BROM reach a certain amount, control logic in fpga chip writes data into the data in the BROM in Flash B by the channel in the channel SPI and SIP MUX and Flash B between fpga chip and SPI MUX.After the data received are all written in Flash B, fpga chip returns to an interruption to CPU.After CPU receives interruption, the rest part of PCIe static logic is written in Flash B successively by this method.
306, when needing to load the PCIe static logic in Flash, CPU sends load instruction to FPGA by the channel PCIe.Wherein, the logic in load instruction in instruction fpga chip load Flash.Due to the initial stage, SIP MUX is connected to the channel SPI between Flash B, so, the logic in namely FlashB is loaded herein, that is, updated PCI e static logic.
It in order to distinguish update is initiated by Client-initiated or chain of command, can also include the instruction information for referring to initiator in load instruction.After indicating that PCI e static logic is completed in CPU load, it is to continue with the non-PCIe static logic of load
After 308, FPGA receive the load instruction, (general-purpose input/output, GPIO) interface is exported by universal input and sends a reading signal to CPLD.
After 310, CPLD receive the reading signal, load signal is sent to fpga chip by triggering program B pin.The load signal is used to indicate the logic in fpga chip load Flash.
312, after fpga chip receives the load signal, data are loaded by the channel SPI between fpga chip and the Flash B.
Wherein, fpga chip is to be connected by SPI MUX with Flash.There is the channel SPI between fpga chip and SPI MUX, and also has the channel SPI between SPI MUX and Flash.The channel SPI between SPI MUX and Flash is to be arranged in advance.For example, in the present embodiment, initial stage, the channel SPI between SPI MUX and Flash B is in connected state.At this point, fpga chip loads modified PCI e static logic from Flash B.
314, after the completion of fpga chip is loaded from the data of Flash B, Xiang Suoshu CPU sends load and completes signal, and CPU receives execution PC I e after signal is completed in the load and enumerates.That is, CPU detection is connected by the channel PCIe and CPU
The equipment connect.In the present embodiment, if CPU scan to fpga chip is connected on CPU by the channel PCIe, illustrate that CPU can be communicated with fpga chip.
316, if CPU can't detect fpga chip, illustrates that the communication connection between CPU and fpga chip disconnects, can not continue to load non-PCIe static logic and dynamic logic.In this case, CPU transmission enumerates failure news to BMC, indicates not communicating between CPU and fpga chip described in BMC.
318, BMC enumerate failure news according to what is received, send load instruction to CPLD, instruction CPLD loads chain of command publication PCIe static logic from FlashA.
Alternatively, in step 316, it is also possible to after enumerating failure, CPU sends escape instruction to BMC, and escape instruction is used to indicate the logic namely the first logic loaded in the first memory.And in step 318, BMC is instructed to the CPLD according to the escape and is sent the load instruction.
After 320, CPLD receive the load instruction of BMC, to SPI MUX sendaisle switching command to indicate that SPI MUX switches the channel between the SPI MUX and memory.
322, SPI MUX close the channel between SPI MUX and Flash B according to the channel switching command received, and the SPI MUX is connected to the channel between Flash A.That is, the channel that the channel being connected between original SPI MUX and Flash B is closed, and closes originally between SPI MUX and Flash A is connected to.After SPI MUX, which switches, to be completed, confirmation signal is returned to CPLD to show that channel switching is completed.
324, CPLD receive the confirmation signal, and after knowing that channel switching is completed, triggering Program_B pin sends load signal to fpga chip.As above-mentioned steps 310, which is used to indicate fpga chip and loads data from Flash.
Alternatively, after CPLD receives the confirmation signal, which can also be returned into BMC, returns to the instruction reloaded from the BMC to CPU, instruction CPU is fpga chip load logic.After CPU receives the instruction reloaded, data can be loaded according to step 306-312.
Since before sending load instruction, CPLD switches channel, it is to be understood that this fpga chip load logic from Flash A.
326, fpga chip, which is received, loads the PCIe static logic that chain of command is issued from Flash A by the channel SPI between CPLD and SPI MUX and the channel between SPI MUX and Flash A.
328, after the completion of fpga chip loads the data in Flash A, load is sent to CPU and completes signal, CPU receives execution PCIe after signal is completed in the load and enumerates.
330, in the present embodiment, if CPU scan to fpga chip is connected on CPU by the channel PCIe, that is, success is enumerated, then illustrate the communication recovery between CPU and fpga chip, CPU transmission enumerates successful message to BMC.
332, BMC enumerate successful message according to what is received, send resetting instruction to CPLD, data channel is switched back into the second memory of initial connection by instruction CPLD.
Alternatively, in step 330, what CPU was sent to BMC is the instruction for restoring former connection.And in step 332, the BMC sends the resetting to FPGA according to the instruction for restoring former connection and indicates.Here former connection i.e. the connection of fpga chip and second memory.
After 334, CPLD receive the resetting instruction of BMC, to SPI MUX sendaisle switching command to instruct SPI MUX to switch the channel SPI between the SPI MUX and the first and second memories.
The channel SPI between SPI MUX and Flash A is closed according to the instruction of the switching channel received and opens the channel SPI between SPI MUX and Flash B by 336, SPI MUX.
After SPI MUX switching is completed, confirmation signal is returned to CPLD to confirm that channel switching is completed, which then returns to resetting success response to BMC.After BMC receives the resetting success response, confirmation signal is returned to CPU, confirmation signal instruction channel has switched (these steps are not shown in figure).In fact, channel has switched back into the Flash B of initial connection at this time.After this, CPU can receive the request that user reloads, or reload the logic in Flash B according to configuration automatic trigger.The process of the logic in Flash B is reloaded with reference to above-mentioned steps 306-314.When enumerating success in step 314, then illustrates that the modified PCIe static logic of user is successfully loaded fpga chip, execute step 338.If enumerating failure, continue step 316, the PCIe static logic of the chain of command publication in Flash A is loaded into fpga chip.
338, CPU the non-PCIe static logic of user is written by the channel PCIe to fpga chip, writes non-PCIe static logic and then dynamic logic is written to fpga chip by the channel PCIe.Or the non-PCIe static logic and dynamic logic of user can also be passed through the channel PCIe write-in FPGA by CPU together.In the above-described embodiment, two memories, that is, Flash A and Flash B are introduced.User modification logic Flash B is first written, and saved in Flash A be then user modification before logic.If the modified logic of user be loaded into after fpga chip enumerate it is unsuccessful, using the logic in the logic reduction fpga chip stored in Flash A.Although static logic, using the scheme of the embodiment of the present invention, can rapidly restore the logic in FPGA using the logic in Flash A because open may bring risk to user.To ensure that effective operation of FPGA.
It should be noted that, need to upgrade the logic of FGPA if it is chain of command, updated logic is also that Flash B is first written, similarly, if the updated logic of chain of command publication is loaded into after fpga chip and enumerates unsuccessful, the logic in the fast quick-recovery fpga chip of the logic stored in Flash A can also be used.Detailed process is referred to above-mentioned step 302-304 and the updated PCIe static logic of chain of command is written in Flash B.Referring next to above-mentioned steps 306-336, updated PCIe static logic in Flash B is loaded into fpga chip, if load Flash B in updated PCIe static logic after can not the channel successful enumeration PCIe, using Flash A save update before PCIe static logic restore fpga chip in logic.The difference is that then illustrating that the modified PCIe static logic of chain of command is successfully loaded fpga chip after step 314 is enumerated successfully.Later, can first by updated PCIe static logic be written Flash A in, it is to be updated after PCIe static logic write-in Flash A in and then execute step 338.Step 338 can also be first carried out, then updated PCIe static logic is written in Flash A again.Wherein, the process of updated PCIe static logic write-in Flash A is referred into Fig. 4, included the following steps.
S1, after fpga chip loads the updated PCIe static logic in Flash B and enumerates the success of the channel PCIe, CPU sends load and completes signal to BMC, has loaded success with the PCIe static logic for showing that chain of command is issued.
After S2, BMC are according to load completion signal is received, determine that the PCIe static logic of chain of command publication is loaded into the success of PFGA chip, BMC sends first to CPLD accordingly and writes data command, and instruction has data to that Flash A is written.
If first memory is provided with write-protect, BMC described herein is also used to send the instruction for closing the write-protect of the first memory to the CPLD.It can be and write data command while as the instruction for closing write-protect by first, it can also individually as the instruction for closing write-protect, the present invention be not construed as limiting for instruction with another.
S3, CPLD are received write data command after, to SPI MUX sendaisle switching command to indicate that SPI MUX switches the channel between the SPI MUX and memory.
Optionally, if CPLD also has received the instruction of write-protect closing, CPLD is sent to Flash A closes write-protect instruction.
S4, SPI MUX close the channel between SPI MUX and Flash B according to the channel switching command received,
And the SPI MUX is connected to the channel between Flash A.That is, the channel that the channel being connected between original SPI MUX and Flash B is closed, and closes originally between SPI MUX and Flash A is connected to.
S5, after the completion of the switching of channel, SPI MUX returns to confirmation signal to CPLD to confirm that channel switching is completed, and CPLD is received and sent the confirmation signal to BMC after the confirmation signal.
If CPLD also has sent the instruction for closing write-protect to Flash A in above-mentioned S3; after confirmation signal is closed in the write-protect that so CPLD etc. receives the confirmation signal for the switching completion that SPI MUX is returned and Flash A is returned, then to BMC return confirmation signal to confirm Flash A write-protect closing and channel switching completion.
S6, the BMC send second to the CPU and write data command, and data are written into Flash by instruction CPU.
S7, the CPU calls FPGA driver and PCIe driver to find fpga chip, and data command is sent to fpga chip by the channel PCIe, fpga chip is written in Flash A by the channel data in the channel SPI and SIP MUX and Flash A between fpga chip and SPI MUX.Detailed process refers to step 302-304.
It is understood that CPU can also be sent completely instruction to BMC to show that data have write after writing Flash A.At this time BMC is notified that data channel is switched back into second memory by CPLD.That is, the state of fpga chip connection second memory.
As it can be seen that the PCIe static logic that the scheme of the embodiment of the present invention may be chain of command upgrading fpga chip provides safeguard.
In other situations, it is, when user expires to the modification of FPGA or access right, when cloud service provider recycles virtual machine, it is also desirable to which the logic on fpga chip is reduced to the initial p CIe static logic of chain of command publication.In this case, BMC sends load instruction to CPLD, and instruction CPLD loads the PCIe static logic of chain of command publication from Flash A.Then, then the PCIe static logic that chain of command in Flash A is issued is loaded on fpga chip by CPLD according to the load instruction notification SPI MUX switching channel received by the channel after switching.Specific process refers to above-mentioned steps 318-328.If enumerating success in step 328, the PCIe static logic that chain of command is issued in Flash A has been loaded successfully on fpga chip.
Finally, it should be noted that the above embodiments are unfolded with the server in public cloud, and the scheme of actually above-described embodiment is not limited to public cloud, other remotely provide hardware service to being applicable in the network of user in the same old way.For example, private clound, mixed cloud etc..That is the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although the present invention is described in detail referring to the foregoing embodiments, those skilled in the art should understand that: it is still possible to modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；And these are modified or replaceed, the protection scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (18)
- A kind of method of logic in recovery fpga chip, the method is applied to FPGA device, the FPGA device includes the FGPA chip, first memory, second memory, wherein, the first memory is stored with the first logic, and second logic is stored in the second memory, and second logic is the logic after the first logical renewal, it is characterized in that, which comprisesThe FPGA device receives the first load instruction that BMC is sent, and the first load instruction, which is used to indicate, is loaded into the fpga chip for first logic；The FPGA device disconnects the data channel between the fpga chip and the second memory according to the first load instruction, connects the data channel between the fpga chip and the first memory；First logic is loaded into the fpga chip by the data channel by the FPGA device.
- The method as described in claim 1, which is characterized in that the FPGA device further includes read-write controller and multiplexer MUX, whereinThe read-write controller receives the first load instruction；The read-write controller sends first passage switching command to the MUX according to the first load instruction, and the channel switching command is used to indicate the MUX and switches data channel between the MUX and first and second memory；The MUX disconnects the data channel between the fpga chip and the second memory according to the first passage switching command, connects the data channel between the FPGA and the first memory；The read-write controller sends the first load signal to the fpga chip after channel switching is completed, and the first load signal is for triggering the fpga chip load logic；First logic is loaded into fpga chip by the fpga chip according to the first load data channel of the signal by the fpga chip and the first memory.
- Method according to claim 2, which is characterized in that the method also includes:Read-write controller receives the resetting instruction that the BMC is sent；Read-write controller indicates according to the resetting, and Xiang Suoshu multiplexer sends second channel switching command, and the channel switching command is used to indicate the MUX and switches data channel between the MUX and first and second memory；The MUX disconnects the data channel between the fpga chip and the first memory according to the second channel switching command, connects the data channel between the fpga chip and the second memory.
- Method as claimed in claim 3, which is characterized in that the method further include:The fpga chip receives the second load instruction, and sends load request signal to the read-write controller according to the second load instruction, the logic in the second load instruction instruction fpga chip load store device；The read-write controller receives the load request signal, and responds the load request signal and return to the second load signal to the fpga chip, and the second load signal is for triggering FPGA load logic；Second logic is loaded on the fpga chip according to the second load signal by the data channel between the FPGA and the second memory by the fpga chip.
- Method as claimed in claim 4, which is characterized in that first logic and second logic are PCIe static logic, the method further include:After the completion of second logic, the fpga chip sends load to CPU and completes signal, and the channel PCIe between the fpga chip and the CPU is enumerated in order to the CPU；After enumerating successfully, the fpga chip loads non-PCIe static logic and dynamic logic by the channel PCIe between the CPU.
- Method as claimed in claim 4, which is characterized in that when the first memory is provided with write-protect, the method also includes:The read-write controller receives first and writes data command; described first, which writes data command instruction, has data to that the first memory is written, and writes the instruction that data command sends third channel switching command to the multiplexer and sends closing write-protect to the first memory according to described first；The MUX disconnects the data channel between the fpga chip and second reservoir, connects the data channel between the fpga chip and the first memory according to the third channel switching command；The first memory closes write-protect according to the instruction for closing write-protect.
- Method as described in claim 2-6, which is characterized in that the read-write controller is CPLD, and the MUX is SPI MUX, and the data channel is the channel SPI.
- A kind of FPGA device, the FPGA device includes FGPA chip, first memory, second memory, read-write controller and multiplexer, wherein, the first memory is stored with the first logic, second logic is stored in the second memory, second logic is the logic after the first logical renewal, it is characterised in that:The read-write controller is for receiving the first load instruction, the first load instruction, which is used to indicate, is loaded into the fpga chip for first logic, and first passage switching command is sent to multiplexer according to the first load instruction and sends the first load signal to the fpga chip after channel switching is completed, wherein, the first passage switching command is used to indicate the MUX and switches data channel between the MUX and first and second memory, and the first load signal is for triggering the fpga chip load logic；The MUX is used to disconnect the data channel between the fpga chip and the second memory according to the first passage switching command, connect the data channel between the FPGA and the first memory；The fpga chip, for, by the data channel between the fpga chip and the first memory, first logic being loaded into fpga chip according to the first load signal.
- Equipment as claimed in claim 8, which is characterized in thatThe read-write controller is also used to receive resetting instruction, second channel switching command is sent to the multiplexer according to resetting instruction, the second channel switching command is used to indicate the MUX and switches data channel between the MUX and first and second memory；The MUX is also used to disconnect the data channel between the fpga chip and the first memory according to the second channel switching command, connect the data channel between the FPGA and the second memory.
- Equipment as claimed in claim 9, which is characterized in thatThe fpga chip sends load request signal to the read-write controller for receiving the second load instruction, according to the second load instruction, the logic in the second load instruction instruction fpga chip load store device；The read-write controller is also used to receive load request signal, and responds the load request signal and return to the second load signal to the fpga chip, and the second load signal triggers FPGA load logic；Second logic is loaded on the fpga chip according to the second load signal by the data channel between the FPGA and the second memory by the fpga chip.
- Equipment as claimed in claim 10, which is characterized in that first logic and second logic are PCIe static logic, after second logic loads successfully,The fpga chip, which is also used to send load to CPU, completes signal, and after the CPU is enumerated successfully, leads to It crosses the channel PCIe between the fpga chip and CPU and loads non-PCIe static logic and dynamic logic.
- Equipment as claimed in claim 10, when the first memory is provided with write-protect, which is characterized in thatThe read-write controller is also used to receive first and writes data command; described first, which writes data command instruction, has data to that the first memory is written, and writes the instruction that data command sends third channel switching command to the multiplexer and sends closing write-protect to the first memory according to described first；The MUX is also used to disconnect the data channel between the fpga chip and second reservoir according to the third channel switching command, connects the data channel between the fpga chip and the first memory；The first memory is also used to close write-protect according to the instruction for closing write-protect.
- A kind of computer system, the computer system includes central processing unit CPU, Baseboard Management Controller BMC and on-site programmable gate array FPGA equipment, the FPGA device includes FGPA chip, first memory, second memory, wherein, the first memory is stored with the first logic, the second logic is stored in the second memory, second logic is the logic after first logical renewal, it is characterised in that:The CPU is used for after enumerating the channel the PCIe failure between the CPU and the FPGA device, and Xiang Suoshu BMC sends escape instruction, and the escape instruction is used to indicate the logic loaded in the first memory；The BMC is used to send the first load to the FPGA device according to escape instruction and instruct, and the first load instruction, which is used to indicate, is loaded into the fpga chip for first logic；The FPGA device is for receiving the first load instruction, the data channel between the fpga chip and the second memory is disconnected according to the first load instruction, the data channel between the fpga chip and the first memory is connected, and first logic is loaded by the fpga chip by the data channel.
- Computer system as claimed in claim 13, which is characterized in thatThe FPGA device is also used to after having loaded first logic, and Xiang Suoshu CPU sends the first load and completes signal；After the CPU is also used to receive the first load completion signal, the channel PCIe between the CPU and the FPGA device is enumerated, and send the instruction for restoring former connection to the BMC after enumerating successfully；The BMC is also used to send resetting instruction to the FPGA device according to the instruction for restoring former connection；The FPGA device is also used to disconnect the data channel between the fpga chip and the first memory according to the resetting instruction, connects the data channel between the FPGA and the second memory.
- Computer system as claimed in claim 14, which is characterized in thatThe BMC is also used to receive resetting success response from the FPGA device, and sends confirmation signal to the CPU to confirm that the data channel has switched；The CPU is also used to send the second load instruction to the FPGA device according to the confirmation signal, indicates the logic in the FPGA device load store device；The FPGA device is also used to after receiving the second load instruction, and by the data channel between the FPGA and the second memory, second logic is loaded on the fpga chip.
- Computer system as claimed in claim 15, which is characterized in thatThe FPGA device is also used to after the completion of the second logic loads, and Xiang Suoshu CPU sends the second load and completes signal, and after described enumerate successfully, loads non-PCIe static logic and dynamic logic by the channel PCIe between the CPU；The CPU is also used to after receiving second load and completing signal, enumerates the channel PCIe between the FPGA device and the CPU.
- Computer architecture system as described in claim 15 or 16, which is characterized in thatThe BMC is also used to complete signal according to the third load received, first is sent to the FPGA device and writes data command to indicate to have data to be written the first memory, and writes data command according to sending second to CPU from the confirmation signal that the FPGA device receives；The CPU is also used to after the FPGA device loads second logic and enumerates successfully, the third load, which is sent, to the BMC completes signal, and data command is write according to receive from BMC described second, second logic is written in Xiang Suoshu first memory；The FPGA device is also used to write data command according to described first, disconnect the data channel between the fpga chip and the second memory, the data channel between the fpga chip and the first memory is connected, and sends confirmation signal to the BMC after switching is completed.
- Computer system as claimed in claim 17, which is characterized in that when the first memory is provided with write-protect,The BMC, which is also used to be loaded according to the third, completes signal, and Xiang Suoshu FPGA device sends write-protect out code；The FPGA device is also used to close the write-protect of the first memory, and send the confirmation signal to the BMC after switching is completed and write-protect is closed according to the write-protect out code.
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Also Published As
| Publication number | Publication date |
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| CN112486585A (en) | 2021-03-12 |
| CN110073333B (en) | 2020-11-17 |
| CN112486585B (en) | 2024-01-02 |
| WO2019084916A1 (en) | 2019-05-09 |
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