CN110071146B - Display panel and electronic device - Google Patents
Display panel and electronic device Download PDFInfo
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- CN110071146B CN110071146B CN201910279042.6A CN201910279042A CN110071146B CN 110071146 B CN110071146 B CN 110071146B CN 201910279042 A CN201910279042 A CN 201910279042A CN 110071146 B CN110071146 B CN 110071146B
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- 239000010410 layer Substances 0.000 claims abstract description 205
- 239000002184 metal Substances 0.000 claims abstract description 111
- 239000010409 thin film Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 10
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005274 electronic transitions Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a display panel and an electronic device. The display panel includes: a substrate, a thin-film transistor layer, and a light-emitting structure. The thin-film transistor layer includes a plurality of thin-film transistors, the thin-film transistors including: the buffer layer, the first active region, the second active region, the grid dielectric layer, the grid metal layer, the interlayer dielectric layer, the source region metal layer, the drain region metal layer and the planarization layer. The first active region and the second active region are positioned on the substrate, and the first active region comprises a channel region and a source region and a drain region which are positioned on two sides of the channel region; the source region metal layer is located on the interlayer dielectric layer and is electrically connected with the source region through a through hole, and the drain region metal layer is located on the interlayer dielectric layer and is electrically connected with the drain region and the second active region through a through hole. The display panel and the electronic device provided by the invention can effectively reduce the resistance of the signal line in the display panel.
Description
Technical Field
The present invention relates to the field of electronic display, and in particular, to a display panel and an electronic device.
Background
In order to reduce the influence of the capacitive coupling on the system impedance, a top gate thin film transistor is generally used as a thin film transistor layer of the display panel to reduce the load of the signal line. But the resistance of the signal line becomes non-negligible for a large-sized or ultra-large-sized display. The resistor consumes the power supply voltage, resulting in uneven brightness of the display panel.
Therefore, it is necessary to provide a tft structure capable of eliminating the voltage drop of the signal line.
Disclosure of Invention
The invention provides a display panel and an electronic device, which can effectively reduce the resistance of a signal line in the display panel.
To solve the above problems, the present invention provides a display panel, which includes:
a substrate;
a thin-film transistor layer on the substrate;
a light emitting structure on the thin film transistor layer; wherein,
the thin-film transistor layer includes a plurality of thin-film transistors, the thin-film transistors including:
a buffer layer on the substrate;
the first active region and the second active region are positioned on the substrate, and the first active region comprises a channel region, a source region and a drain region which are positioned on two sides of the channel region;
a gate dielectric layer covering the first active region;
the grid metal layer covers the grid dielectric layer positioned above the first active region;
the interlayer dielectric layer covers the grid metal layer;
the source region metal layer is positioned on the interlayer dielectric layer and is electrically connected with the source region through a through hole;
the drain region metal layer is positioned on the interlayer dielectric layer and is electrically connected with the drain region and the second active region through a through hole;
and the planarization layer covers the source region metal layer, the drain region metal layer and the interlayer dielectric layer.
According to one aspect of the present invention, the light emitting structure includes a light emitting material layer, a projection of which on the substrate does not coincide with the first and second active regions.
According to one aspect of the invention, the first active region and the second active region are electrically isolated.
According to one aspect of the present invention, the plurality of thin film transistors are distributed in an array, and include at least one row of thin film transistors arranged along a first direction and at least one column of thin film transistors arranged along a second direction; wherein,
the second active regions of the plurality of thin film transistors in the same row are electrically connected, and the second active regions of the plurality of thin film transistors in the same column are electrically insulated.
According to one aspect of the present invention, the display panel further includes a first metal layer and a second metal layer between the substrate and the buffer layer, the first metal layer and the second metal layer being electrically insulated from each other.
According to one aspect of the present invention, the first metal layer and the second metal layer are light-shielding metal layers.
According to one aspect of the invention, a projection of the first metal layer on the buffer layer covers a projection of the first active region on the buffer layer, and a projection of the second metal layer on the buffer layer covers a projection of the second active region on the buffer layer.
According to one aspect of the present invention, a surface of the light-shielding metal layer adjacent to the substrate has a uniformly distributed diffuse reflection structure.
According to one aspect of the present invention, a surface of the light-shielding metal layer adjacent to the substrate has a uniformly undulating wave-shaped structure.
Correspondingly, the invention also provides an electronic device which comprises the display panel.
According to the invention, the first active region and the second active region are arranged in the buffer layer in the thin film transistor, and the second active region is connected with the source region wiring layer through the through hole, so that the area of metal wiring is effectively increased, the resistance of a signal wire is reduced, and the voltage drop on the signal wire is effectively avoided. Meanwhile, the invention also provides a first metal layer and a second metal layer which are positioned below the first active region and the second active region. The first metal layer and the second metal layer are light-shading metal layers, so that the resistance of the signal line can be further reduced, and meanwhile, external light is prevented from being emitted into the active region, and therefore threshold voltage drift is avoided.
Drawings
FIG. 1 is a schematic cross-sectional view of a prior art display panel;
FIG. 2 is a schematic cross-sectional view of a display panel in an embodiment of the invention;
FIG. 3 is a top view of a partial trace of a display panel according to an embodiment of the invention;
fig. 4 is a schematic cross-sectional view of a display panel in another embodiment of the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The prior art will first be briefly described. Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a display panel in the related art. The display panel includes: substrate 112, a thin-film transistor layer, and a light-emitting structure.
The thin-film transistor layer is located on the substrate 112 and includes a plurality of thin-film transistors. Each of the thin film transistors includes: a buffer layer 116, the buffer layer 116 being located on the substrate 112; an active region located on the buffer layer 116, the active region including a channel region 120 and a source region 122 and a drain region 124 located at two sides of the channel region 120; a gate dielectric layer 130, wherein the gate dielectric layer 130 covers the active region; a gate metal layer 140, wherein the gate metal layer 140 covers the gate dielectric layer 130 located above the active region; an interlayer dielectric layer 150, wherein the interlayer dielectric layer 150 covers the gate metal layer 140; the source drain metal layer is positioned on the interlayer dielectric layer 150; and the planarization layer 170, wherein the planarization layer 170 covers the source drain metal layer and the interlayer dielectric layer 150.
The light-emitting structure is located on the thin film transistor layer. The light emitting structure includes an anode 182, a pixel defining layer 190, a light emitting material layer 184, and a cathode 186.
The anode 182 is located on the planarization layer 170 and electrically connected to the source-drain metal layer 160 through a via; the pixel defining layer 190 is on the planarization layer 172 and has a through hole exposing the anode 182; the layer of light emitting material 184 is located on the anode 182; the cathode 186 covers the light emitting material layer 184.
Referring to fig. 1, in the prior art, resistance of a source-drain metal layer is not negligible for a large-size or ultra-large-size display. The resistor consumes the power supply voltage, resulting in uneven brightness of the display panel.
In view of the above problems, the present invention provides a display panel and an electronic device, which can effectively reduce the resistance of a signal line in the display panel. Referring to fig. 2 and 3, fig. 2 is a schematic cross-sectional view of a display panel in an embodiment of the invention, and fig. 3 is a top view of a local trace of the display panel in an embodiment of the invention.
In this embodiment, the display panel is an Organic Light Emitting Diode (OLED) display panel. In other embodiments of the present invention, the display panel may also be a liquid crystal display panel or other types of display panels.
Referring to fig. 2, the display panel includes: substrate 112, a thin-film transistor layer, and a light-emitting structure.
The substrate 112 may be a rigid substrate or a flexible substrate. Rigid substrates include glass, metal, etc., and flexible substrates can be various polymers, such as polyimide.
The thin film transistor layer is located on the substrate 112 and includes a plurality of thin film transistors, and the thin film transistors include: buffer layer 116, first active region 12, second active region 126, gate dielectric layer 130, gate metal layer 140, interlayer dielectric layer 150, source region metal layer 164, drain region metal layer 162, and planarization layer 170.
In this embodiment, the first active region 12 is electrically isolated from the second active region 126.
The first active region 12 covers the buffer layer 116 over the first metal layer 114, and the first active region 12 includes a channel region 120 and source and drain regions 122 and 124 on both sides of the channel region 120.
The second active region 126 is disposed adjacent to the first active region 12, and the second active region 126 is located under the drain region metal layer 162.
The projection of the second active region 126 on the buffer layer 116 covers the projection of the drain metal layer 162 on the buffer layer 116. Preferably, the shape and area of the second active region 126 are the same as those of the drain region metal layer 162. This provides two advantages, on one hand, since the second active region 126 and the drain region metal layer 162 have the same shape, they can be formed by the same mask, thereby reducing the manufacturing cost. On the other hand, the second active region 126 and the drain region metal layer 162 correspond in position and shape, and projections of the second active region 126 and the drain region metal layer 162 on the buffer layer 116 are overlapped, so that positions of through holes for realizing electrical connection between the second active region and the drain region metal layer can be arbitrarily set according to actual conditions, and process implementation is facilitated.
Referring to fig. 3, fig. 3 is a top view of a partial trace of a display panel according to an embodiment of the invention. The area a of fig. 2 where the second active region 126 is located is a corresponding cross-sectional view of the area a of fig. 3. As shown in fig. 3, in this embodiment, the plurality of thin film transistors are distributed in an array shape, and include at least one row of thin film transistors arranged along a first direction and at least one column of thin film transistors arranged along a second direction. The second active regions 126 in the plurality of thin film transistors in the same row are electrically connected, and the second active regions 126 in the plurality of thin film transistors in the same column are electrically insulated.
Referring to fig. 4, in another embodiment of the present invention, in order to further reduce the resistance of the source region metal layer 164 and the drain region metal layer 162, a first metal layer 114 and a second metal layer 118 are further disposed in the thin film transistor. The first metal layer 114 and the second metal layer 118 are located on the substrate 112. In this embodiment, the first metal layer 114 and the second metal layer 118 are electrically isolated from each other.
The projection of the first metal layer 114 on the buffer layer 116 covers the projection of the active region on the buffer layer 116. Preferably, the area of the first metal layer 114 is greater than or equal to the sum of the area of the active region and the area of the source region metal layer 164. This arrangement enables the source region metal layer 164 to be electrically connected to the first metal layer 114 through a via hole, thereby increasing the area of the source region metal layer 164 and thus reducing the resistance of the source region metal layer 164.
The projection of the second metal layer 118 on the buffer layer 116 covers the projection of the drain metal layer 162 on the buffer layer 116. Preferably, the second metal layer 118 has the same shape and area as the drain metal layer 162. This provides two benefits, on one hand, since the second metal layer 118 and the drain region metal layer 162 have the same shape, they can be formed by the same mask, thereby reducing the production cost. On the other hand, the second metal layer 118 and the drain region metal layer 162 are corresponding in position and shape, and projections of the second metal layer and the drain region metal layer 162 on the buffer layer 116 are overlapped, so that positions of through holes for realizing electrical connection between the second metal layer and the drain region metal layer can be set at will according to actual conditions, and process implementation is facilitated.
In this embodiment, the first metal layer 114 and the second metal layer 118 are light-shielding metal layers. The shading metal layer can effectively prevent external light from entering the active region, and effectively inhibits the electronic transition of the active region. For the amorphous silicon thin film transistor, the shading metal layer can greatly enhance the stability of the thin film transistor.
Preferably, the surfaces of the first metal layer 114 and the second metal layer 118 adjacent to the substrate 112 have uniformly distributed diffuse reflection structures, and the diffuse reflection structures may be granular frosted surfaces. In other embodiments, it is preferable that the surface of the light-shielding metal layer adjacent to the substrate 112 has a uniformly undulating wave structure. The diffuse reflection structure and the wave-shaped structure can diffuse and absorb light, and further enhance the shading effect of the first metal layer 114 and the second metal layer 118.
In this embodiment, as shown in fig. 2, the source region metal layer 164 is located on the interlayer dielectric layer 150 and electrically connected to the source region 122 through a via. The drain region metal layer 162 is located on the interlayer dielectric layer 150 and electrically connected to the drain region 124 and the second active region 142 through a via hole.
In this embodiment, the planarization layer 170 covers the source region metal layer 164, the drain region metal layer 162 and the interlayer dielectric layer 150.
In this embodiment, the light emitting structure is located on the thin film transistor layer. The light emitting structure includes an anode 182, a pixel defining layer 190, a light emitting material layer 184, and a cathode 186. The anode 182 is located on the planarization layer 170 and electrically connected to the source-drain metal layer 160 through a via; the pixel defining layer 190 is on the planarization layer 172 and has a through hole exposing the anode 182; the layer of light emitting material 184 is located on the anode 182; the cathode 186 covers the light emitting material layer 184.
In this embodiment, in order to avoid the metal traces from affecting the light emitting effect of the display panel, the projection of the light emitting material layer on the substrate 112 is not overlapped with the first active region 12 and the second active region 126.
Correspondingly, the invention also provides an electronic device which comprises the display panel.
According to the invention, the first active region and the second active region are arranged in the buffer layer in the thin film transistor, and the second active region is connected with the source region wiring layer through the through hole, so that the area of metal wiring is effectively increased, the resistance of a signal wire is reduced, and the voltage drop on the signal wire is effectively avoided. Meanwhile, the invention also provides a first metal layer and a second metal layer which are positioned below the first active region and the second active region. The first metal layer and the second metal layer are light-shading metal layers, so that the resistance of the signal line can be further reduced, and meanwhile, external light is prevented from being emitted into the active region, and therefore threshold voltage drift is avoided.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (7)
1. A display panel, comprising:
a substrate;
a thin-film transistor layer on the substrate;
a light emitting structure on the thin film transistor layer; wherein,
the thin-film transistor layer includes a plurality of thin-film transistors, the thin-film transistors including:
a buffer layer on the substrate;
the first metal layer and the second metal layer are positioned between the substrate and the buffer layer and are electrically insulated, and the first metal layer and the second metal layer are shading metal layers;
the first active region and the second active region are positioned on the substrate and comprise a channel region, and a source region and a drain region which are positioned on two sides of the channel region, wherein the projection of the first metal layer on the buffer layer covers the projection of the first active region on the buffer layer, and the projection of the second metal layer on the buffer layer covers the projection of the second active region on the buffer layer;
a gate dielectric layer covering the first active region;
the grid metal layer covers the grid dielectric layer positioned above the first active region;
the interlayer dielectric layer covers the grid metal layer;
the source region metal layer is positioned on the interlayer dielectric layer and is electrically connected with the source region through a through hole;
the drain region metal layer is positioned on the interlayer dielectric layer and is electrically connected with the drain region and the second active region through a through hole;
and the planarization layer covers the source region metal layer, the drain region metal layer and the interlayer dielectric layer.
2. The display panel of claim 1, wherein the light emitting structure comprises a layer of light emitting material, a projection of the layer of light emitting material on the substrate being non-coincident with the first and second active regions.
3. The display panel according to claim 1, wherein the first active region and the second active region are electrically insulated from each other.
4. The display panel according to claim 1, wherein the plurality of thin film transistors are distributed in an array, and include at least one row of thin film transistors arranged in a first direction and at least one column of thin film transistors arranged in a second direction; wherein,
the second active regions of the plurality of thin film transistors in the same row are electrically connected, and the second active regions of the plurality of thin film transistors in the same column are electrically insulated.
5. The display panel according to claim 1, wherein a surface of the light-shielding metal layer adjacent to the substrate has a uniformly distributed diffuse reflection structure.
6. The display panel according to claim 5, wherein a surface of the light-shielding metal layer adjacent to the substrate has a uniformly undulating wave structure.
7. An electronic device characterized in that the electronic device comprises the display panel of any one of claims 1-6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910279042.6A CN110071146B (en) | 2019-04-09 | 2019-04-09 | Display panel and electronic device |
| PCT/CN2019/085525 WO2020206772A1 (en) | 2019-04-09 | 2019-05-05 | Display panel and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910279042.6A CN110071146B (en) | 2019-04-09 | 2019-04-09 | Display panel and electronic device |
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| CN110071146A CN110071146A (en) | 2019-07-30 |
| CN110071146B true CN110071146B (en) | 2021-02-02 |
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| CN110854137B (en) * | 2019-11-22 | 2022-12-02 | 京东方科技集团股份有限公司 | Display panel, array substrate and manufacturing method thereof |
| CN113497076A (en) * | 2020-04-01 | 2021-10-12 | 深圳市柔宇科技有限公司 | Display panel and electronic device |
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| TW586144B (en) * | 2002-11-15 | 2004-05-01 | Toppoly Optoelectronics Corp | Method of forming a liquid crystal display |
| CN109545836B (en) * | 2018-12-13 | 2021-01-01 | 武汉华星光电半导体显示技术有限公司 | OLED display device and manufacturing method thereof |
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- 2019-04-09 CN CN201910279042.6A patent/CN110071146B/en active Active
- 2019-05-05 WO PCT/CN2019/085525 patent/WO2020206772A1/en active Application Filing
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| CN110071146A (en) | 2019-07-30 |
| WO2020206772A1 (en) | 2020-10-15 |
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