CN110034592B

CN110034592B - Power stage circuit with charge current reduction

Info

Publication number: CN110034592B
Application number: CN201810027971.3A
Authority: CN
Inventors: 杨曜玮
Original assignee: Elite Semiconductor Memory Technology Inc
Current assignee: Elite Semiconductor Memory Technology Inc
Priority date: 2018-01-11
Filing date: 2018-01-11
Publication date: 2022-02-11
Anticipated expiration: 2038-01-11
Also published as: CN110034592A

Abstract

The invention provides a power stage circuit, which comprises a plurality of high-side metal oxide semiconductor field effect transistors and a control circuit. The first end of each high-side metal oxide semiconductor field effect transistor is electrically connected to a power supply, and the second ends of the high-side metal oxide semiconductor field effect transistors are electrically connected with each other to generate an output signal. The control circuit is electrically connected to the gate terminal of each high-side metal oxide semiconductor field effect transistor, and the control circuit conducts the high-side metal oxide semiconductor field effect transistors in any sequence to reduce the charging current when the high-side metal oxide semiconductor field effect transistors are conducted, so that the power consumption is reduced, and the service life of the high-side metal oxide semiconductor field effect transistors is prolonged.

Description

Power stage circuit with charge current reduction

Technical Field

The present invention relates to a power stage circuit, and more particularly, to a power stage circuit with reduced charging current.

Background

Referring to fig. 1A, fig. 1A is a schematic diagram of a high-side metal-oxide-semiconductor field-effect transistor (high-side MOSFET) of a conventional power stage circuit. High-side metal oxide semiconductor field effect transistor M_HSDue to the inherent Gate-Source capacitance C between the Gate terminal (Gate) and the Source terminal (Source)_GSAnd a gate-Drain inherent capacitance C is provided between the gate terminal and the Drain terminal (Drain)_GD. As shown in FIG. 1B, the high side MOSFET M_HSGate source voltage V during conduction_GSFirst break through the critical voltage V_THThen, the gate source intrinsic capacitance C is attached_GSAnd gate drain inherent capacitance C_GDAre charged simultaneously (charging interval A) and then at a voltage V_SPThe gate-drain inherent capacitance C is set at the nearby charging interval B_GDCharging, wherein the voltage variation is gradually gentle, and then the gate-source voltage V_GSIt rises significantly again (charging interval C). Generally, in order to provide a large current to the power stage circuit, a large high-side mosfet M is used_HSSo that the gate-drain inherent capacitance C_GDAnd will increase accordingly. While on the high side the metal oxide semiconductor field effect transistor M_HSDuring the charging process, due to the inherent capacitance C of the gate-drain of the charging region B_GDThe charging time is dependent on the gate-drain inherent capacitance C_GDIs increased so that the high-side metal oxide semiconductor field effect transistor M_HSA large current i is consumed during the conduction process_G。

Thus, there is an improved circuit of FIG. 2A that provides two high-side MOSFETs M_HS1、M_HS2By leading one of the high-side metal oxide semiconductor field effect transistors M to be turned on_HS1So that the charging interval B is only for the high-side MOSFET M_HS1Gate-drain inherent capacitance C_GD1Charging, at the high side of the MOSFET M_HS1After the conduction, the high-side metal oxide semiconductor field effect transistor M is continuously conducted_HS2At this time, the source terminal voltage SW is already due to the high-side MOSFET M_HS1Is pulled to the potential of the power source HVin close to the drain terminal, so that the high-side metal oxide semiconductor field effect transistor M_HS2The conduction process does not need to have the inherent capacitance C of the gate and drain_GD2Charging, i.e. high-side MOSFET M_HS2The conduction process of (2) does not need to pass through the charging interval B, so that under the condition of the same current requirement, the current consumed in the conduction process (the current I of figure 2B) can be saved_G1、I_G2Will be compared to fig. 1_BCurrent of (I)_GSmall). However, the transistors that are turned on first during each turn-on process may have large losses, which may shorten the service life of the circuit.

Disclosure of Invention

Embodiments of the present invention provide a power stage circuit to reduce the charging current when a high-side mosfet is turned on, thereby reducing power consumption and prolonging the lifetime of the high-side mosfet.

The embodiment of the invention provides a power stage circuit, which comprises a plurality of high-side metal oxide semiconductor field effect transistors and a control circuit. Each high-side MOSFET has a first terminal and a second terminal. The first end of each high-side metal oxide semiconductor field effect transistor is electrically connected to a power supply, and the second ends of the high-side metal oxide semiconductor field effect transistors are electrically connected with each other to generate an output signal. The control circuit is electrically connected to the gate terminal of each high-side metal oxide semiconductor field effect transistor, and the control circuit conducts the high-side metal oxide semiconductor field effect transistors in any sequence.

In summary, the embodiments of the present invention provide a power stage circuit for reducing the charging current of a high-side mosfet, which can reduce the total current consumed in the switching process by turning on any one high-side mosfet first, and the high-side mosfets turned on first each time may not be the same, so that the probability (or frequency) of turning on each of a plurality of high-side mosfets can be set (or controlled) to be approximately the same, thereby prolonging the service life of the power stage circuit.

For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for illustration purposes only and are not intended to limit the scope of the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.

Fig. 1A is a diagram of a high-side mosfet of a conventional power stage circuit.

FIG. 1B is a waveform diagram of the voltage and current at turn-on of the high-side MOSFET of FIG. 1A.

Fig. 2A is a diagram of a high-side mosfet of a conventional power stage circuit.

FIG. 2B is a waveform diagram of the voltage and current at turn-on of the high-side MOSFET of FIG. 2A.

Fig. 3 is a circuit diagram of a high-side mosfet of a power stage circuit and a related control circuit thereof according to an embodiment of the invention.

Fig. 4 is a circuit diagram of the selectively conducting cell of fig. 3.

Fig. 5 is a circuit diagram of the logical operation unit of fig. 3.

Fig. 6 is a waveform diagram of the voltage and current when the high-side mosfet of the power stage circuit is turned on according to the embodiment of the invention.

Fig. 7 is a voltage waveform diagram of the high side mosfet of the power stage circuit according to the present invention during the successive high side conduction process.

[ List of reference numerals ]

BS and SW: voltage of

I_G、I_G0、I_G1、I_G2、I_G3: electric current

HVin: power supply

C_GS、C_GD、C_GS0、C_GD0、C_GS1、C_GD1、C_GS2、C_GD2、C_GS3、C_GD3: capacitor with a capacitor element

M_HS、M_HS0、M_HS1、M_HS2、M_HS3: high-side metal oxide semiconductor field effect transistor

V_TH、V_SP、V_TH1、V_SP1、V_GS、V_GS1、V_GS2、V_DS、V_GS0、V_GS3: voltage of

A. B, C: charging interval

100. 110, 120, 130: driving circuit

14: selective conduction unit

145: counter with a memory

140. 141, 142, 143, 154: and gate

15: logical operation unit

151. 152: NOR gate

153: NAND gate

101. 111, 121, 131: drive amplifier

102. 112, 122, 132: OR gate

V_GH0、V_GH1、V_GH2、V_GH3: first on signal

And (5) SecdC: second on signal

HSC: high side pilot signal

Detailed Description

Embodiments of Power stage circuits

According to the conventional circuit shown in fig. 2A, when there are a plurality of high-side MOSFETs, only one of the high-side MOSFETs is turned on, so that the current consumed in turning on the transistors can be reduced, but the transistors turned on first in each turn-on process are the same, so that the transistors turned on first may have a larger loss and a shorter lifetime. In view of this problem, the present embodiment provides a power stage circuit, which turns on the high-side mosfets in any order by way of circuit design. The related control circuit portion of the present embodiment does not refer to a transistor switch circuit designed according to the power output requirement of the general power stage circuit itself, and the control circuit portion of the present embodiment does not affect the original operation mode of the power stage circuit.

Referring to fig. 3, fig. 3 is a circuit diagram of a high-side mosfet of a power stage circuit and a related control circuit thereof according to an embodiment of the invention. In the embodiment of fig. 3, the number of the high-side mosfets is four, but the invention is not limited thereto. The number of high-side mosfets may be two, three, five or more, according to the same principle.

The power stage circuit of this embodiment includes a plurality of high-side MOSFETs M_HS0、M_HS1、M_HS2、M_HS3And a corresponding control circuit. Generally, the power stage circuit may further include a low side MOSFET (low side MOSFET) whose switching is complementary to the high side MOSFET, and the operation of the power stage circuit will be understood by those skilled in the art and will not be described herein. Each of the high-side mosfets of the present embodiment has the opportunity to be selectively turned on first, and then the other high-side mosfets are turned on. Meanwhile, when the power stage circuit of the present embodiment operates, the high-side mosfet turned on first at each time may be different.

Each high side metal oxide semiconductor field effect transistor (M)_HS0Or M_HS1Or M_HS2Or M_HS3) Is electrically connected to a power supply HVin, the high side mosfet (M)_HS0、M_HS1、M_HS2、M_HS3) The second terminals are electrically connected to each other (voltage SW) for generating the output signal. A control circuit electrically connected to each high-side MOSFET M_HS0、M_HS1、M_HS2、M_HS3A Gate terminal (Gate) of the control circuit, the control circuit turns on the high side metal oxide semiconductor field effect transistor M in any order_HS0、M_HS1、M_HS2、M_HS3. For a detailed implementation of the control circuit, reference is made to the following further description.

Before describing the details of the control circuit of the present embodiment, the operation of the power stage circuit will be briefly described. In the operation procedure of the power stage circuit, the process of turning on all the high-side mosfets may be referred to as a high-side turning-on procedure, and the high-side turning-on procedure (when there is a low-side mosfet, the low-side mosfet is turned on after each high-side turning-on procedure) is performed successively during the operation procedure of the power stage circuit, for example, the control is performed according to a pulse width modulation method, but the invention is not limited thereto. According to the design requirements of the power stage circuit, those skilled in the art can design the required circuit according to the prior art, and will not be described in detail.

The first terminal of the high-side mosfet is a Drain terminal (Drain) and the second terminal of the high-side mosfet is a Source terminal (Source). High-side metal oxide semiconductor field effect transistor M_HS0Between the gate terminal and the source terminal of the transistor has a gate-source intrinsic capacitance C_GS0High-side MOSFET M_HS0The gate terminal and the drain terminal have a gate-drain inherent capacitance C_GD0. High-side metal oxide semiconductor field effect transistor M_HS1Between the gate terminal and the source terminal of the transistor has a gate-source intrinsic capacitance C_GS1High-side MOSFET M_HS1The gate terminal and the drain terminal have a gate-drain inherent capacitance C_GD1. High-side metal oxide semiconductor field effect transistor M_HS2Between the gate terminal and the source terminal of the transistor has a gate-source intrinsic capacitance C_GS2High-side MOSFET M_HS2The gate terminal and the drain terminal have a gate-drain inherent capacitance C_GD2. High side metal oxide semiconductor field effectTransistor M_HS3Between the gate terminal and the source terminal of the transistor has a gate-source intrinsic capacitance C_GS3High-side MOSFET M_HS3The gate terminal and the drain terminal have a gate-drain inherent capacitance C_GD3。

Referring to fig. 3 again, the control circuit includes, for example, a plurality of driving circuits (in fig. 3, four driving

circuits

100, 110, 120, and 130 are taken as an example), a selective turn-on unit 14, and a logic operation unit 15. Each of the driving

circuits

100, 110, 120 or 130 is electrically connected to the corresponding high-side mosfet M_HS0、M_HS1、M_HS2Or M_HS3Is used as the door extreme.

Each driver circuit (100, 110, 120 OR 130) includes a driver amplifier (101, 111, 121 OR 131) and an OR gate (OR) (102, 112, 122 OR 132). The driving amplifier (101, 111, 121 or 131) is electrically connected to the gate terminal of the corresponding high-side MOSFET for driving the corresponding high-side MOSFET (M)_HS0、M_HS1、M_HS2Or M_HS3). In detail, the driving

amplifiers

101, 111, 121, 131 are connected to the voltages BS, SW and provide driving to the corresponding high-side MOSFETs M_HS0、M_HS1、M_HS2、M_HS3Current of gate terminal I_G0、I_G1、I_G2、I_G3。

The output terminal of the or gate 102 is electrically connected to the driving amplifier 101. The OR gate 102 turns on the first signal V_GH0Performing a logical OR operation with the second conducting signal SecdC, and turning on the corresponding high-side MOSFET M of the corresponding driver amplifier 101 when the logical OR operation result is true_HS0. Similarly, the OR gate 112 will turn on the first signal V_GH1Performing a logical OR operation with the second conducting signal SecdC, and turning on the corresponding high-side MOSFET M of the corresponding driver amplifier 111 when the logical OR operation result is true_HS1. Similarly, the OR gate 122 will turn on the first signal V_GH2And the second conducting signal SecdC, and when the logical OR operation result is true, the corresponding driving amplifier 121 is conducted to the corresponding high-side metal oxide semiconductorField effect transistor M_HS2. Similarly, the OR gate 132 will turn on the first signal V_GH3Performing a logical OR operation with the second conducting signal SecdC, and turning on the corresponding high-side MOSFET M of the driver amplifier 131 when the logical OR operation result is true_HS3。

The selective turn-on unit 14 has four output terminals for respectively outputting four first turn-on signals V corresponding to the four driving

circuits

100, 110, 120, 130_GH0、V_GH1、V_GH2、V_GH3. In detail, the selective conducting unit 14 is electrically connected to the driving

circuits

100, 110, 120, and 130 through the output terminal to generate a first conducting signal V_GH0、V_GH1、V_GH2、V_GH3First on signal V_GH0Corresponding driving circuit 100 and high-side MOSFET M_HS0First on signal V_GH1Corresponding driving circuit 110 and high-side MOSFET M_HS1First on signal V_GH2Corresponding driving circuit 120 and high-side MOSFET M_HS2First on signal V_GH3Corresponding driving circuit 130 and high-side MOSFET M_HS3. Each time the high-side metal oxide semiconductor field effect transistor is to be conducted, the first conducting signal can be different and can be V_GH0、V_GH1、V_GH2、V_GH3One of them. First on signal V_GH0Or V_GH1Or V_GH2Or V_GH3For controlling the first conducting signal V_GH0Or V_GH1Or V_GH2Or V_GH3The

corresponding driving circuit

100 or 110 or 120 or 130 turns on the corresponding high-side MOSFET M_HS0Or M_HS1Or M_HS2Or M_HS3. That is, the first conducting signal V is utilized by the selective conducting unit 14_GH0Or V_GH1Or V_GH2Or V_GH3First-on high-side metal oxide semiconductor field effect transistor M_HS0、M_HS1、M_HS2、M_HS3Of the above-mentioned substrate.

It should be noted that, in fig. 3, the selective conducting unit 14 further hasAn input terminal for receiving the second conducting signal SecdC, but the invention is not limited thereto. The second conducting signal SecdC received by the selective conducting unit 14 of fig. 3 is used to change the first conducting signal V output by the selective conducting unit 14_GH0、V_GH1、V_GH2Or is V_GH3. That is, the second turn-on signal SecdC in fig. 3 is used to change the state of the first turn-on signal generated by the selective turn-on unit 14 next time. However, the present invention does not limit how the selectively conducting unit 14 changes the state of the first conducting signal, and the selectively conducting unit 14 may automatically change the next generated first conducting signal from its inside, or the selectively conducting unit 14 may change the next generated first conducting signal according to other signals.

The logic operation unit 15 is electrically connected to the high-side MOSFET M_HS0、M_HS1、M_HS2、M_HS3Gate terminal of and on the high side of the MOSFET M_HS0、M_HS1、M_HS2、M_HS3First turned on high side MOSFET M_HS0Or M_HS1Or M_HS2Or M_HS3Voltage V of gate terminal_GS0Or V_GS1Or V_GS2Or V_GS3When a set value is exceeded (described in further detail below), a second turn-on signal SecdC is generated and transmitted to the driving

circuits

100, 110, 120, and 130, so that other high-side mosfets are turned on. That is, the present embodiment has four high-side MOSFETs M_HS0、M_HS1、M_HS2、M_HS3In the case of when the high-side MOSFET M_HS0Is turned on first, and other high-side metal oxide semiconductor field effect transistors M_HS1、M_HS2、M_HS3And subsequently turned on. When the high-side metal oxide semiconductor field effect transistor M_HS1Is turned on first, and other high-side metal oxide semiconductor field effect transistors M_HS0、M_HS2、M_HS3And subsequently turned on. When the high-side metal oxide semiconductor field effect transistor M_HS2Is turned on first, and other high-side metal oxide semiconductor field effect transistors M_HS0、M_HS1、M_HS3And subsequently turned on.When the high-side metal oxide semiconductor field effect transistor M_HS3Is turned on first, and other high-side metal oxide semiconductor field effect transistors M_HS0、M_HS1、M_HS2And subsequently turned on.

In other words, the control circuit of the present embodiment is applied to the high-side mosfet M_HS0、M_HS1、M_HS2、M_HS3Until the gate-source voltage of the charged high-side MOSFET is greater than a set value, then the gate terminals of the other MOSFETs are charged. In practical implementation, the high-side mosfet that is turned on first passes through the charging interval B shown in fig. 1B and fig. 2B, and then the other high-side mosfets are turned on subsequently. According to the charging interval B, the triggering second conducting signal SecdC is used to conduct other high-side metal oxide semiconductor field effect transistors in the following period, and the first conducted high-side metal oxide semiconductor field effect transistor M_HS0Or M_HS1Or M_HS2Or M_HS3The set value of the voltage at the gate terminal of (1) may be, for example, a voltage V larger than that of FIG. 1B_SP(or the voltage V of FIG. 2B_SP1) Said voltage V being_SPIs larger than the inherent capacitance C of the gate drain_GDGate source voltage V during charging_GS. That is, the set value can be set to be greater than the gate-source voltage V in the charging interval B_GS. For example, when the first high-side MOSFET M is turned on_HS0Or M_HS1Or M_HS2Or M_HS3Voltage V of gate terminal_GS0Or V_GS1Or V_GS2Or V_GS3Over voltage V_SPThen, a second turn-on signal SecdC is generated and transmitted to the driving

circuits

100, 110, 120, and 130, so that other high-side mosfets that are not turned on are turned on.

How to turn on the high-side MOSFET M in an arbitrary order_HS0、M_HS1、M_HS2、M_HS3. Ideally, each high-side mosfet is shared equally among the first-to-turn-on operations. In this embodiment, a selectively conducting unit (e.g., including a counter) is utilized to conductSequentially generating the MOS transistors M corresponding to the high-side MOS transistors respectively_HS0、M_HS1、M_HS2、M_HS3Of one of the first conduction signals V_GH0、V_GH1、V_GH2、V_GH3The high-side MOSFETs turned on first by the control circuit are different in the successive high-side conduction process, whereby the high-side MOSFETs are turned on first approximately the same number of times in the successive high-side conduction process.

Furthermore, in the embodiment, the first conducting signal V generated by the control circuit_GH0、V_GH1、V_GH2、V_GH3Not only for leading through the high side metal oxide semiconductor field effect transistor M_HS0、M_HS1、M_HS2、M_HS3Any one of them, and the voltage (V) of the gate terminal of the first-turned-on high-side MOSFET_GS0、V_GS1VGS2 or V_GS3) For turning on other high-side mosfets. For example, when the high-side MOSFET M_HS0First conducted high side metal oxide semiconductor field effect transistor M_HS0Voltage V of gate terminal_GS0For turning on other high-side metal oxide semiconductor field effect transistor M_HS1、M_HS2、M_HS3. When the high-side metal oxide semiconductor field effect transistor M_HS1First conducted high side metal oxide semiconductor field effect transistor M_HS1Voltage V of gate terminal_GS1For turning on other high-side metal oxide semiconductor field effect transistor M_HS0、M_HS1、M_HS3And so on.

Please refer to fig. 3 and fig. 4 simultaneously. Fig. 4 is a circuit diagram of the selectively conducting cell of fig. 3. The selective turn-on unit 14 includes a counter 145 AND a plurality of AND gates (AND), in fig. 4, four AND

gates

140, 141, 142, 143. The counter 145 sequentially generates the MOS transistors M corresponding to the high-side MOSFETs M_HS0、M_HS1、M_HS2、M_HS3The count signal of one of them. The counter 145 counts each time the second turn-on signal SecdC is received and changes the count signal, thereby changing the pair of the first turn-on signalsThe high side mosfet. The AND

gates

140, 141, 142, 143 are electrically connected to the counter 145, the AND

gates

140, 141, 142, 143 correspond to the driving

circuits

100, 110, 120, 130 one-to-one, AND each of the AND

gates

140, 141, 142, or 143 is used for performing a logical AND operation on the count signal AND the high side conducting signal HSC to generate the first conducting signal V_GH0Or V_GH1Or V_GH2Or V_GH3And the first conducting signal V is used_GH0Or V_GH1Or V_GH2Or V_GH3Output to the

corresponding driving circuit

100 or 110 or 120 or 130. It should be noted that the high side conduction signal HSC is a signal for controlling the turn-on of the high side mosfet by the transistor switch circuit of the general power stage circuit, and the high side conduction signal HSC can be controlled by a commonly used pulse width modulation signal, for example, that is, the high side conduction signal HSC is used to trigger the high side conduction procedure and inform the control circuit of the embodiment to let all the high side mosfets M pass through_HS0、M_HS1、M_HS2、M_HS3All are turned on.

Referring to fig. 3 and 5, fig. 5 is a circuit diagram of the logical operation unit of fig. 3. The logical operation unit 15 of fig. 3 may be replaced with various logic circuits, and the present invention is not limited thereto. The logic operation unit 15 can let any high-side metal oxide semiconductor field effect transistor M_HS0、M_HS1、M_HS2、M_HS3Voltage V of gate terminal_GS0、V_GS1、V_GS2、V_GS3When True (True) and the high side conduction signal HSC is True (True), the second conduction signal SecdC is generated. In FIG. 5, when the voltage V is applied_GS0、V_GS1When any one of the two is true, the NOR gate (NOR)151 outputs NO (False), and when the voltage V is true_GS2、V_GS3When either is true, the NOR gate (NOR)152 outputs no (False). The outputs of the NOR gate (NOR)151 and NOR gate (NOR)152 are connected to the inputs of a NAND gate (NAND) 153. One input terminal of the and gate 154 receives the high side conducting signal HSC, the other input terminal of the and gate 154 is connected to the output terminal of the nand gate 153, and the output terminal of the and gate 154 outputs the second conducting signal SecdC.

Please refer to simultaneouslyFig. 3 and 6 are diagrams illustrating waveforms of voltage and current when the high-side mosfet of the power stage circuit is turned on according to the embodiment of the present invention. According to the circuit of FIG. 3, a high-side MOSFET M_HS0、M_HS1、M_HS2、M_HS3Any one of them may be turned on, for example, when the high-side MOSFET M_HS0Is first turned on, and the voltage V at the gate terminal is shown in FIG. 6_GS0First rising and then turning on other high-side metal oxide semiconductor field effect transistors M_HS1、M_HS2、M_HS3。

Fig. 3 and fig. 7 are voltage waveforms of the high-side mosfet of the power stage circuit according to the embodiment of the invention during the successive high-side conduction process. In each high-side conduction process, the first turned-on high-side mosfet may be different, as shown in fig. 7, and in the first turn-on shown at the leftmost side, the first turned-on high-side mosfet M is turned on_HS0. According to the circuits of fig. 3 and 4, the count signal generated by the counter 145 of the conducting unit 14 is selected to correspondingly generate the first conducting signal V_GH0So that the first turned on is the high-side MOSFET M_HS0Voltage V at gate terminal_GS0First rising, then the logic operation unit 15 is operated by the voltage V_GS0Trigger (voltage exceeds the set value) to generate the second conducting signal SecdC to conduct other high-side MOSFET M_HS1、M_HS2、M_HS3. Accordingly, the counter 145 of fig. 4 receives the second turn-on signal SecdC, so that the counter 145 counts to change the count signal, which corresponds to the first turn-on signal V_GH1. Then, when conducting for the second time, the high-side metal oxide semiconductor field effect transistor M is firstly conducted_HS1Voltage V at gate terminal_GS1First rising, voltage V_GS1For triggering and turning on other high-side metal oxide semiconductor field effect transistors M_HS0、M_HS2、M_HS3Then the first on signal is changed to V_GH2. Then, when conducting for the third time, the high side metal oxide semiconductor field effect transistor M is conducted first_HS2At the extreme of the doorVoltage V_GS2First rising, voltage V_GS2For triggering and turning on other high-side metal oxide semiconductor field effect transistors M_HS0、M_HS1、M_HS3Then the first on signal is changed to V_GH3. Then, when conducting for the fourth time, the high side metal oxide semiconductor field effect transistor M is conducted first_HS3Voltage V at gate terminal_GS3Rise, voltage V_GS3For triggering and turning on other high-side metal oxide semiconductor field effect transistors M_HS0、M_HS1、M_HS2. However, the above-mentioned sequence of turning on the first high-side mosfet may be changed, and the invention is not limited thereto.

Advantageous effects of the embodiments

In summary, the power stage circuit provided in the embodiments of the present invention is configured to reduce the charging current of the high-side mosfets, and reduce the total current consumed in the switching process by turning on any one of the high-side mosfets, and the high-side mosfets turned on first each time may not be the same, so that the probability (or the number of times) that each of the plurality of high-side mosfets is turned on first can be set (or controlled) to be approximately the same by using, for example, a counter, thereby prolonging the service life of the power stage circuit.

The above description is only an example of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A power stage circuit, comprising:

a plurality of high-side MOSFETs, each of the high-side MOSFETs having a first end and a second end, the first end of each of the high-side MOSFETs being electrically connected to a power source, the second ends of the high-side MOSFETs being electrically connected to each other for generating an output signal; and

the control circuit is electrically connected to the gate terminal of each high-side metal oxide semiconductor field effect transistor, and the control circuit firstly conducts any one of the high-side metal oxide semiconductor field effect transistors until the gate-source voltage of the high-side metal oxide semiconductor field effect transistor which is firstly conducted is larger than a set value, and then conducts the other high-side metal oxide semiconductor field effect transistors.

2. The power stage circuit of claim 1, wherein the control circuit generates a first turn-on signal to turn on any one of the high-side mosfets first, and the voltage at the gate terminal of the high-side mosfet that is turned on first is used to turn on the other high-side mosfets.

3. The power stage circuit of claim 2, wherein the process of turning on all of the high-side mosfets is a high-side turning-on process, and the high-side turning-on process is performed sequentially during the operation of the power stage circuit, wherein the control circuit uses a counter to sequentially generate the first turn-on signals respectively corresponding to one of the high-side mosfets, so that the high-side mosfets turned on first by the control circuit are different in the sequential high-side turning-on process, whereby the number of times the high-side mosfets are turned on first in the sequential high-side turning-on process is approximately the same.

4. The power stage circuit of claim 1, wherein the first terminal of the high side mosfet is a drain terminal, the second terminal of the high side mosfet is a source terminal, each high side mosfet has a gate-source intrinsic capacitance between the gate terminal and the source terminal, and each high side mosfet has a gate-drain intrinsic capacitance between the gate terminal and the drain terminal.

5. The power stage of claim 4, wherein the control circuit charges the gate of one of the MOSFETs until the gate-source voltage of the high-side MOSFET that was charged is greater than a predetermined value, followed by charging the gate of the other MOSFETs.

6. The power stage circuit of claim 1, wherein the control circuit comprises:

a plurality of driving circuits, each of which is electrically connected to the gate terminal of the corresponding high-side mosfet;

the selective conduction unit is electrically connected with the drive circuits and generates a first conduction signal so as to control the drive circuit corresponding to the first conduction signal to conduct the corresponding high-side metal oxide semiconductor field effect transistor; and

and the logic operation unit is electrically connected with the gate terminals of the high-side metal oxide semiconductor field effect transistors, and generates and transmits a second conduction signal to the driving circuits when the voltage of the gate terminal of the first conducted high-side metal oxide semiconductor field effect transistor in the high-side metal oxide semiconductor field effect transistors exceeds a set value so as to conduct other high-side metal oxide semiconductor field effect transistors.

7. The power stage circuit of claim 6, wherein the selectively conducting unit comprises:

a counter for sequentially generating a count signal corresponding to each of the high-side MOSFETs; and

AND the AND gates (ANDs) are electrically connected with the counters AND correspond to the driving circuits in a one-to-one mode, AND each AND gate is used for performing logic AND operation on the counting signal AND the high-side conducting signal to generate the first conducting signal AND outputting the first conducting signal to the corresponding driving circuit.

8. The power stage circuit of claim 7, wherein the counter receives the second turn-on signal to count to change the count signal, thereby changing the high-side MOSFET corresponding to the first turn-on signal.

9. The power stage circuit of claim 6, wherein the driver circuit comprises:

the driving amplifier is electrically connected with the gate terminal of the corresponding high-side metal oxide semiconductor field effect transistor and used for driving the corresponding high-side metal oxide semiconductor field effect transistor; and

and the output end of the OR gate is electrically connected with the drive amplifier, the OR gate performs logical OR operation on the first conducting signal and the second conducting signal, and the corresponding drive amplifier is conducted with the corresponding high-side metal oxide semiconductor field effect transistor when the logical OR operation result is true.