CN119364876A

CN119364876A - Front-illuminated photodiode structure, preparation method thereof and X-ray detector

Info

Publication number: CN119364876A
Application number: CN202411425326.9A
Authority: CN
Inventors: 李荐民; 陈志强; 李元景; 张丽; 李玉兰
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2024-10-12
Filing date: 2024-10-12
Publication date: 2025-01-24

Abstract

The application discloses a front-illuminated photodiode structure, a preparation method thereof and an X-ray detector, and belongs to the field of semiconductor photoelectric sensors in nuclear technology application. The front-illuminated photodiode structure comprises a substrate, an antireflection film, an electrode lead and a through-silicon-hole structure, wherein the substrate comprises an epitaxial layer, the epitaxial layer comprises an electrode area located on the photosensitive side of the epitaxial layer, the antireflection film is located on the photosensitive side of the epitaxial layer, the electrode lead is located on one side, away from the epitaxial layer, of the antireflection film and penetrates through the antireflection film to be connected with the electrode area, and the through-silicon-hole structure penetrates through the substrate and the antireflection film and is connected with the electrode lead. The application can simultaneously ensure the quantum efficiency and the rapid time response of the photodiode, is suitable for large-size process lines, and realizes the splicing of the periphery.

Description

Front-illuminated photodiode structure, preparation method thereof and X-ray detector

Technical Field

The application belongs to the field of semiconductor sensors applied to nuclear technology, and particularly relates to a front-illuminated photodiode structure, a preparation method and an X-ray detector.

Background

At present, a back-illuminated photodiode for X-ray detection is mainly produced by using a 6-inch wafer special production line, and after an electrode pad of the back-illuminated photodiode is formed, the back surface of the 6-inch wafer needs to be thinned, and then the subsequent process is continued. The size of the 6-inch wafer is smaller, the mechanical strength after thinning is not greatly influenced, and the breaking risk is lower. However, as the size of the wafer increases (e.g., 8 inches or 12 inches), the mechanical strength of the thinned wafer is poorer and poorer, and the risk of breaking the wafer is greatly increased, so that the wafer cannot be subjected to subsequent processes after being thinned. In addition, current back-illuminated photodiodes for X-ray detection are limited by mechanical strength, typically ranging in thickness from 50-200um, and slow minority carrier drift velocity limits the time response performance of the photodiode.

Disclosure of Invention

The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the front-illuminated photodiode structure, the preparation method and the X-ray detector provided by the application can ensure the response time of the photodiode, reduce the fragmentation risk, are suitable for large-size process lines, and realize that the periphery can be spliced.

In a first aspect, the present application provides a front-lit photodiode structure comprising:

a substrate comprising an epitaxial layer, the epitaxial layer comprising an electrode region on a photosensitive side of the epitaxial layer;

An antireflection film positioned on the photosensitive side of the epitaxial layer;

The electrode lead is positioned at one side of the antireflection film, which is away from the epitaxial layer, and penetrates through the antireflection film to be connected with the electrode area;

and the silicon through hole structure penetrates through the substrate and the antireflection film and is connected with the electrode lead.

According to one embodiment of the application, the peripheral side surface of the front-illuminated photodiode structure is a splice-able surface.

According to one embodiment of the present application, the electrode region includes a highly doped region having a doping type different from that of the epitaxial layer, and the electrode lead includes a lead connected to the highly doped region;

The epitaxial layer further comprises a floating doped region which is positioned on the photosensitive side of the epitaxial layer, the floating doped region is different from the epitaxial layer in doping type, and the floating doped region is positioned at the bottom of the lead and is transversely arranged at intervals with the electrode region and the through silicon via structure.

According to one embodiment of the application, the through silicon via structure comprises a conductive layer and a spacing layer, wherein the conductive layer penetrates through the substrate and the transparent enhancement layer and is connected with the electrode lead, and the spacing layer is arranged around the conductive layer. According to one embodiment of the application, the base further comprises a substrate;

the substrate is positioned on one side of the epitaxial layer, which is away from the antireflection film.

According to one embodiment of the application, the substrate is a P-type or N-type substrate and the epitaxial layer is an N-type epitaxial layer.

According to one embodiment of the present application, the front-illuminated photodiode structure further includes:

the dielectric layer is positioned at one side of the substrate away from the antireflection film;

the bonding pad is positioned on one side of the dielectric layer, which is away from the substrate;

the silicon through hole structure is connected with the bonding pad through the dielectric layer, or the bonding pad is connected with the silicon through hole structure through the dielectric layer.

And a protective layer covering the electrode leads.

According to one embodiment of the application, the epitaxial layer has a resistance of 500-1500ohm, and/or,

The thickness of the epitaxial layer is 5-15 mu m.

In a second aspect, the present application provides an X-ray detector comprising a front-lit photodiode structure as described in the first aspect.

According to one embodiment of the application, the X-ray detector comprises a plurality of the front-illuminated photodiode structures spliced together.

In a third aspect, the present application provides a method for manufacturing a front-illuminated photodiode structure, including:

Providing a substrate and an antireflection film, wherein the substrate comprises an epitaxial layer, the epitaxial layer comprises an electrode area positioned on a photosensitive side, and the antireflection film is positioned on the photosensitive side of the epitaxial layer;

forming an electrode lead on one side of the antireflection film, which is away from the substrate, and connecting the electrode lead with the electrode area by penetrating through the antireflection film;

Temporarily bonding a carrier sheet and one side of the electrode lead away from the antireflection film;

Thinning one side of the substrate, which is away from the antireflection film;

Debonding the carrier sheet from a side of the electrode lead facing away from the anti-reflection film;

the method further comprises the steps of:

and forming a through silicon via structure, wherein the through silicon via structure penetrates through the thinned substrate and the antireflection film and is connected with the electrode lead. According to one embodiment of the application, the substrate is a 12 inch or 8 inch wafer.

According to one embodiment of the application, the substrate further comprises a substrate positioned on one side of the epitaxial layer away from the antireflection film;

the thinning treatment of the side of the substrate facing away from the antireflection film comprises the following steps:

thinning one side of the substrate away from the epitaxial layer;

The forming of the through silicon via structure comprises:

And after the thinning treatment is carried out on one side of the substrate, which is far away from the antireflection film, forming a silicon through hole structure penetrating through the thinned substrate, the epitaxial layer and the antireflection film.

The forming of the through silicon via structure comprises:

before an electrode lead is formed on one side of the antireflection film, which is away from the base, a through silicon via structure penetrating through the antireflection film and the epitaxial layer and extending into the substrate is formed;

and thinning the side, away from the epitaxial layer, of the substrate to expose the through silicon via structure.

According to one embodiment of the application, before the temporary bonding of the carrier sheet to the side of the electrode lead facing away from the anti-reflection film, the method further comprises:

And forming a protective layer covering the electrode leads.

According to one embodiment of the application, the method further comprises:

forming a dielectric layer on one side of the substrate, which is away from the antireflection film, and forming a bonding pad on one side of the dielectric layer, which is away from the substrate;

The above technical solutions in the embodiments of the present application have at least one of the following technical effects:

After the slide glass and the electrode lead wire are temporarily bonded on one side, deviating from the antireflection film, of the substrate are subjected to thinning treatment, so that the mechanical strength of the substrate is increased, the quantum efficiency and the rapid time response of the photodiode are ensured, the breaking risk of the substrate after thinning is reduced, the front-illuminated photodiode structure can be produced on a large-size process line, namely, the front-illuminated photodiode structure is suitable for the large-size process line, the production efficiency is improved, the production cost is reduced, and the electrode of the front-illuminated photodiode is led out to the non-photosensitive side of the substrate through the through-silicon-hole structure, so that the peripheral side of the front-illuminated photodiode structure can be spliced, and the front-illuminated photodiode structure is suitable for pixel arrays with any size.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic flow chart of a method for manufacturing a front-illuminated photodiode structure according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a method for manufacturing a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 3 is a second schematic diagram of a method for fabricating a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 4 is a third schematic diagram of a manufacturing method of a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 10 is a second flow chart of a method for fabricating a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 12 is a diagram illustrating a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 13 is a schematic diagram of a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 14 is a diagram illustrating an eleventh embodiment of a method for fabricating a front-illuminated photodiode structure according to the present application;

FIG. 15 is a schematic diagram of a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 16 is a second schematic diagram of a front-illuminated photodiode structure according to an embodiment of the present application, and FIG. 17 is a third schematic diagram of a front-illuminated photodiode structure according to an embodiment of the present application;

FIG. 18 is a graph showing junction capacitance and depletion region width versus epitaxial layer resistance for a front-illuminated photodiode structure according to an embodiment of the present application;

fig. 19 is a graph showing the relationship between the wavelength of incident light and the internal quantum efficiency of the front-illuminated photodiode structure according to the embodiment of the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.

The front-illuminated photodiode structure, the manufacturing method and the X-ray detector provided by the embodiment of the application are described below with reference to the accompanying drawings.

Fig. 1 is a schematic flow chart of a method for manufacturing a front-illuminated photodiode structure according to an embodiment of the present application. The front-illuminated photodiode is a front-illuminated photodiode based on a CMOS process, and can be applied to an X-ray detector, which is a front-illuminated detector.

In the case where the front-illuminated photodiode in the present embodiment is applied to an X-ray detector, the front-illuminated photodiode is used to convert a visible light signal (the scintillator converts an X-ray signal into a visible light signal) into an electrical signal, and the electrical signal is output to a data processing and control circuit after being processed by an ADC (analog-to-digital converter).

The working principle of the front-illuminated photodiode is that when light (visible light signal) with a certain wavelength is incident into an epitaxial layer (such as silicon) and photon energy is larger than a band gap Eg of silicon (for silicon, the wavelength is smaller than 1100 nm), electrons in a valence band absorb photon energy and transition to a conduction band to form an electron-hole pair. When electron-hole pairs are generated in the depletion region of the PN junction, the electrons and the holes are separated under the action of a built-in electric field, and photocurrent is formed if a circuit outside the PN junction forms a loop. When electron-hole pairs are generated outside the depletion region of the PN junction, if the minority carrier lifetime in the corresponding region is sufficiently long, the minority carriers in the electron-hole pairs can diffuse into the depletion region and be collected to form photocurrent.

The embodiment of the application provides a preparation method of a front-illuminated photodiode structure, which comprises the following steps:

forming an electrode lead on one side of the antireflection film, which is away from the substrate, and connecting the electrode lead with the electrode area through the antireflection film;

Temporarily bonding a slide glass and one side of an electrode lead away from the antireflection film;

Thinning the side of the substrate away from the antireflection film;

debonding the slide from a side of the electrode lead facing away from the anti-reflection film;

The method further comprises the steps of:

And forming a through silicon via structure, wherein the through silicon via structure penetrates through the thinned substrate and the antireflection film and is connected with the electrode lead.

The step of forming the through silicon via structure may be located after the step of thinning the side of the substrate facing away from the anti-reflection film, or may be located before the step of forming the electrode lead on the side of the anti-reflection film facing away from the substrate, so as to ensure that the through silicon via structure leads out the electrode of the photodiode to the non-photosensitive side, so that the peripheral side of the front-illuminated photodiode structure can be spliced.

As shown in fig. 1, an embodiment of the present application provides a method for manufacturing a front-illuminated photodiode structure, which includes steps 110, 120, 130, 140, 150 and 160.

Step 110, providing a substrate and an antireflection film, wherein the substrate comprises an epitaxial layer, the epitaxial layer comprises an electrode area positioned on a photosensitive side, and the antireflection film is positioned on the photosensitive side of the epitaxial layer.

In some embodiments, the substrate is a wafer with a size greater than 6 inches, such as a commercially available 12 inch or 8 inch wafer. The present embodiment may be applicable to large-scale wafer processing lines, i.e., the present embodiment may be produced on large-scale wafer processing lines, such as 12-inch wafer CMOS processing lines.

The related art adopts a special 6-inch wafer production line to produce the back-illuminated photodiode for X-ray detection, and the special production line can adopt a customized machine for each process and research and develop a special process scheme. However, large-size wafer process lines (e.g., 12-inch wafer CMOS process lines) are currently the mainstream semiconductor general-purpose production lines, and are mainly characterized by being compatible with the production of various types of chips, such as digital chips, analog chips, memory chips, power management chips, and the like. Compared with a special wire, the process has better process stability, more supported process types and lower production cost. However, there are many more restrictions and considerations on the process, including sharing of tools for different products, compatibility of process capabilities with different products, etc.

For the foundry, as the wafer size increases, the time and cost increase required to process a single wafer is much smaller than the area increase, so the larger the wafer size, the lower the average to unit area time and process costs. Meanwhile, the size of the X-ray detector is large (in centimeter level), and the area utilization rate of the large-size wafer is higher. Compared with a plurality of common chips, the area utilization rate of the 12-inch wafer is 7% -14% higher than that of the 6-inch wafer, and the average cost per unit area of the chips is further reduced. In terms of process control capability, the annual output of a 12-inch wafer CMOS process line (generally >1 ten thousand pieces/month) is far higher than that of a 6-inch and 8-inch line, so that the data volume for Statistical Process Control (SPC) is larger, and the process fluctuation trend can be better mastered, and the control capability on process stability is stronger. In addition, the 12-inch wafer CMOS process line has more process types and smaller minimum line width of the photoetching process, can meet the research and development requirements of the current photoelectric sensor and the integration of the follow-up photoelectric sensor and the analog-to-digital chip, for example, the photoetching line width is smaller (1 μm), can meet the optimization requirement of an anode structure, has Atomic Layer Deposition (ALD) capability (film thickness change is less than 0.5 nm), supports the research of high-uniformity antireflection films, is used for the groove etching/epitaxy process of stress engineering, can support the research of novel photodiode structures and the like.

The embodiment prepares the front-illuminated photodiode based on the large-size wafer process line, improves the production efficiency, reduces the production cost and provides the process stability compared with the 6-inch wafer process line.

As shown in connection with fig. 2, a substrate 10 is provided, the substrate 10 may comprise an epitaxial layer 1. In some embodiments, the base 10 may further include a substrate 13, i.e., the epitaxial layer 1 is formed on the substrate 13 by a thin film deposition process. The thin film deposition process comprises physical vapor deposition, chemical vapor deposition, atomic layer deposition or laser-assisted deposition and the like.

The doping type of the epitaxial layer 1 is different or the same as that of the substrate 13. In some embodiments, epitaxial layer 1 may be an N-type epitaxial layer and substrate 13 may be a P-type or N-type substrate.

The production of the special line with 6 inches does not need to consider the problem of mutual pollution caused by sharing a machine with other products, and the commercial CMOS process line (12 inches or 8 inches) commonly uses the P-type wafer. Photodiodes for X-ray detection need to be produced using N-type wafers. When the wafer is subjected to a high temperature process, the internal doping elements diffuse into the chamber and adhere to the inside of the chamber. The common machine for the N-type and P-type wafers on the large-size process line can cause pollution problems (such as diffusion of residual N-type doping elements in the chamber into the P-type epitaxy and vice versa), and cause problems of poor wafer yield, difficulty in factory control, frequent cleaning of the chamber, increased cost and the like. Based on the above, the embodiment grows the N-type epitaxial layer on the P-type substrate, avoids the pollution to a large-size (such as 12 inches) process line, and meets the N-type epitaxial requirement of the X-ray detector.

Then, the photosensitive side of the epitaxial layer 1 is doped by an ion implantation process, and activated using high-temperature annealing, and the electrode region 11 is formed on the photosensitive side of the epitaxial layer 1. The electrode region 11 may include a first highly doped region 111 having a doping type different from that of the epitaxial layer 1 and a second highly doped region 112 having the same doping type as that of the epitaxial layer 1. For example, the first highly doped region 111 is a P-type highly doped region, and the second highly doped region 112 is an N-type highly doped region. The second highly doped region 112 and the first highly doped region 111 are both located on the photosensitive side of the epitaxial layer 1, and the second highly doped region 112 is laterally spaced from the first highly doped region 111. One of the second highly doped region 112 and the first highly doped region 111 is an anode, and the other is a cathode.

It should be noted that, the doping types of the first highly doped region 111 and the second highly doped region 112 are different, and two photomasks are required to form the first highly doped region 111 and the second highly doped region 112 respectively. The order in which the first highly doped region 111 and the second highly doped region 112 are formed is not particularly limited.

Then, an antireflection film 2 is formed on the photosensitive side of the epitaxial layer 1 by a thin film deposition process. The thickness of the antireflection film 2 is fixed and thin, for example, the thickness of the antireflection film 2 may be less than 100nm.

And 120, forming an electrode lead on one side of the antireflection film, which is away from the substrate, and connecting the electrode lead with the electrode area through the antireflection film.

Two through holes are formed in the anti-reflection film 2 through an etching process, and the two through holes correspond to the positions of the first high doped region 111 and the second high doped region 112 respectively, so as to expose the first high doped region 111 and the second high doped region 112.

Then, a metal layer is formed on one side of the antireflection film 2, which is away from the epitaxial layer 1, by a thin film deposition process, and the metal layer fills two through holes, and contacts the first highly doped region 111 and the second highly doped region 112 respectively, so as to form a low-resistance contact. As shown in fig. 3, the metal layer is etched by an etching process to form the electrode lead 3. Wherein the electrode lead 3 includes a first lead 31 connected to the first highly doped region 111 and a second lead 32 connected to the second highly doped region 112, and the first lead 31 and the second lead 32 are laterally spaced apart.

In some embodiments, the method further includes forming a protective layer covering the electrode lead prior to temporarily bonding the carrier sheet to the side of the electrode lead facing away from the anti-reflection film in step 130.

As shown in fig. 4, a protective layer 7 covering the electrode leads 3 is formed using a thin film deposition process. The protective layer 7 serves to protect the electrode lead 3. It should be noted that, the protective layer of the photosensitive area needs to be removed, only the antireflection film is reserved, and the light transmittance is ensured.

It should be noted that the above process is completed based on a large-size wafer CMOS production line, and the subsequent process may be completed by a packaging factory. The structure completed by the CMOS production line is a wafer structure, and the wafer structure comprises a plurality of front-illuminated photodiode chips. The wafer structure may then be diced into individual back-illuminated photodiode chips.

And 130, temporarily bonding the carrier sheet and one side of the electrode lead away from the antireflection film.

As shown in connection with fig. 5, the side of the protective layer 7 facing away from the substrate 10 and the surface of the carrier sheet 9 are coated with a bonding medium 8. The carrier sheet 9 is then bonded to the side of the protective layer 7 facing away from the substrate 10 by means of the bonding medium 8.

The thickness of the large-size wafer is thicker, for example, the thickness of a 12-inch wafer is generally 775 mu m, when the wafer is directly thinned to about 100 mu m, the wafer breaking risk is extremely high, and the excessively thin wafer cannot be identified in part of the machine, is difficult to normally transfer into the machine and transfer among different machines, so that the selection range of the subsequent process is limited.

Based on this, the front surface of the substrate 10 is bonded with the carrier 9, and then a subsequent thinning process is performed, so that the mechanical strength of the substrate is increased, the quantum efficiency and the rapid time response of the photodiode are ensured, and the risk of breaking the chip is reduced, so that the method is suitable for a large-size process line. In addition, for the front-illuminated photodiode structure, the subsequent substrate 10 is not required to be reduced to be too thin, and only the TSV (through silicon via) process is required to be met, so that permanent bonding is not required, temporary bonding is only required before the back surface process is performed on the substrate 10, the mechanical strength of the substrate 10 is increased, and the subsequent process requirement is met.

And 140, thinning the side of the substrate away from the antireflection film.

In the case where the substrate 10 includes the epitaxial layer 1, the side of the epitaxial layer 1 facing away from the antireflection film 2 is subjected to thinning treatment. After thinning, the thickness of the epitaxial layer 1 meets the TSV process requirement, for example, the thickness of the epitaxial layer 1 is 200 μm.

In the case where the base 10 comprises the epitaxial layer 1 and the substrate 13, the thinning of the side of the base facing away from the anti-reflection film in step 130 comprises thinning of the side of the substrate facing away from the epitaxial layer.

As shown in connection with fig. 6, the side of the substrate 13 facing away from the epitaxial layer 1 is subjected to a thinning process. After thinning, the total thickness of the substrate 13 and the epitaxial layer 1 meets the TSV process requirement, for example, the total thickness of the substrate 13 and the epitaxial layer 1 is 200 μm. After the thinning treatment is performed on the side of the substrate facing away from the antireflection film in step 140, the preparation method of the front-illuminated photodiode structure further includes:

and 141, forming a through silicon via structure penetrating the thinned substrate and the antireflection film, wherein the through silicon via structure is connected with the electrode lead.

And forming a through silicon via structure penetrating through the thinned substrate, the epitaxial layer and the antireflection film under the condition that the base further comprises the substrate.

In some embodiments, before forming the through-silicon via structure penetrating the thinned substrate and the anti-reflection film in step 141, the method for fabricating the front-illuminated photodiode structure further includes forming a dielectric layer on a side of the substrate facing away from the anti-reflection film, wherein the through-silicon via structure also penetrates the dielectric layer.

As shown in fig. 7, a thin film deposition process is used to form a dielectric layer 6 on the side of the substrate 10 facing away from the anti-reflection film 2. Then, at least two through silicon vias are formed through the dielectric layer 6, the thinned substrate 10 and the antireflection film 2 by etching process, so as to expose the electrode lead 3, and the two through silicon vias expose the first lead 31 and the second lead 32 respectively. A thin film deposition process is used to form spacer layers 44 on the sidewalls of the two through-silicon vias, and then fill the conductive layers 43 in the two through-silicon vias, thereby forming the through-silicon via structure 4.

The through-silicon via structure 4 comprises a first through-silicon via sub-structure 41 and a second through-silicon via sub-structure 42, which are located in two through-silicon vias, respectively. The first through-silicon via substructure 41 longitudinally penetrates the dielectric layer 6, the substrate 10 and the anti-reflection film 2 and is connected to the first highly doped region 111 by the lead 31. The second through-silicon via substructure 42 longitudinally penetrates the dielectric layer 6, the substrate 10 and the anti-reflection film 2 and is connected to the second highly doped region 112 by the leads 32.

The spacer 44 between the conductive layer 43 and the epitaxial layer 1 in this embodiment can reduce parasitic capacitance formed between the conductive layer 43 and the epitaxial layer 1.

In some embodiments, prior to debonding the carrier sheet from the side of the electrode lead facing away from the anti-reflection film in step 150, the method further includes forming a pad on the side of the dielectric layer facing away from the substrate, and the pad is connected to the through-silicon via structure.

As shown in connection with fig. 8, a pad 5 is formed on the side of the dielectric layer 6 facing away from the substrate 10 using a thin film deposition process. The pad 5 may include a first pad 51 and a second pad 52 disposed at a lateral interval. The first and second pads 51 and 52 are correspondingly connected to the first and second leads 31 and 32 through the first and second through-silicon-via sub-structures 41 and 42, respectively, so that the anode and cathode of the front-illuminated photodiode are led out to the non-photosensitive side of the substrate 10, so that the peripheral side of the front-illuminated photodiode structure is a splice-able surface.

Under the condition that the cross section of the front-illumination type photodiode structure is rectangular, four side faces of the front-illumination type photodiode structure are all spliced faces. The front-illuminated photodiodes can be spliced to form pixel arrays with any size, and are suitable for various application scenes, such as security inspection, industrial detection, medical imaging and the like.

And 150, debonding the carrier sheet and one side of the electrode lead away from the antireflection film.

As shown in fig. 9, after the back side process is completed, the carrier 9 and the side of the protective layer 7 facing away from the substrate 10 are unbuckled by means of unbuckling according to the bonding medium used, so that the front-illuminated photodiode structure is separated from the carrier 9. The de-bonding mode comprises UV light irradiation, mechanical stripping, laser stripping and the like.

As shown in fig. 10, the embodiment of the application further provides a method for manufacturing a front-illuminated photodiode structure, which includes steps 110, 111, 120, 130, 140 and 150.

As shown in connection with fig. 2, a substrate 10 is provided, the substrate 10 may comprise an epitaxial layer 1. In some embodiments, the base 10 may further include a substrate 13, and the epitaxial layer 1 is formed on the substrate 13.

Then, the photosensitive side of the epitaxial layer 1 is doped by an ion implantation process, and the electrode region 11 is formed on the photosensitive side of the epitaxial layer 1. The electrode region 11 may include a first highly doped region 111 having a doping type different from that of the epitaxial layer 1 and a second highly doped region 112 having the same doping type as that of the epitaxial layer 1. One of the second highly doped region 112 and the first highly doped region 111 is an anode, and the other is a cathode.

Then, an antireflection film 2 is formed on the photosensitive side of the epitaxial layer 1. The thickness of the antireflection film 2 is fixed and thin, for example, the thickness of the antireflection film 2 may be less than 100nm.

Step 111, forming a through silicon via structure penetrating the anti-reflection film and extending into the substrate.

In the case where the base 10 includes the substrate 13 and the epitaxial layer 1, the through-silicon via structure penetrates the antireflection film 2 and the epitaxial layer 1 and extends into the substrate 13. At least two through silicon vias are formed by an etching process, the through silicon vias penetrating the anti-reflection film 2 and the epitaxial layer 1 and extending into the substrate 13. Two through silicon vias are disposed adjacent to the first highly doped region 111 and the second highly doped region 112, respectively. As shown in fig. 11, a thin film deposition process is used to form spacers 44 on the sidewalls and bottom of the two through-silicon vias, and then fill the conductive layer 43 in the two through-silicon vias, thereby forming the through-silicon via structure 4.

The through-silicon via structure 4 comprises a first through-silicon via sub-structure 41 and a second through-silicon via sub-structure 42, which are located in two through-silicon vias, respectively. The first through-silicon via substructure 41 extends longitudinally through the anti-reflection film 2 and the epitaxial layer 1 into the substrate 13, and the second through-silicon via substructure 42 extends longitudinally through the anti-reflection film 2 and the epitaxial layer 1 into the substrate 13.

And 120, forming an electrode lead on one side of the antireflection film, which is away from the substrate, wherein the electrode lead is connected with the silicon through hole structure, and the electrode lead penetrates through the antireflection film and is connected with the electrode area.

Then, as shown in fig. 12, a metal layer is formed on the side of the antireflection film 2 facing away from the epitaxial layer 1 by a thin film deposition process, and the metal layer fills two through holes and contacts the first highly doped region 111 and the second highly doped region 112, respectively, to form a low resistance contact. The metal layer is etched by an etching process to form the electrode lead 3. The electrode lead 3 includes a first lead 31 and a second lead 32 disposed at a lateral interval, the first lead 31 is connected to the first highly doped region 111 and the first through-silicon-via substructure 41, and the second lead 32 is connected to the second highly doped region 112 and the second through-silicon-via substructure 42.

As shown in fig. 12, a thin film deposition process is used to form a protective layer 7 covering the electrode leads 3. The protective layer 7 serves to protect the electrode lead 3. It should be noted that, the protective layer of the photosensitive area needs to be removed, only the antireflection film is reserved, and the light transmittance is ensured.

As shown in connection with fig. 13, the side of the protective layer 7 facing away from the substrate 10 and the surface of the carrier sheet 9 are coated with the bonding medium 8. The carrier sheet 9 is then bonded to the side of the protective layer 7 facing away from the substrate 10 by means of the bonding medium 8.

In this embodiment, the front surface of the substrate 10 is bonded with the carrier 9, and then a subsequent thinning process is performed, so that the mechanical strength of the substrate is increased, the quantum efficiency and the rapid time response of the photodiode are ensured, and the breaking risk is reduced, so that the method is suitable for a large-size process line.

And 140, thinning the side of the substrate away from the anti-reflection film to expose the through silicon via structure.

In the case where the base 10 includes the substrate 13 and the epitaxial layer 1, the through-silicon via structure 4 penetrates the antireflection film 2 and the epitaxial layer 1 and extends into the substrate 13. As shown in connection with fig. 14, the side of the substrate 13 facing away from the epitaxial layer 1 is thinned to expose the through silicon via structure 4. The spacer layer 44 at the bottom of the through-silicon via structure 4 is removed to expose the conductive layer 43 in the through-silicon via structure 4 while the substrate 13 is thinned.

In some embodiments, after the thinning of the side of the substrate facing away from the anti-reflection film in step 140 to expose the through silicon via structure, the method further comprises:

Forming a dielectric layer on one side of the substrate away from the antireflection film;

And forming a bonding pad penetrating through the dielectric layer, wherein the bonding pad is connected with the through silicon via structure.

As shown in fig. 15, a thin film deposition process is used to form a dielectric layer 6 on the side of the substrate 10 facing away from the anti-reflection film 2. Then, two through holes are formed through the dielectric layer 6 by an etching process to expose the through silicon via structure 4. The two vias expose the first and second through-silicon via sub-structures 41 and 42, respectively.

Then, a thin film deposition process is used to form a pad 5 on the side of the dielectric layer 6 facing away from the substrate 10, and the pad 5 is filled in the through hole and connected with the through silicon via structure 4. The pad 5 may include a first pad 51 and a second pad 52 disposed at a lateral interval. The first and second pads 51 and 52 are correspondingly connected to the first and second leads 31 and 32 through the first and second through-silicon-via sub-structures 41 and 42, respectively, so that the anode and cathode of the front-illuminated photodiode are led out to the non-photosensitive side of the substrate 10, so that the peripheral side of the front-illuminated photodiode structure is a splice-able surface.

As shown in fig. 16, after the back side process is completed, the carrier 9 and the side of the protective layer 7 facing away from the substrate 10 are unbuckled by means of unbuckling according to the bonding medium used, so that the front-illuminated photodiode structure is separated from the carrier 9.

In some embodiments, as shown in fig. 17, epitaxial layer 1 further comprises an over-the-air doped region 12 located on the photosensitive side of epitaxial layer 1. The floating doped region 12 is located at the bottom of the wire (i.e., the first wire 31), i.e., the front projection of the first wire 31 onto the epitaxial layer 1 covers the floating doped region 12. The floating doped region 12 is laterally spaced apart from the electrode region 11 and the through-silicon via structure 4, i.e. the floating doped region 12 is laterally spaced apart from the first highly doped region 111, the second highly doped region 112, the first through-silicon via structure 41 and the second through-silicon via structure 42, respectively, and the floating doped region 12 is not connected to any electrode.

The floating doped region 12 is of a different doping type than the epitaxial layer 1, i.e. the floating doped region 12 has a second doping type. The doping concentration of the floating doped region 12 is not particularly limited, i.e., the floating doped region 12 may be a low doped region or a high doped region.

Before the formation of the antireflection film 2, the photosensitive side of the epitaxial layer 1 is doped by an ion implantation process to form a floating doped region 12. The sequence of forming the floating doped region 12, the first highly doped region 111 and the second highly doped region 112 is not particularly limited. In some embodiments, the floating doped region 12 and the first highly doped region 111 can be formed simultaneously, so that the doping type and doping concentration of the floating doped region 12 and the first highly doped region 111 are the same, thereby avoiding additional photomask addition and reducing production cost.

Parasitic capacitance exists between the first lead 31 and the epitaxial layer 1, the floating doped region 12 is added at the bottom of the first lead 31, so that junction capacitance is formed between the floating doped region 12 and the epitaxial layer 1, and the junction capacitance and the original parasitic capacitance can be equivalently connected in series, thereby reducing the total parasitic capacitance.

Since the antireflection film 2 between the first lead 31 and the epitaxial layer 1 is thin (less than 100 nm), a parasitic capacitance C1 exists between the first lead 31 and the epitaxial layer 1. The floating doped region 12 is added at the bottom of the first lead 31, so that a junction capacitance C2 is formed between the floating doped region 12 and the epitaxial layer 1, and the junction capacitance C2 and the parasitic capacitance C1 can be equivalently connected in series, thereby reducing the parasitic capacitance between the first lead 31 and the epitaxial layer 1 and further reducing electronic noise.

For example, the thickness of the antireflection film 2 between the first lead 31 and the epitaxial layer 1 is 70nm, and the parasitic capacitance C1 is 324pF/mm ². After the floating doped region 12 is provided, the equivalent series capacitance C2, the parasitic capacitance is reduced to 13pF/mm ².

In some embodiments, the resistance of epitaxial layer 1 is 500-1500 ohms.

In order to reduce dark current, the photodiode for X-ray detection adopts zero bias under the working state, the P-type high doping area (first high doping area) of the photodiode is highly doped, and the N-type epitaxial layer is low doped and can be similar to a single-side junction. By combining the two points, the width of the depletion region in the working state is only related to the doping concentration of the epitaxial layer (the doping concentration is characterized by the resistance value of the epitaxial layer), and the width of the depletion region influences key parameters such as quantum efficiency, junction capacitance and the like. Furthermore, the doping concentration of the epitaxial layer also affects minority carrier lifetime. In summary, the resistance of the epitaxial layer is critical to the photodiode performance. As shown in fig. 18, the depletion region width and junction capacitance vary with the resistance of the epitaxial layer, the wider the depletion region, the smaller the junction capacitance, and typically the lower the readout electronics noise. Therefore, from the viewpoint of electronic noise, the epitaxial layer resistance should be selected to be as high as possible.

For front-lit photodiodes, most of the absorbed photo-generated carriers are generated in the depletion region and can be directly collected under the action of the built-in electric field. Photogenerated carriers outside the depletion region need to diffuse into the depletion region to be collected and require a sufficient minority carrier lifetime to diffuse into the depletion region. The minority carrier lifetime is greatly affected by the process, such as lattice defects, impurity energy levels and the like, and the minority carrier lifetime is greatly reduced. Thus, the wider the depletion region, the fewer photogenerated carriers outside the depletion region and the less affected by the process. Therefore, the front-illuminated photodiode should select the epitaxial layer resistance value as high as possible.

In this embodiment, the resistance of the epitaxial layer 1 is 500-1500ohm, so that the junction capacitance between the first highly doped region and the epitaxial layer is effectively reduced, the electronic noise is reduced, and the degree of the quantum efficiency affected by the process is reduced.

In some embodiments, the thickness of epitaxial layer 1 is 5-15 μm.

In photodiodes, the epitaxial layer is the active area where the device collects photo-generated carriers, so the epitaxial layer thickness also has a large impact on quantum efficiency. FIG. 19 is a simulation result of the effect on quantum efficiency when the epitaxial layer thickness was 10 μm and 50 μm, respectively. It can be seen that in front-illuminated photodiode structures, the epitaxial layer thickness mainly affects the quantum efficiency at incident wavelengths longer than 600 nm. Because the longer the wavelength of the incident light, the slower the decay rate of the light intensity inside the epitaxial layer (silicon), the greater the number of photogenerated carriers in deeper locations, and the higher the quantum efficiency of the thick epitaxial layer.

The wavelength of incident light of the X-ray detector is generally in the range of 400-650nm, so the front-illuminated photodiode should be selected to have the thickness of the epitaxial layer as thick as possible. In this embodiment, the thickness of the epitaxial layer 1 is 5-15 μm, so as to effectively improve the quantum efficiency.

In summary, according to the preparation method of the front-illuminated photodiode provided by the embodiment of the application, after the slide 9 and the electrode lead 3 are temporarily bonded on the side away from the antireflection film 2, the side of the substrate 10 away from the antireflection film 2 is thinned, so as to increase the mechanical strength of the substrate 10, reduce the breaking risk of the thinned substrate 10, enable the front-illuminated photodiode structure to be produced on a large-size process line, namely be suitable for the large-size process line, so as to improve the production efficiency and reduce the production cost, and lead the electrode of the front-illuminated photodiode to the non-photosensitive side of the substrate 10 through the through silicon via structure 4, so that the periphery of the front-illuminated photodiode structure can be spliced, and the front-illuminated photodiode structure is suitable for pixel arrays with any size. In addition, the floating doped region 12 is provided in the epitaxial layer 1 at the bottom of the first lead 31 to reduce parasitic capacitance between the first lead 31 and the epitaxial layer 1, thereby reducing electronic noise.

Correspondingly, the embodiment of the application also provides a front-illuminated photodiode structure, which can be prepared by adopting the preparation method of the front-illuminated photodiode structure in the embodiment.

Fig. 9 and 16 are schematic structural diagrams of a front-illuminated photodiode structure according to an embodiment of the present application. The front-illuminated photodiode can be applied to an X-ray detector, wherein the X-ray detector is a front-illuminated detector.

As shown in fig. 9 and 16, the front-illuminated photodiode structure provided in the embodiment of the present application includes a substrate 10, an antireflection film 2, an electrode lead 3, and a through-silicon via structure 4.

The substrate 10 comprises an epitaxial layer 1, the epitaxial layer 1 comprising an electrode region 11, the electrode region 11 being located on the photosensitive side of the epitaxial layer 1. The front surface of the epitaxial layer 1 is a photosensitive side, and the photosensitive side is a side on which light is incident on the epitaxial layer 1. The electrode region 1 is located on the front side of the epitaxial layer 1.

The epitaxial layer 1 may be a semiconductor layer including silicon or a semiconductor layer including other elements. The epitaxial layer 1 may be a first doping type epitaxial layer and the first doping type may be N-type. For example, the epitaxial layer 1 may be doped with a trace amount of a pentavalent element such as phosphorus, arsenic, or the like, to constitute an N-type epitaxial layer. In some embodiments, epitaxial layer 1 is an N-type low doped epitaxial layer.

In the preparation process of the front-illuminated photodiode structure, the substrate is temporarily bonded with the slide glass before the back process is performed on the substrate, so that the mechanical strength of the substrate is enhanced, the quantum efficiency and the rapid time response of the photodiode are ensured, and the fragmentation risk is reduced. And then thinning the substrate, after the back surface process of the substrate 10 is completed, the substrate 10 is de-bonded with the carrier sheet, so that the front-illuminated photodiode structure can be produced on a large-size (such as 12 inches) process line, thereby improving the production efficiency and reducing the production cost. The substrate 10 is not required to be thinned, and after thinning, the thickness of the substrate 10 may satisfy a Through Silicon Via (TSV) process, for example, the thickness of the substrate 10 is about 200 μm.

The electrode region 11 comprises a highly doped region (i.e. the first highly doped region 111) of a doping type different from that of the epitaxial layer 1, i.e. the first highly doped region 111 has a second doping type different from the first doping type. For example, trivalent elements, such as boron, are doped into the first highly doped region 111 to constitute a P-type highly doped region. In some embodiments, the epitaxial layer 1 is an N-type lightly doped epitaxial layer, and the first highly doped region 111 is a P-type highly doped region. The first highly doped region 111 is one electrode of the front-illuminated photodiode, such as a cathode or an anode. The first highly doped region 111 may be connected to a power source through a conductive structure such as an electrode lead.

The electrode region 11 may further comprise a second highly doped region 112 of the same doping type as the epitaxial layer 1, i.e. the second highly doped region 112 has the first doping type. The doping concentration of the second highly doped region 112 is greater than the doping concentration of the epitaxial layer 1. In some embodiments, the epitaxial layer 1 is an N-type low doped epitaxial layer, the first highly doped region 111 is a P-type highly doped region, and the second highly doped region 112 is an N-type highly doped region. The second highly doped region 112 is one electrode of the front-illuminated photodiode, such as a cathode or anode. The second highly doped region 112 may be grounded through a conductive structure such as an electrode lead.

The second highly doped region 112 and the first highly doped region 111 are both located on the photosensitive side of the epitaxial layer 1, and the second highly doped region 112 and the first highly doped region 111 are laterally spaced apart, and the lateral direction refers to a direction parallel to the front surface of the epitaxial layer 1. The second highly doped region 112 and the first highly doped region 111 are different electrodes of the front-illuminated photodiode. For example, the first highly doped region 111 is a cathode and the second highly doped region 112 is an anode, or the first highly doped region 111 is an anode and the second highly doped region 112 is a cathode.

The antireflection film 2 is located on the photosensitive side of the epitaxial layer 1, that is, the antireflection film 2 is located on the side of the epitaxial layer 1 near the electrode region 11 and covers the electrode region 11. The antireflection film 2 is used to reduce light reflection and increase transmitted light intensity, thereby improving quantum efficiency. The thickness of the antireflection film 2 is fixed and thin, and the thickness of the antireflection film 2 is smaller than the target thickness, for example, the target thickness is 100nm. The antireflection film 2 is used as a dielectric layer at the same time, and the antireflection film 2 may include one or a combination of more of silicon oxide, silicon nitride, and the like.

The electrode lead 3 is located at one side of the antireflection film 2 away from the epitaxial layer 1, and the electrode lead 3 penetrates the antireflection film 2 longitudinally to be connected with the electrode area 11, and the longitudinal direction is a direction perpendicular to the front surface of the epitaxial layer 1. The electrode lead 3 may include one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel, and titanium.

In some embodiments, the electrode lead 3 may include a lead (i.e., the first lead 31) connected to the highly doped region (i.e., the first highly doped region 111). The first lead 31 is located at a side of the antireflection film 2 away from the epitaxial layer 1, and the first lead 31 longitudinally penetrates the antireflection film 2 to be connected with the first highly doped region 111. The first leads 31 may extend laterally to enlarge the connection window to facilitate connection of the through-silicon via structure.

The electrode lead 3 may further include a second lead 32 connected to the second highly doped region 112, and the second lead 32 is spaced apart from the first lead 31. The second lead 32 is located at a side of the anti-reflection film 2 away from the epitaxial layer 1, and the second lead 32 longitudinally penetrates the anti-reflection film 2 to be connected with the second high doped region 112. The second leads 32 may extend laterally to enlarge the connection window to facilitate connection of the through silicon via structure.

The through silicon via structure 4 longitudinally penetrates the substrate 10 and the antireflection film 2, and the through silicon via structure 4 is connected with the electrode lead 3. The electrode region 11 is connected to the through-silicon via structure 4 by the electrode lead 3, i.e. the electrode region 11 is led out to the non-photosensitive side of the substrate 10 by the electrode lead 3 and the through-silicon via structure 4. The non-photosensitive side is disposed opposite to the photosensitive side, i.e., the non-photosensitive side of the substrate 10 is located on the side of the substrate 10 facing away from the anti-reflection film 2.

In some embodiments, the through-silicon via structure 4 may include a first through-silicon via sub-structure 41 and a second through-silicon via sub-structure 42 disposed laterally spaced apart. The first through-silicon via substructure 41 longitudinally penetrates the substrate 10 and the anti-reflection film 2 and is connected to the first lead 31 to draw the first highly doped region 111 out to the non-photosensitive side of the substrate 10 through the first through-silicon via substructure 41 and the first lead 31. The second through-silicon via substructure 42 longitudinally penetrates the substrate 10 and the anti-reflection film 2 and is connected to the second lead 32 to draw the second highly doped region 112 out to the non-photosensitive side of the substrate 10 through the second through-silicon via substructure 42 and the second lead 32.

The manner of forming the through-silicon via structure 4 is not particularly limited. May be formed on the photosensitive side before temporary bonding or may be formed on the back side after thinning.

In some embodiments, first through silicon via substructure 41 and second through silicon via substructure 42 each include a conductive layer 43 and a spacer layer 44. The conductive layer 43 longitudinally penetrates the substrate 10 and the anti-reflection film 2 and is connected with the electrode lead 3, i.e. the conductive layer 43 in the first through silicon via substructure 41 longitudinally penetrates the substrate 10 and the anti-reflection film 2 and is connected with the first lead 31, and the conductive layer 43 in the second through silicon via substructure 42 longitudinally penetrates the substrate 10 and the anti-reflection film 2 and is connected with the second lead 32. A spacer layer 44 is provided around the conductive layer 43 to isolate the conductive layer 43 from other film layers. Wherein the conductive layer 43 may comprise one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel, and titanium, and the spacer layer 44 may comprise one or more combinations of silicon nitride and silicon oxide, etc.

The electrode region 11 is led out from the non-photosensitive side of the substrate 10 through the electrode lead 3 and the through-silicon via structure 4, so that the peripheral side of the front-illuminated photodiode structure is a spliced surface, i.e. the peripheral side of the front-illuminated photodiode structure can be spliced with the peripheral sides of other front-illuminated photodiode structures. Under the condition that the cross section of the front-illumination type photodiode structure is rectangular, four side faces of the front-illumination type photodiode structure are all spliced faces. The front-illuminated photodiodes can be spliced to form any pixel array, so that the front-illuminated photodiodes are suitable for various application scenes, such as security inspection, industrial detection, medical imaging and the like.

In some embodiments, the base 10 further comprises a substrate 13, the substrate 13 being located on a side of the epitaxial layer 1 facing away from the anti-reflection film 2. The epitaxial layer 1 is of a different doping type than the substrate 13. For example, epitaxial layer 1 may be an N-type epitaxial layer and substrate 13 may be a P-type or N-type substrate.

In the embodiment, the N-type epitaxial layer is grown on the P-type substrate, so that the pollution to a large-size (such as 12 inches) process line is reduced, and the N-type epitaxial requirement of the X-ray detector is met.

In some embodiments, as shown in fig. 9, the front-illuminated photodiode structure further comprises a dielectric layer 6 and a pad 5. The dielectric layer 6 is located at one side of the substrate 10 facing away from the anti-reflection film 2, and the through silicon via structure 4 further penetrates through the dielectric layer 6, i.e. the through silicon via structure 4 longitudinally penetrates through the dielectric layer 6, the substrate 10 and the anti-reflection film 2 and is connected with the electrode lead 3. The dielectric layer 6 may comprise one or more combinations of silicon nitride and silicon oxide, etc.

The pad 9 is located on the side of the dielectric layer 6 facing away from the substrate 10 and is connected to the through-silicon via structure 4. The pads 5 are connected to the conductive layer 43 in the through-silicon via structure 4. The bonding pad 5 may include one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel, and titanium. In some embodiments, as shown in fig. 9, the pad 5 may include a first pad 51 and a second pad 52 disposed at a lateral interval. The first solder joint 51 is located at a side of the dielectric layer 6 facing away from the substrate 10 and is connected to the conductive layer 43 in the first through-silicon-via substructure 41, so that the first highly doped region 111 is led out through the first lead 31, the first through-silicon-via substructure 41 and the first solder joint 51. The first pad 51 may be connected to a power source such that the first highly doped region 111 is connected to the power source through the first lead 31, the first through silicon via sub-structure 41 and the first pad 51. The second pad 52 is located on a side of the dielectric layer 6 facing away from the substrate 10 and is connected to the conductive layer 43 in the second through-silicon-via substructure 42, such that the second highly doped region 112 is led out through the second lead 32, the second through-silicon-via substructure 42 and the second pad 52. The second bond pad 52 may be grounded such that the second highly doped region 112 is grounded through the second lead 32, the second through-silicon-via substructure 42, and the second bond pad 52.

In some embodiments, as shown in fig. 16, the front-illuminated photodiode structure further comprises a dielectric layer 6 and a pad 5. The dielectric layer 6 is located on one side of the substrate 10 facing away from the anti-reflection film 2, and the bonding pad 5 is located on one side of the dielectric layer 6 facing away from the substrate 10 and penetrates through the dielectric layer 6 to be connected with the through silicon via structure 4.

In some embodiments, as shown in fig. 16, the pad 5 may include a first pad 51 and a second pad 52 disposed at a lateral interval. The first solder joint 51 is located at a side of the dielectric layer 6 facing away from the substrate 10, and penetrates through the dielectric layer 6 to be connected with the conductive layer 43 in the first through-silicon-via substructure 41, so that the first highly doped region 111 is led out through the first lead 31, the first through-silicon-via substructure 41 and the first solder joint 51. The second solder joint 52 is located at a side of the dielectric layer 6 facing away from the substrate 10, and penetrates through the dielectric layer 6 to be connected with the conductive layer 43 in the second through-silicon-via substructure 42, so that the second highly doped region 112 is led out through the second lead 32, the second through-silicon-via substructure 42 and the second solder joint 52.

In some embodiments, the front-illuminated photodiode structure further includes a protective layer 7, and the protective layer 7 covers the electrode lead 3 to protect the electrode lead 3. The protective layer 7 may include one or more combinations of silicon oxide and silicon nitride, etc.

In some embodiments, as shown in fig. 17, epitaxial layer 1 further comprises an over-the-air doped region 12 located on the photosensitive side of epitaxial layer 1. The floating doped region 12 is located at the bottom of the wire (i.e., the first wire 31), i.e., the front projection of the first wire 31 onto the epitaxial layer 1 covers the floating doped region 12. The floating doped region 12 is laterally spaced apart from the electrode region 11 and the through-silicon via structure 4, i.e. the floating doped region 12 is laterally spaced apart from the first highly doped region 111, the second highly doped region 112, the first through-silicon via structure 41 and the second through-silicon via structure 42, respectively, and the floating doped region 12 is not connected to any electrode. For example, the bottom of the first lead 31 of the floating doped region 12 is laterally spaced apart between the first through-silicon via structure 41 and the first highly doped region 111.

The depth, width, etc. of the floating doped region 12 are not particularly limited. The floating doped region 12 is of a different doping type than the epitaxial layer 1, i.e. the floating doped region 12 has a second doping type. The doping concentration of the floating doped region 12 is not particularly limited, i.e., the floating doped region 12 may be a low doped region or a high doped region.

In some embodiments, epitaxial layer 1 is an N-type lightly doped epitaxial layer and first highly doped region 111 and floating doped region 12 are both P-type highly doped regions. The first heavily doped region 111 and the floating doped region 12 can be formed simultaneously without adding an additional mask, thereby avoiding increasing the process complexity and the production cost.

Since the antireflection film 2 between the first lead 31 and the epitaxial layer 1 is thin (less than 100 nm), the parasitic capacitance C1 between the first lead 31 and the epitaxial layer 1 is large. The floating doped region 12 is disposed at the bottom of the first lead 31, so that a junction capacitance C2 is formed between the floating doped region 12 and the epitaxial layer 1, and the junction capacitance C2 and the parasitic capacitance C1 are equivalent to be connected in series, thereby reducing the parasitic capacitance between the first lead 31 and the epitaxial layer 1 and further reducing electronic noise.

In some embodiments, the resistance of epitaxial layer 1 is 500-1500 ohms. The depletion region width and junction capacitance of the front-illuminated photodiode change with the resistance of the epitaxial layer, the higher the resistance, the wider the depletion region, the smaller the junction capacitance, and typically the lower the readout electronics noise. In this embodiment, the resistance of the epitaxial layer 1 is 500-1500ohm, so as to effectively reduce the junction capacitance between the first highly doped region 111 and the epitaxial layer 1, reduce electronic noise, and reduce the degree of the quantum efficiency affected by the process.

In some embodiments, the thickness of epitaxial layer 1 is 5-15 μm. The longer the wavelength of the incident light of the front-illuminated photodiode, the slower the decay rate of the light intensity inside the epitaxial layer (silicon), the greater the number of photogenerated carriers in deeper locations and the higher the quantum efficiency. Therefore, the front-illuminated photodiode should be chosen to have an epitaxial layer thickness as thick as possible. In this embodiment, the thickness of the epitaxial layer 1 is 5-15 μm, so that the quantum efficiency can be effectively improved.

In summary, according to the preparation method of the front-illuminated photodiode provided by the embodiment of the application, after the slide 9 and the electrode lead 3 are temporarily bonded on the side away from the antireflection film 2, the side of the substrate 10 away from the antireflection film 2 is thinned, so that the mechanical strength of the substrate 10 is increased, the quantum efficiency and the rapid time response of the photodiode are ensured, the breaking risk of the thinned substrate 10 is reduced, the front-illuminated photodiode structure can be produced on a large-size process line, namely, the front-illuminated photodiode structure is suitable for a large-size process line, so that the production efficiency is improved, the production cost is reduced, and the electrode of the front-illuminated photodiode is led out to the non-photosensitive side of the substrate 10 through the through-silicon-hole structure 4, so that the periphery of the front-illuminated photodiode structure can be spliced, and the front-illuminated photodiode structure is suitable for pixel arrays with any size.

Correspondingly, the embodiment of the application also provides an X-ray detector.

The X-ray detector provided by the embodiment of the present application includes a front-illuminated photodiode structure, where the front-illuminated photodiode structure is the front-illuminated photodiode in the above embodiment, and detailed descriptions thereof are omitted herein.

The X-ray detector can be applied to the fields of security inspection, industrial detection and medical imaging, and a scintillator is used for converting an X-ray signal into a visible light signal, then the visible light signal is converted into an electric signal through a front-illuminated photodiode, and the electric signal is output to a data processing and control circuit after being processed by an ADC (analog-to-digital converter).

In some embodiments, the X-ray detector may include a plurality of front-lit photodiode structures that are tiled. The front-illuminated photodiode structure is a spliced structure, namely, the peripheral side surface of the front-illuminated photodiode structure is a spliced surface. Under the condition that the cross section of the front-illumination type photodiode structure is rectangular, four side faces of the front-illumination type photodiode structure are all spliced faces. The back-illuminated photodiode structures can form a large-area pixel array through splicing, and the back-illuminated photodiode structure is suitable for scenes such as medical imaging.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more.

In the description of the present application, "plurality" means two or more.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the application as defined by the appended claims and their equivalents.

Claims

1. A front-illuminated photodiode structure, comprising:

2. The front-illuminated photodiode structure of claim 1, wherein a peripheral side of the front-illuminated photodiode structure is a stitchable side.

3. The front-illuminated photodiode structure of claim 1 wherein the electrode region comprises a highly doped region of a different doping type than the epitaxial layer, the electrode lead comprising a lead connected to the highly doped region;

4. The front-illuminated photodiode structure of claim 1 wherein the through-silicon via structure includes a conductive layer and a spacer layer, the conductive layer extending through the substrate and the anti-reflection film and being connected to the electrode leads, the spacer layer being disposed around the conductive layer.

5. The front-lit photodiode structure of claim 1, wherein the base further comprises a substrate;

6. The front-illuminated photodiode structure of claim 5 wherein the substrate is a P-type or N-type substrate and the epitaxial layer is an N-type epitaxial layer.

7. The front-lit photodiode structure of claim 1, wherein the front-lit photodiode structure further comprises:

8. The front-lit photodiode structure of claim 1, wherein the front-lit photodiode structure further comprises:

And a protective layer covering the electrode leads.

9. The structure of claim 1-8, wherein the epitaxial layer has a resistance of 500-1500ohm, and/or,

The thickness of the epitaxial layer is 5-15 mu m.

10. An X-ray detector comprising a front-lit photodiode structure as claimed in any one of claims 1-9.

11. The X-ray detector of claim 10, wherein the X-ray detector comprises a plurality of the front-lit photodiode structures that are tiled.

12. A method for fabricating a front-illuminated photodiode structure, comprising:

Thinning one side of the substrate, which is away from the antireflection film;

the method further comprises the steps of:

13. The method of claim 12, wherein the substrate is a 12-inch or 8-inch wafer.

14. The method of claim 12, wherein the substrate further comprises a substrate on a side of the epitaxial layer facing away from the anti-reflection film;

thinning one side of the substrate away from the epitaxial layer;

The forming of the through silicon via structure comprises:

15. The method of claim 12, wherein the substrate further comprises a substrate on a side of the epitaxial layer facing away from the anti-reflection film;

The forming of the through silicon via structure comprises:

16. The method of claim 12, further comprising, prior to temporarily bonding the carrier sheet to a side of the electrode lead facing away from the anti-reflection film:

And forming a protective layer covering the electrode leads.

17. The method of manufacturing a front-illuminated photodiode structure according to any of claims 12-16, characterized in that the method further comprises: