CN119364865A

CN119364865A - Solar cell and preparation method thereof, photovoltaic module

Info

Publication number: CN119364865A
Application number: CN202411552249.3A
Authority: CN
Inventors: 张鹏; 欧文凯; 张东威
Original assignee: Jiangmen Pule Kairui Solar Energy Technology Co ltd
Current assignee: Jiangmen Pule Kairui Solar Energy Technology Co ltd
Priority date: 2024-11-01
Filing date: 2024-11-01
Publication date: 2025-01-24

Abstract

The present application relates to a solar cell and a method for preparing the same, and a photovoltaic module. The solar cell comprises: a semiconductor substrate having a first surface and a second surface arranged opposite to each other; a first region and a second region arranged alternately along a first direction are provided on the semiconductor substrate; the first direction is perpendicular to the thickness direction of the semiconductor substrate; a first semiconductor layer is provided on the first surface and is located in the first region; the first semiconductor layer comprises an intrinsic semiconductor portion and a doped semiconductor portion, and the orthographic projection of the intrinsic semiconductor portion on the semiconductor substrate is located between the orthographic projection of the doped semiconductor portion on the semiconductor substrate and the second region; a first electrode is provided on the first surface and is in ohmic contact with the doped semiconductor portion of the first semiconductor layer; a second electrode is provided on the first surface and is in ohmic contact with the semiconductor substrate; the polarities of the first electrode and the second electrode are opposite. The present application is conducive to improving the leakage of solar cells.

Description

Solar cell, preparation method thereof and photovoltaic module

Technical Field

The application relates to the technical field of solar photovoltaic cells, in particular to a solar cell, a preparation method thereof and a photovoltaic module.

Background

A solar cell, also called a photovoltaic cell, is a semiconductor device that directly converts light energy of the sun into electrical energy. Because it is a green environment-friendly product, does not cause environmental pollution, and is a renewable resource, the solar cell is a novel energy source with wide development prospect under the condition of current energy shortage. At present, more than 80% of solar cells are prepared from crystalline silicon materials, so that the preparation of high-efficiency crystalline silicon solar cells has great significance for large-scale solar power generation.

Because the light receiving surface of the back contact solar cell is not provided with the main grid line, the anode and the cathode are both positioned on the back surface of the cell, the shading rate of the grid line of the light receiving surface is greatly reduced, and the conversion efficiency of the cell is improved, so the back contact solar cell becomes a hot spot for developing the current solar cell. However, since the electrodes of the back contact solar cell are all on the backlight surface, bad problems such as electric leakage easily occur, and the photoelectric conversion efficiency of the back contact solar cell is reduced.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a solar cell, a method of manufacturing the same, and a photovoltaic module.

In a first aspect, an embodiment of the present application provides a solar cell, including:

The semiconductor device comprises a semiconductor substrate, a first substrate, a second substrate, a first electrode, a second electrode, a first electrode and a second electrode, wherein the first surface and the second surface are oppositely arranged;

The semiconductor device comprises a first surface, a second surface, a first semiconductor layer, a second semiconductor layer, a first electrode and a second electrode, wherein the first surface is arranged on the first surface and is positioned in the first region;

A first electrode provided on the first surface and in ohmic contact with the doped semiconductor portion of the first semiconductor layer;

And the second electrode is arranged on the first surface and in ohmic contact with the semiconductor substrate, and the polarities of the first electrode and the second electrode are opposite.

In one embodiment, a ratio of a dimension of the intrinsic semiconductor portion along the first direction to a dimension of the doped semiconductor portion along the first direction is between 1:4 and 1:5.

In one embodiment, the solar cell further comprises a tunneling layer disposed between the first semiconductor layer and the first face.

In one embodiment, the tunneling layer has a thickness of 1nm-3nm;

And/or the thickness of the first semiconductor layer is 40nm-100nm.

In one embodiment, the solar cell further comprises:

The first passivation layer group is arranged on the first surface and is positioned in the first region and the second region, the first passivation layer group positioned in the first region covers the surface of one side of the first semiconductor layer far away from the semiconductor substrate, and the first passivation layer group positioned in the second region at least covers the first surface;

The surface field layer is arranged in the semiconductor substrate and is connected with the second surface;

The second passivation layer group is arranged on the second surface and is positioned in the first area and the second area.

In a second aspect, an embodiment of the present application provides a method for manufacturing a solar cell, including:

the method comprises the steps of providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are oppositely arranged, and the semiconductor substrate is provided with first areas and second areas which are alternately arranged along a first direction, and the first direction is perpendicular to the thickness direction of the semiconductor substrate;

Forming a first semiconductor layer on the first face of the first region, wherein the first semiconductor layer comprises an intrinsic semiconductor part and a doped semiconductor part, and the orthographic projection of the intrinsic semiconductor part on the semiconductor substrate is positioned between the orthographic projection of the doped semiconductor part on the semiconductor substrate and the second region;

And forming a first electrode and a second electrode on the first surface, wherein the first electrode is in ohmic contact with the doped semiconductor part of the first semiconductor layer, the second electrode is in ohmic contact with the semiconductor substrate, and the polarities of the first electrode and the second electrode are opposite.

In one embodiment, the forming a first semiconductor layer on the first side of the first region includes:

Forming an intrinsic semiconductor layer on the first side of the first region, the intrinsic semiconductor layer comprising a first portion and a second portion, an orthographic projection of the first portion on the semiconductor substrate being located between an orthographic projection of the second portion on the semiconductor substrate and the second region;

Forming a slurry containing a doping element on the second portion of the intrinsic semiconductor layer;

and performing annealing treatment to form the first semiconductor layer.

In one embodiment, the forming an intrinsic semiconductor layer on the first face of the first region includes:

The intrinsic semiconductor layer is formed on the first face located in the first region based on a mask plate.

In one embodiment, before forming the intrinsic semiconductor layer on the first face of the first region, the method includes:

And forming a tunneling layer on the first surface of the first region based on the mask plate.

In a third aspect, embodiments of the present application provide a photovoltaic module comprising the solar cell of any of the embodiments of the first aspect.

According to the solar cell, the preparation method thereof and the photovoltaic module provided by the embodiment of the application, the first semiconductor layer comprising the intrinsic semiconductor part and the doped semiconductor part is arranged in the first region, and the orthographic projection of the intrinsic semiconductor part on the semiconductor substrate is positioned between the orthographic projection of the doped semiconductor part on the semiconductor substrate and the second region. Therefore, when the first electrode and the second electrode respectively work as the positive electrode and the negative electrode, the intrinsic semiconductor part can separate the positive electrode from the negative electrode of the battery, which is favorable for leading the positive electrode and the negative electrode to have better insulating property, thereby improving the electric leakage problem of the solar battery.

Drawings

In order to more clearly illustrate the technical solutions of embodiments or exemplary embodiments of the present application, the drawings that are required to be used in the description of the embodiments or exemplary embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

Fig. 1 is a schematic view of a partial cross-sectional structure of a solar cell according to an embodiment of the application.

Fig. 2 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the application.

Fig. 3 is a schematic flow chart of S200 in the preparation method shown in fig. 2.

Fig. 4 to 10 are schematic partial cross-sectional structures of the solar cell during the manufacturing method shown in fig. 2.

Reference numerals:

1. Solar cell, 11, semiconductor substrate, 111, first face, 112, second face, 11a, first region, 11b, second region, 12, tunneling layer, 13, first semiconductor layer, 131, intrinsic semiconductor portion, 132, doped semiconductor portion, 14, first electrode, 15, second electrode, 16, first passivation layer group, 161, first passivation layer, 162, first antireflection layer, 17, second passivation layer group, 171, second passivation layer, 172, second antireflection layer, 18, surface field layer, 21, oxide layer, 22, intrinsic semiconductor layer, 23, slurry.

Detailed Description

In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. The present application may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the application, whereby the application is not limited to the specific embodiments disclosed below.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

In a first aspect, referring to fig. 1, an embodiment of the present application provides a solar cell 1 including a semiconductor substrate 11, a first semiconductor layer 13, a first electrode 14, and a second electrode 15. The semiconductor substrate 11 has a first face 111 and a second face 112 disposed opposite to each other. In the embodiment of the application, the first surface 111 is a backlight surface, and the second surface 112 is a light receiving surface. The semiconductor substrate 11 is provided with first regions 11a and second regions 11b alternately arranged in a first direction X, which is perpendicular to the thickness direction of the semiconductor substrate 11. The first semiconductor layer 13 is disposed on the first surface 111 and is located in the first region 11a, and the first semiconductor layer 13 includes an intrinsic semiconductor portion 131 and a doped semiconductor portion 132, wherein an orthographic projection of the intrinsic semiconductor portion 131 on the semiconductor substrate 11 is located between an orthographic projection of the doped semiconductor portion 132 on the semiconductor substrate 11 and the second region 11 b. The first electrode 14 is disposed on the first surface 111 and in ohmic contact with the doped semiconductor portion 132 of the first semiconductor layer 13. The second electrode 15 is disposed on the first surface 111 and is in ohmic contact with the semiconductor substrate 11. The polarity of the first electrode 14 and the second electrode 15 is opposite. It is understood that one of the first electrode 14 and the second electrode 15 is a positive electrode, and the other is a negative electrode.

It is understood that the material of the semiconductor substrate 11 may be silicon, a compound semiconductor, ‌, and a wide bandgap semiconductor material. Illustratively, the silicon includes crystalline silicon, amorphous silicon. The compound semiconductor includes selenium, ‌ selenide, and the like. The wide bandgap semiconductor material includes silicon carbide, gallium nitride, diamond, etc.

In the embodiment of the present application, the region corresponding to the second region 11b is a first conductivity type region, and the region corresponding to the doped semiconductor portion 132 in the first region 11a is a second conductivity type region. One of the first conductive type region and the second conductive type region is an N type region, and the other is a P type region.

The solar cell 1 provided in the embodiment of the present application is formed by disposing the first semiconductor layer 13 including the intrinsic semiconductor portion 131 and the doped semiconductor portion 132 in the first region 11a, and making the orthographic projection of the intrinsic semiconductor portion 131 on the semiconductor substrate 11 be located between the orthographic projection of the doped semiconductor portion 132 on the semiconductor substrate 11 and the second region 11b, that is, equivalently, disposing the intrinsic semiconductor portion 131 between the N-type region and the P-type region. In this way, when the first electrode 14 and the second electrode 15 respectively operate as the positive electrode and the negative electrode, the intrinsic semiconductor portion 131 can separate the positive electrode and the negative electrode of the battery, which is beneficial to the positive electrode and the negative electrode having better insulating property, so as to improve the leakage problem of the solar battery 1.

The semiconductor substrate 11 is provided with a plurality of first regions 11a and a plurality of second regions 11b, and all of the first regions 11a and all of the second regions 11b are alternately arranged along the first direction X. Namely, a second region 11b is provided between any two adjacent first regions 11a, and a first region 11a is provided between any two adjacent second regions 11 b. Each first region 11a is provided with a first semiconductor layer 13 corresponding thereto.

In one embodiment, when the second regions 11b are disposed on both sides of one first region 11a along the first direction X, the first semiconductor layer 13 corresponding to the first region 11a includes one doped semiconductor portion 132 and two intrinsic semiconductor portions 131, and the two intrinsic semiconductor portions 131 are respectively disposed on both sides of the one doped semiconductor portion 132 along the first direction X. When the first region 11a is provided with the second region 11b on only one side (along the first direction X), the first semiconductor layer 13 corresponding to the first region 11a includes one doped semiconductor portion 132 and one intrinsic semiconductor portion 131, and the one intrinsic semiconductor portion 131 is located on the side of the one doped semiconductor portion 132 close to the second region 11 b.

In one embodiment, as shown in fig. 1, the ratio of the dimension of the intrinsic semiconductor portion 131 along the first direction X to the dimension of the doped semiconductor portion 132 along the first direction X is between 1:4 and 1:5. In fig. 1, the intrinsic semiconductor portion 131 has a dimension L1 along the first direction X, and the doped semiconductor portion 132 has a dimension L2 along the first direction X. Illustratively, the ratio of the dimensions of L1 and L2 may be 1:4, 1:4.5, 1:4.8, 1:5, etc.

In the solar cell 1, on the other hand, the area below the doped semiconductor portion 132 is the PN junction effective area, and the embodiment of the application is beneficial to making the PN junction effective area larger and improving the efficiency of the solar cell 1.

In one embodiment, L2 has a length between 100 μm and 200 μm. Illustratively, the length of L2 may be 100 μm, 120 μm, 160 μm, 180 μm, 200 μm, or between any two of the above.

In one embodiment, the second region 11b has a dimension in the first direction X of between 300 μm and 500. Mu.m. The second region 11b may have a dimension in the first direction X of 300 μm, 350 μm, 400 μm, 430 μm, 480 μm or between any two of the above values, for example.

In one embodiment, the solar cell 1 further comprises a tunneling layer 12, the tunneling layer 12 being arranged between the first semiconductor layer 13 and the first side 111. Illustratively, the tunneling layer 12 may be made of a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polysilicon, silicon carbide, or titanium oxide. In this way, the tunneling layer 12 and the first semiconductor layer 13 can form a tunneling passivation contact structure, which is favorable for reducing carrier recombination and improving the open-circuit voltage and short-circuit current of the battery.

In one embodiment, the tunneling layer 12 has a thickness between 1nm and 3nm. Illustratively, the thickness of the tunneling layer 12 may be 1nm, 2nm, 3nm, or between any two of the above values. Thus, the tunneling layer 12 can have a better passivation effect.

In one embodiment, the thickness of the first semiconductor layer 13 is between 40nm and 100nm. Illustratively, the thickness of the first semiconductor layer 13 may be 40nm, 50nm, 60nm, 80nm, 100nm or between any two of the above values. In this way, the first electrode 14 can prevent the first semiconductor layer 13 from being burned through during sintering to damage the semiconductor substrate 11, and the intrinsic semiconductor portion 131 of the first semiconductor layer 13 can have better insulating properties, and the doped semiconductor portion 132 of the first semiconductor layer 13 can have better conductive properties.

In one embodiment, the material of the first semiconductor layer 13 is polysilicon. Specifically, the intrinsic semiconductor portion 131 is intrinsic polysilicon, and the doped semiconductor portion 132 is bit-doped polysilicon. In another embodiment, the intrinsic semiconductor portion 131 is amorphous silicon, and the doped semiconductor portion 132 is doped polysilicon.

In one embodiment, the solar cell 1 further comprises a first passivation layer group 16, a surface field layer 18 and a second passivation layer group 17.

The first passivation layer set 16 is disposed on the first surface 111 and is located in the first region 11a and the second region 11b. The first passivation layer group 16 located in the first region 11a covers a surface of the first semiconductor layer 13 away from the semiconductor substrate 11, that is, the first passivation layer group 16 located in the first region 11a contacts a surface of the first semiconductor layer 13 away from the semiconductor substrate 11. The first passivation layer group 16 located in the second region 11b covers at least the first face 111, i.e. the first passivation layer group 16 located in the second region 11b is in contact with the first face 111. The first electrode 14 and the second electrode 15 each penetrate through the first passivation layer group 16. The surface field layer 18 is disposed in the semiconductor substrate 11 and contacts the second surface 112. The second passivation layer group 17 is disposed on the second face 112 and is located in the first region 11a and the second region 11b.

By providing the first passivation layer group 16 and the second passivation layer group 17, the solar cell 1 can have better passivation performance. By providing the surface field layer 18, the collection capability of carriers can be enhanced.

In one embodiment, the first passivation layer group 16 includes a first passivation layer 161 and a first anti-reflection layer 162 stacked in a direction away from the semiconductor substrate 11, and the second passivation layer group 17 includes a second passivation layer 171 and a second anti-reflection layer 172 stacked in a direction away from the semiconductor substrate 11. The materials of the first passivation layer 161 and the second passivation layer 171 may be aluminum oxide, silicon oxide, etc., and the materials of the first anti-reflection layer 162 and the second anti-reflection layer 172 may be one or more combinations of SiNx, siOxNy, siOx.

In one embodiment, the distance between the first face 111 and the second face 112 of the first zone 11a is greater than the distance between the first face 111 and the second face 112 of the second zone 11 b.

In one embodiment, a connection surface (not shown) is provided between the first surface 111 located in the first region 11a and the first surface 111 located in the second region 11b, and the first passivation layer group 16 also covers the connection surface. In this way, the passivation performance of the solar cell 1 can be made better.

In a second aspect, referring to fig. 2, and referring to fig. 4 to 10, an embodiment of the present application provides a method for manufacturing a solar cell 1, which specifically includes the following steps:

S100, providing a semiconductor substrate 11. The semiconductor substrate 11 has a first face 111 and a second face 112 disposed opposite to each other, and the semiconductor substrate 11 is provided with first regions 11a and second regions 11b alternately arranged in a first direction X, which is perpendicular to a thickness direction of the semiconductor substrate 11.

The first semiconductor layer 13 is formed on the first face 111 located in the first region 11a S200. The first semiconductor layer 13 includes an intrinsic semiconductor portion 131 and a doped semiconductor portion 132, and an orthographic projection of the intrinsic semiconductor portion 131 on the semiconductor substrate 11 is located between an orthographic projection of the doped semiconductor portion 132 on the semiconductor substrate 11 and the second region 11 b.

The first electrode 14 and the second electrode 15 are formed on the first surface 111S 400. The first electrode 14 is in ohmic contact with the doped semiconductor portion 132 of the first semiconductor layer 13, the second electrode 15 is in ohmic contact with the semiconductor substrate 11, and the polarities of the first electrode 14 and the second electrode 15 are opposite. It will be appreciated that the first electrode 14 and the second electrode 15 may be manufactured by printing, sintering, or the like.

The method for manufacturing the solar cell 1 according to the embodiment of the present application is that the first semiconductor layer 13 including the intrinsic semiconductor portion 131 and the doped semiconductor portion 132 is disposed in the first region 11a, and the orthographic projection of the intrinsic semiconductor portion 131 on the semiconductor substrate 11 is located between the orthographic projection of the doped semiconductor portion 132 on the semiconductor substrate 11 and the second region 11b, that is, is equivalent to disposing the intrinsic semiconductor portion 131 between the N-type region and the P-type region. In this way, when the first electrode 14 and the second electrode 15 respectively operate as the positive electrode and the negative electrode, the intrinsic semiconductor portion 131 can separate the positive electrode and the negative electrode of the battery, which is beneficial to the positive electrode and the negative electrode having better insulating property, so as to improve the leakage problem of the solar battery 1.

In one embodiment, referring to fig. 3, S200, a first semiconductor layer 13 is formed on a first surface 111 located in a first region 11a, and specifically includes the steps of:

The intrinsic semiconductor layer 22 is formed on the first face 111 located in the first region 11a S210. It will be appreciated that the intrinsic semiconductor layer 22 includes a first portion (not shown) and a second portion (not shown), the orthographic projection of the first portion on the semiconductor substrate 11 being located between the orthographic projection of the second portion on the semiconductor substrate 11 and the second region 11 b. Here, the first portion corresponds to the intrinsic semiconductor portion 131, and the second portion corresponds to the doped semiconductor portion 132. It will be appreciated that the intrinsic semiconductor layer 22 may be fabricated using ALD (Atomic Layer Deposition ), PECVD (PLASMA ENHANCED CHEMICAL Vapor Deposition), PEALD (PLASMA ENHANCED Atomic Layer Deposition ), LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical Vapor Deposition), and the like. Illustratively, the intrinsic amorphous silicon is deposited by an LPCVD process at a process temperature of 700-900 ℃. The structure of the intrinsic semiconductor layer 22 after formation is shown in fig. 7.

And S220, forming a slurry 23 containing a doping element on the second portion of the intrinsic semiconductor layer 22. The structure of the slurry 23 after formation is shown in fig. 8. Specifically, the phosphorus-containing slurry 23 may be printed on the second portion. The solids content of the phosphorus-containing slurry 23 may be 15% -35%. The phosphorus-containing slurry 23 may be composed of organic substances such as phosphoric acid, terpineol, butyrolactone, dodecanol ester, and the like. The embodiment of the application can realize the localized doping of the specific area by printing the slurry 23, thereby being beneficial to improving the leakage problem.

And S230, performing annealing treatment to form the first semiconductor layer 13. The structure after the first semiconductor layer 13 is formed is shown in fig. 9. It is understood that the annealing treatment may be performed by means of laser annealing or thermal annealing, the second portion forming the doped semiconductor portion 132 and the first portion forming the intrinsic semiconductor portion 131. It is understood that crystallization of the intrinsic semiconductor layer 22 occurs during the annealing. In one example, an annealing treatment is performed in a tube annealing furnace using a temperature of 700 ℃ to 1000 ℃ for 5 minutes.

In one embodiment, S210, an intrinsic semiconductor layer 22 is formed on the first side 111 of the first region 11a, comprising the steps of:

S211, forming an intrinsic semiconductor layer 22 on the first surface 111 located in the first region 11a based on the mask. The formation region of the intrinsic semiconductor layer 22 may be controlled by depositing the intrinsic semiconductor layer 22 through a mask. Specifically, on one hand, the generation of deposition around plating of the intrinsic semiconductor layer 22 is controlled, on the other hand, the deposition precision of the intrinsic semiconductor layer 22 is ensured, on the other hand, the tedious process of etching is reduced, and the manufacturing cost is reduced.

In one embodiment, S210, before forming the intrinsic semiconductor layer 22 on the first face 111 of the first region 11a, the method further includes the steps of:

And S190, forming a tunneling layer 12 on the first surface 111 positioned in the first region 11a based on the mask plate. The structure of tunneling layer 12 after formation is shown in fig. 7. Specifically, the tunneling layer 12 may be fabricated by high temperature thermal oxidation or wet oxidation. The formation area of the tunneling layer 12 can be controlled by depositing the tunneling layer 12 through a mask. Specifically, on one hand, the generation of deposition around plating of the tunneling layer 12 is controlled, on the other hand, the deposition precision of the tunneling layer 12 is ensured, on the other hand, the tedious process brought by etching is reduced, and the manufacturing cost is reduced. It will be appreciated that the same mask may be used to fabricate the tunneling layer 12 and the intrinsic semiconductor layer 22.

In one embodiment, after providing the semiconductor substrate 11, S100, before forming the first semiconductor layer 13 on the first face 111 of the first region 11a, further comprises the steps of:

and S110, performing texturing treatment on the semiconductor substrate 11. Illustratively, the texturing solution includes NaOH, ADDI, H ₂O,NaOH、ADDI、H₂ O in a volume ratio of 3:1:20. The temperature of the texturing treatment is between 70 ℃ and 85 ℃. The treatment time is 300s-500s. The reflectivity of the pyramid pile face is about 8% -12%.

S120, forming a surface field layer 18 in the semiconductor substrate 11. Ion diffusion may be performed using a high temperature tube process to provide surface field layer 18. Specifically, BCL ₃ is introduced at a process temperature of about 900-1100 ℃, and oxide layer 21 is generated on the surface of semiconductor substrate 11 by oxidation while diffusing, the thickness of oxide layer 21 is about 30-80 nm, and the sheet resistance of surface field layer 18 is 200 Ω/sq-400 Ω/sq. The structure of the surface field layer 18 after formation is shown in fig. 4.

And S130, carrying out partial grooving treatment on the first surface 111 by adopting a laser ablation mode. The grooved structure is shown in fig. 5. The laser light spot adopts square light spots, the size of the square light spots is 150um-250um, and the overlapping rate of the light spots is 20% -80%. The width of the laser kerf (dimension in the horizontal direction in fig. 5) is approximately 300um-500um.

And S140, polishing the laser grooving area. The polishing solution comprises H ₂ O and NaOH, the volume ratio of H ₂ O to NaOH is 20:1, the concentration of NaOH is 45%, the treatment temperature is 65-75 ℃, the treatment time is 200-300 s, and the interface reflectivity after polishing is about 45%.

And S150, removing the oxide layer 21 by adopting an HF aqueous solution with the concentration of 1 percent. The resulting structure is shown in fig. 6.

In one embodiment, S200, after forming the first semiconductor layer 13 on the first side 111 located in the first region 11a, S400, before forming the first electrode 14 and the second electrode 15 on the first side 111, further comprises the steps of:

S300, forming a first passivation layer 161 and a second passivation layer 171 on the first surface 111 and the second surface 112, respectively, and forming a first anti-reflection layer 162 and a second anti-reflection layer 172 on the first passivation layer 161 and the second passivation layer 171, respectively. As shown in fig. 10, specifically, the first passivation layer 161 and the second passivation layer 171 may be fabricated using an atomic layer deposition process at a process temperature of 150-300 ℃ with trimethylaluminum and ozone as process gases, and the thicknesses of the first passivation layer 161 and the second passivation layer 171 may be 1nm-10nm. The first anti-reflection layer 162 and the second anti-reflection layer 172 are deposited by chemical vapor deposition, and the materials of the first anti-reflection layer 162 and the second anti-reflection layer 172 can be one or more combinations of SiNx, siOxNy, siOx.

In S400, a laser may be used to form a groove in the first passivation layer group 16, the laser power is about 60W to 90W, and a laser with a wavelength of 352nm is used to etch the first passivation layer 161 and the first anti-reflection layer 162 in a predetermined area (the laser groove forming area and the area where the doped semiconductor portion 132 is located), and the groove forming width in the predetermined area is about 100um to 300um. Next, an aluminum paste is printed by means of the printing paste 23 on the aforementioned laser grooved region (second region 11 b) to form a positive electrode (second electrode 15), a silver paste is printed on the region where the doped semiconductor portion 132 is located to form a negative electrode (first electrode 14), and then sintering curing is performed at a temperature of 700 to 900 ℃.

Illustratively, the photovoltaic module includes a plurality of solar cells that can be string welded together by a solder ribbon to collect electrical energy generated by the individual solar cells for subsequent delivery. Of course, the solar cells can be arranged at intervals, and can also be stacked together in a shingle mode.

Further, the photovoltaic module further comprises an encapsulation layer and a cover plate, wherein the encapsulation layer is used for covering the surface of the battery string, and the cover plate is used for covering the surface, far away from the battery string, of the encapsulation layer. The solar cells are electrically connected in whole or multiple pieces to form multiple cell strings, and the multiple cell strings are electrically connected in series and/or parallel. Specifically, in some embodiments, multiple battery strings may be electrically connected by conductive charges. The encapsulation layer covers the surface of the solar cell. The encapsulation layer may be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film, or a polyethylene terephthalate film, for example. The cover plate can be a glass cover plate, a plastic cover plate and the like with a light transmission function.

It should be understood that, in the embodiment of the present application, at least a part of the steps in the drawings may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. A solar cell, comprising:

A semiconductor substrate having a first surface and a second surface arranged opposite to each other; the semiconductor substrate is provided with first regions and second regions arranged alternately along a first direction; the first direction is perpendicular to a thickness direction of the semiconductor substrate;

a first semiconductor layer, disposed on the first surface and located in the first region; the first semiconductor layer comprises an intrinsic semiconductor portion and a doped semiconductor portion, an orthographic projection of the intrinsic semiconductor portion on the semiconductor substrate being located between an orthographic projection of the doped semiconductor portion on the semiconductor substrate and the second region;

A first electrode is disposed on the first surface and is in ohmic contact with the doped semiconductor portion of the first semiconductor layer;

The second electrode is disposed on the first surface and is in ohmic contact with the semiconductor substrate; the polarities of the first electrode and the second electrode are opposite.

2 . The solar cell according to claim 1 , wherein a ratio of a size of the intrinsic semiconductor portion along the first direction to a size of the doped semiconductor portion along the first direction is between 1:4 and 1:5.

3 . The solar cell according to claim 1 , further comprising a tunneling layer, wherein the tunneling layer is disposed between the first semiconductor layer and the first surface.

4. The solar cell according to claim 3, characterized in that the thickness of the tunneling layer is between 1 nm and 3 nm;

And/or, the thickness of the first semiconductor layer is between 40nm and 100nm.

5. The solar cell according to claim 1, characterized in that the solar cell further comprises:

a first passivation layer group, disposed on the first surface and located in the first region and the second region; the first passivation layer group located in the first region covers a surface of the first semiconductor layer away from the semiconductor substrate; the first passivation layer group located in the second region at least covers the first surface; the first electrode and the second electrode both penetrate the first passivation layer group;

A surface field layer is disposed in the semiconductor substrate and is in contact with the second surface;

The second passivation layer group is disposed on the second surface and located in the first region and the second region.

6. A method for preparing a solar cell, comprising:

A semiconductor substrate is provided; the semiconductor substrate has a first surface and a second surface arranged opposite to each other, and the semiconductor substrate is provided with first regions and second regions arranged alternately along a first direction; the first direction is perpendicular to a thickness direction of the semiconductor substrate;

forming a first semiconductor layer on the first surface located in the first region; the first semiconductor layer comprises an intrinsic semiconductor portion and a doped semiconductor portion, an orthographic projection of the intrinsic semiconductor portion on the semiconductor substrate being located between an orthographic projection of the doped semiconductor portion on the semiconductor substrate and the second region;

A first electrode and a second electrode are formed on the first surface; the first electrode is in ohmic contact with the doped semiconductor portion of the first semiconductor layer, the second electrode is in ohmic contact with the semiconductor substrate, and the first electrode and the second electrode have opposite polarities.

7. The method for preparing a solar cell according to claim 6, wherein forming a first semiconductor layer on the first surface located in the first region comprises:

forming an intrinsic semiconductor layer on the first surface located in the first region; the intrinsic semiconductor layer comprises a first portion and a second portion, an orthographic projection of the first portion on the semiconductor substrate being located between an orthographic projection of the second portion on the semiconductor substrate and the second region;

forming a paste containing a doping element on the second portion of the intrinsic semiconductor layer;

An annealing process is performed to form the first semiconductor layer.

8. The method for preparing a solar cell according to claim 7, wherein forming an intrinsic semiconductor layer on the first surface located in the first region comprises:

The intrinsic semiconductor layer is formed on the first surface located in the first region based on a mask.

9. The method for preparing a solar cell according to claim 8, characterized in that before forming the intrinsic semiconductor layer on the first surface located in the first region, the method comprises:

A tunneling layer is formed on the first surface located in the first region based on the mask.

10. A photovoltaic module, characterized by comprising the solar cell according to any one of claims 1 to 5.