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CN119109419A - Signal generating circuit - Google Patents

Signal generating circuit Download PDF

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Publication number
CN119109419A
CN119109419A CN202411204978.XA CN202411204978A CN119109419A CN 119109419 A CN119109419 A CN 119109419A CN 202411204978 A CN202411204978 A CN 202411204978A CN 119109419 A CN119109419 A CN 119109419A
Authority
CN
China
Prior art keywords
circuit
switching device
frequency division
feedback circuit
output end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202411204978.XA
Other languages
Chinese (zh)
Inventor
邹庆
王海舟
欧阳煜东
常志昆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang Geoforcechip Technology Co Ltd
Original Assignee
Zhejiang Geoforcechip Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Zhejiang Geoforcechip Technology Co Ltd filed Critical Zhejiang Geoforcechip Technology Co Ltd
Priority to CN202411204978.XA priority Critical patent/CN119109419A/en
Publication of CN119109419A publication Critical patent/CN119109419A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
    • H03B5/24—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

本申请提供一种信号产生电路，涉及电路技术领域。该信号产生电路包括：振荡电路，振荡电路包括：电流源、充放电电路、比较器、分频反馈电路；电流源的供电端分别与充放电电路的第一端、充放电电路的第二端连接，充放电电路的第一端与比较器的负输入端连接，充放电电路的第二端与比较器的正输入端连接；比较器的输出端与分频反馈电路的时钟输入端连接，比较器的输出端还与充放电电路的第一控制端连接，分频反馈电路的控制端用于输入频率控制信号，分频反馈电路的控制信号输出端与充放电电路的第二控制端连接，分频反馈电路的振荡信号输出端用于输出频率控制信号对应的振荡信号。实现了采用同一振荡电路电路输出不同频率的振荡信号。

The present application provides a signal generating circuit, and relates to the field of circuit technology. The signal generating circuit includes: an oscillating circuit, and the oscillating circuit includes: a current source, a charging and discharging circuit, a comparator, and a frequency-dividing feedback circuit; the power supply end of the current source is respectively connected to the first end of the charging and discharging circuit and the second end of the charging and discharging circuit, the first end of the charging and discharging circuit is connected to the negative input end of the comparator, and the second end of the charging and discharging circuit is connected to the positive input end of the comparator; the output end of the comparator is connected to the clock input end of the frequency-dividing feedback circuit, and the output end of the comparator is also connected to the first control end of the charging and discharging circuit, the control end of the frequency-dividing feedback circuit is used to input a frequency control signal, the control signal output end of the frequency-dividing feedback circuit is connected to the second control end of the charging and discharging circuit, and the oscillation signal output end of the frequency-dividing feedback circuit is used to output an oscillation signal corresponding to the frequency control signal. The same oscillating circuit is used to output oscillation signals of different frequencies.

Description

Signal generating circuit
Technical Field
The application relates to the technical field of circuits, in particular to a signal generating circuit.
Background
With the continuous development of the fields of communication, internet of things, sensors, biomedicine and the like, the requirements on system on chip (SoC, system on Circuits) chips are higher and higher, so that the requirements are developed to the directions of lower cost, lower power consumption and more stability. It is an urgent need to provide a high-precision clock module with stable and reliable performance for these electronic systems.
In the related art, the same oscillating circuit can only output oscillating signals with one frequency, and the same oscillating circuit cannot output oscillating signals with different frequencies.
Disclosure of Invention
The present application is directed to a signal generating circuit for solving the above-mentioned problems of the related art.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows:
in a first aspect, an embodiment of the present application provides a signal generating circuit, including an oscillating circuit, the oscillating circuit including a current source, a charge-discharge circuit, a comparator, and a frequency division feedback circuit;
the power supply end of the current source is respectively connected with the first end of the charge-discharge circuit and the second end of the charge-discharge circuit, the first end of the charge-discharge circuit is connected with the negative input end of the comparator, and the second end of the charge-discharge circuit is connected with the positive input end of the comparator;
The output end of the comparator is connected with the clock input end of the frequency division feedback circuit, the output end of the comparator is also connected with the first control end of the charge-discharge circuit, the control end of the frequency division feedback circuit is used for inputting a frequency control signal, the control signal output end of the frequency division feedback circuit is connected with the second control end of the charge-discharge circuit, and the oscillation signal output end of the frequency division feedback circuit is used for outputting an oscillation signal corresponding to the frequency control signal.
Optionally, the charge-discharge circuit comprises a first resistor, a second resistor, a first capacitor, a first switching device and a second switching device;
one end of the first resistor is a first end of the charge-discharge circuit, one end of the first capacitor is a second end of the charge-discharge circuit, and a control end of the first switching device is a second control end of the charge-discharge circuit;
the other end of the first capacitor is grounded, one end of the first capacitor is grounded through the second switching device, and the control end of the second switching device is a first control end of the charge-discharge circuit.
Optionally, the frequency division feedback circuit comprises a first sub frequency division feedback circuit, a second sub frequency division feedback circuit, a third sub frequency division feedback circuit and an OR gate circuit;
The control output end of the first sub frequency division feedback circuit is connected with the control end of the first sub frequency division feedback circuit, and the output end of the first sub frequency division feedback circuit is respectively connected with the clock input end of the second sub frequency division feedback circuit and the clock input end of the third sub frequency division feedback circuit;
The control end of the second sub frequency division feedback circuit is a control end of the frequency division feedback circuit, and the control signal output end of the second sub frequency division feedback circuit is a control signal output end of the frequency division feedback circuit;
The output end of the third sub frequency division feedback circuit is connected with the second input end of the OR gate circuit, the reset end of the third sub frequency division feedback circuit is connected with the reset signal output end of the second sub frequency division feedback circuit, the output end of the third sub frequency division feedback circuit is connected with the control end of the third sub frequency division feedback circuit, and the output end of the OR gate circuit is the oscillation signal output end of the frequency division feedback circuit.
Optionally, the first sub-frequency division feedback circuit comprises a first trigger and a first inverter;
The clock input end of the first trigger is the clock input end of the frequency division feedback circuit, the control output end of the first trigger is the control output end of the first sub frequency division feedback circuit, the output end of the first trigger is connected with the input end of the first inverter, and the output end of the first inverter is the output end of the first sub frequency division feedback circuit.
Optionally, the second sub-frequency division feedback circuit comprises a second trigger, a second inverter and an AND gate circuit;
The clock input end of the second trigger is the clock input end of the second sub frequency division feedback circuit, the control end of the second trigger is the control end of the second sub frequency division feedback circuit, the output end of the second trigger is the reset signal output end of the second sub frequency division feedback circuit, and the output end of the second trigger is connected with the input end of the second inverter;
the output end of the first sub frequency division feedback circuit is connected with the second input end of the AND gate circuit, and the output end of the AND gate circuit is the output end of the second sub frequency division feedback circuit.
Optionally, the third sub-divide feedback circuit includes a third flip-flop, a third inverter, a fourth inverter, and a fifth inverter, including:
the clock input end of the third trigger is the clock input end of the third sub-frequency division feedback circuit, the reset end of the third trigger is the reset end of the third sub-frequency division feedback circuit, and the output end of the third trigger is connected with the input end of the fifth inverter through the fourth inverter;
The output end of the fifth inverter is the output end of the third sub-frequency division feedback circuit, the control end of the third trigger is the control end of the third sub-frequency division feedback circuit, the output end of the fifth inverter is connected with the input end of the third inverter, and the output end of the third inverter is connected with the control end of the third trigger.
Optionally, the signal generating circuit further comprises a failure detecting circuit;
The output end of the oscillating signal of the frequency division feedback circuit is connected with the input end of the failure detection circuit, the failure detection circuit is used for carrying out frequency failure detection on the oscillating signal, the output end of the failure detection circuit is used for outputting a detection signal aiming at the oscillating signal, and the detection signal is used for indicating whether the oscillating signal has frequency failure or not.
Optionally, the failure detection circuit comprises a pulse generation circuit, a capacitor discharge ramp circuit and a digital latch circuit;
The input end of the pulse generating circuit is the input end of the failure detection circuit, the output end of the pulse generating circuit is connected with the input end of the capacitor discharging ramp circuit, the output end of the capacitor discharging ramp circuit is connected with the input end of the digital latch circuit, and the output end of the digital latch circuit is the output end of the failure detection circuit.
Optionally, the capacitor discharging ramp circuit comprises a second capacitor, a third switching device, a fourth switching device, a fifth switching device, a sixth switching device and a seventh switching device;
The input end of the capacitor discharging ramp circuit comprises a control end of the third switching device and a control end of the fourth switching device, wherein the first end of the third switching device and the first end of the fourth switching device are both connected with a power supply voltage end, and the output end of the capacitor discharging ramp circuit comprises a second end of the third switching device and a second end of the fourth switching device;
The control end of the fifth switching device, the first end of the fifth switching device, the control end of the sixth switching device and the control end of the seventh switching device are respectively used for receiving input bias current, the second end of the fifth switching device is grounded, the first end of the sixth switching device is connected with the second end of the third switching device, the second end of the sixth switching device is grounded, the first end of the seventh switching device is connected with the second end of the fourth switching device, and the second end of the seventh switching device is grounded.
Optionally, the third switching device and the fourth switching device are P-type metal-oxide semiconductor field effect transistor MOS transistors, and the fifth switching device, the sixth switching device and the seventh switching device are N-type MOS transistors.
The signal generation circuit has the beneficial effects that the signal generation circuit comprises an oscillation circuit, wherein the oscillation circuit comprises a current source, a charge-discharge circuit, a comparator and a frequency division feedback circuit, the power supply end of the current source is respectively connected with the first end of the charge-discharge circuit and the second end of the charge-discharge circuit, the first end of the charge-discharge circuit is connected with the negative input end of the comparator, the second end of the charge-discharge circuit is connected with the positive input end of the comparator, the output end of the comparator is connected with the clock input end of the frequency division feedback circuit, the output end of the comparator is also connected with the first control end of the charge-discharge circuit, the control end of the frequency division feedback circuit is used for inputting a frequency control signal, the control signal output end of the frequency division feedback circuit is connected with the second control end of the charge-discharge circuit, and the oscillation signal output end of the frequency division feedback circuit is used for outputting an oscillation signal corresponding to the frequency control signal. The control end of the frequency division feedback circuit inputs a frequency control signal, the charging time of the charging and discharging circuit is controlled through the control signal output end of the frequency division feedback circuit and the second control end of the charging and discharging circuit according to the frequency control signal, and the charging time of the charging and discharging circuit is controlled through the output end of the comparator and the first control end of the charging and discharging circuit, so that the oscillating circuit outputs oscillating signals corresponding to the frequency control signal, namely the oscillating signals output for different frequency control signals are different, and the purpose of outputting the oscillating signals with different frequencies by adopting the same oscillating circuit is achieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a signal generating circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an oscillating circuit according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a charge-discharge circuit according to an embodiment of the present application;
Fig. 4 is a schematic structural diagram of a comparator according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a frequency division feedback circuit according to an embodiment of the present application;
fig. 6 is a schematic diagram of a signal generating circuit according to a second embodiment of the present application;
fig. 7 is a schematic structural diagram of a failure detection circuit according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a pulse generating circuit according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a capacitive discharge ramp circuit according to an embodiment of the present application;
Fig. 10 is a schematic diagram of a digital latch circuit according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that, if the terms "upper", "lower", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or an azimuth or the positional relationship conventionally put in use of the product of the application, it is merely for convenience of describing the present application and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.
Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
Fig. 1 is a schematic diagram of a signal generating circuit according to an embodiment of the present application, as shown in fig. 1, the signal generating circuit may include an oscillating circuit 100, where the oscillating circuit 100 includes a current source 101, a charge-discharge circuit 102, a comparator 103, and a frequency division feedback circuit 104.
The power supply end of the current source 101 is respectively connected with a first end of the charge-discharge circuit 102 and a second end of the charge-discharge circuit 102, the first end of the charge-discharge circuit 102 is connected with a negative input end of the comparator 103, and the second end of the charge-discharge circuit 102 is connected with a positive input end of the comparator 103;
in addition, an output end of the comparator 103 is connected to a clock input end of the frequency division feedback circuit 104, an output end of the comparator 103 is also connected to a first control end of the charge/discharge circuit 102, a control end of the frequency division feedback circuit 104 is used for inputting a frequency control signal, a control signal output end of the frequency division feedback circuit 104 is connected to a second control end of the charge/discharge circuit 102, and an oscillation signal output end of the frequency division feedback circuit 104 is used for outputting an oscillation signal corresponding to the frequency control signal.
In some embodiments, the control end of the frequency division feedback circuit 104 inputs a frequency control signal, the frequency control signal is a low level signal, the control signal output end of the frequency division feedback circuit 104 controls the second control end of the charge and discharge circuit 102, the output end of the comparator 103 controls the first control end of the charge and discharge circuit 102, the charge and discharge time of the charge circuit is shortened, the charge and discharge frequency of the charge circuit is increased, and the output end of the comparator 103 outputs a high-frequency clock signal to the clock input end of the frequency division feedback circuit 104, so that the oscillation signal output end of the frequency division feedback circuit 104 outputs a high-frequency oscillation signal.
In other embodiments, the control terminal of the frequency division feedback circuit 104 inputs a frequency control signal, the frequency control signal is a high level signal, the control signal output terminal of the frequency division feedback circuit 104 controls the second control terminal of the charge/discharge circuit 102, and the output terminal of the comparator 103 controls the first control terminal of the charge/discharge circuit 102, so that the charge/discharge time of the charge/discharge circuit 102 is prolonged, and then the charge/discharge frequency of the charge circuit is reduced, and the output terminal of the comparator 103 outputs a low frequency clock signal to the clock input terminal of the frequency division feedback circuit 104, so that the oscillation signal output terminal of the frequency division feedback circuit 104 outputs a low frequency oscillation signal.
Alternatively, the oscillating signal may be a square wave signal. The oscillation signal output end of the frequency division feedback circuit 104 in the oscillation circuit can output a square wave signal with high frequency or a square wave signal with low frequency.
It should be noted that, the current source 101 may be simply referred to as i_chg, and the number of the current sources 101 may be one, two, or other numbers, which is not particularly limited in the embodiment of the present application.
In summary, the embodiment of the application provides a signal generating circuit, which comprises an oscillating circuit, wherein the oscillating circuit comprises a current source 101, a charge-discharge circuit 102, a comparator 103 and a frequency division feedback circuit 104, a power supply end of the current source 101 is respectively connected with a first end of the charge-discharge circuit 102 and a second end of the charge-discharge circuit 102, the first end of the charge-discharge circuit 102 is connected with a negative input end of the comparator 103, a second end of the charge-discharge circuit 102 is connected with a positive input end of the comparator 103, an output end of the comparator 103 is connected with a clock input end of the frequency division feedback circuit 104, an output end of the comparator 103 is also connected with a first control end of the charge-discharge circuit 102, a control end of the frequency division feedback circuit 104 is used for inputting a frequency control signal, a control signal output end of the frequency division feedback circuit 104 is connected with a second control end of the charge-discharge circuit 102, and an oscillating signal output end of the frequency division feedback circuit 104 is used for outputting an oscillating signal corresponding to the frequency control signal. The control end of the frequency division feedback circuit 104 inputs a frequency control signal, the charging time of the charge-discharge circuit 102 is controlled through the control signal output end of the frequency division feedback circuit 104 and the second control end of the charge-discharge circuit 102 according to the frequency control signal, and the charging time of the charge-discharge circuit 102 is controlled through the output end of the comparator 103 and the first control end of the charge-discharge circuit 102, so that the oscillating circuit outputs oscillating signals corresponding to the frequency control signal, namely the oscillating signals output for different frequency control signals are different, and the purpose of outputting the oscillating signals with different frequencies by adopting the same oscillating circuit is achieved.
Optionally, fig. 2 is a schematic structural diagram of an oscillating circuit according to an embodiment of the present application, and as shown in fig. 2, the charge-discharge circuit 102 includes a first resistor 1021, a second resistor 1022, a first capacitor 1023, a first switching device 1024 and a second switching device 1025.
One end of the first resistor 1021 is a first end of the charge-discharge circuit 102, and the first capacitor 1023
One end is a second end of the charge-discharge circuit 102, the control end of the first switch device 1024 is a second control end of the charge-discharge circuit 102, the other end of the first resistor 1021 is grounded through the second resistor 1022, the other end of the first resistor 1021 is grounded through the first switch device 1024, the other end of the first capacitor 1023 is grounded, one end of the first capacitor 1023 is grounded through the second switch device 1025, and the control end of the second switch device 1025 is a first control end of the charge-discharge circuit 102.
Wherein VDD (power supply positive voltage) is used to power two current sources 101,
In the embodiment of the present application, the current source 101 is used to charge the first capacitor 1023, to supply power to one end of the first resistor 1021, the comparator 103 is used to compare the capacitor charging voltage at one end of the first capacitor 1023 with the resistor voltage drop at one end of the first resistor 1021, if the charging voltage is greater than the resistor voltage drop, the second switching device 1025 is controlled to be closed to discharge the first capacitor 1023, the output signal of the comparator 103 is inverted, so that the partial node level in the frequency division feedback circuit 104 is inverted, because the capacitor discharging speed quickly causes the second switching device 1025 to be disconnected to restart charging the first capacitor 1023, and when the next resistor charging voltage is greater than the resistor voltage drop, the output signal of the comparator 103 is inverted again, so that the partial node level in the frequency division feedback circuit 104 is continuously inverted, and the oscillation signal output end of the frequency division feedback circuit 104 is used to output the oscillation signal corresponding to the frequency control signal.
In some embodiments, the control terminal of the frequency division feedback circuit 104 inputs a frequency control signal, the frequency control signal is a low level signal, the control signal output terminal of the frequency division feedback circuit 104 controls the control terminal of the first switching device 1024 so that the first switching device 1024 is closed, when the first switching device 1024 is closed, the second resistor 1022 is short-circuited, current only flows through the first resistor 1021, the resistance voltage drop input by the negative input terminal of the comparator 103 is reduced, that is, the threshold value referenced by the comparator 103 is reduced, so that the time required by the first capacitor 1023 during charging is shorter, and the charging and discharging frequency of the first capacitor 1023 is higher. Meanwhile, the output of the comparator 103 also affects the frequency division feedback circuit 104, and finally, the oscillation signal output end of the frequency division feedback circuit 104 outputs an oscillation signal with high frequency.
In other embodiments, the control terminal of the frequency division feedback circuit 104 inputs a frequency control signal, the frequency control signal is a high level signal, the control terminal of the first switching device 1024 is controlled by the control signal output terminal of the frequency division feedback circuit 104, so that the first switching device 1024 is turned off, when the first switching device 1024 is turned off, the first resistor 1021 and the second resistor 1022 are connected in series, current flows through the first resistor 1021 and the second resistor 1022, the resistance voltage drop input by the negative input terminal of the comparator 103 increases, that is, the threshold value referenced by the comparator 103 increases during comparison, so that the time required by the first capacitor 1023 during charging is longer, and the charge-discharge frequency of the first capacitor 1023 is lower. Meanwhile, the output of the comparator 103 also affects the frequency division feedback circuit 104, and finally, the oscillation signal output end of the frequency division feedback circuit 104 outputs an oscillation signal with low frequency.
It should be noted that the high-frequency oscillation signal may be a high-frequency square wave signal, and the negative input voltage of the comparator 103 may be V IN- =i·r for the circuit principle of generating the high-frequency square wave information, where R represents the resistance value of the first resistor 1021. The comparator 103 outputs a reverse voltage when the charging voltage inputted from the positive input terminal is inputted to the negative input terminal of the comparator 103, and the charging speed of the first capacitor 1023 is:
Where I represents a current flowing through the first capacitor 1023, and C represents a capacitance value of the first capacitor 1023.
Then the relation between the frequency f osc of the square wave signal capable of obtaining high frequency, the capacitance value C of the first capacitor 1023 and the resistance value R of the first resistor 1021 is solved as follows:
Similarly, the relationship between the frequency f osc of the square wave signal with low frequency, the capacitance C of the first capacitor 1023 and the resistance R of the first resistor 1021 is:
in practical applications, the first capacitor 1023 may be formed by a selectable capacitor array, and the frequency of the oscillating circuit is adjusted by adjusting the capacitance value of the capacitor array.
Optionally, the first switching device 1024 and the second switching device 1025 may be N-type MOS transistors (metal-oxide semiconductor field effect transistors), as shown in fig. 3, in which fig. 3 is a schematic structural diagram of a charge-discharge circuit provided by the embodiment of the present application, one end of the first resistor 1021 is connected to the OUTN end, the OUTN end is connected to the negative input end of the first comparator 103, the other end of the first resistor 1021 is grounded through the second resistor 1022, the other end of the first resistor 1021 is grounded through the drain and source of the first switching device 1024 to VSS (circuit common ground voltage), the gate of the first switching device 1024 is connected to the SEL1 end, the SEL1 end is connected to the control signal output end of the frequency division feedback circuit 104, one end of the first capacitor 1023 is connected to the OUTP end, the OUTP end is connected to the positive input end of the first comparator 103, the other end of the first capacitor 1023 is grounded to VSS, one end of the first capacitor 1023 is grounded through the drain and source of the second switching device, and the gate of the second switching device 1025 is connected to the output end of the CTR 103.
As shown in fig. 3, the charge-discharge circuit 102 further includes an eighth switching device 1026, a ninth switching device 1027, and a tenth switching device 1028. The eighth switching device 1026, the ninth switching device 1027 and the tenth switching device 1028 are P-type MOS transistors. One end of the first resistor 1021 is also connected to the drain of the ninth switching device 1027, one end of the first capacitor 1023 is connected to the drain of the tenth switching device 1028, the gate of the eighth switching device 1026, the gate of the ninth switching device 1027, and the gate of the tenth switching device 1028 are connected to each other, and the source of the eighth switching device 1026, the source of the ninth switching device 1027, and the source of the tenth switching device 1028 are all connected to VDD. The eighth switching device has its drain connected to terminal PIBRI and terminal PIBRI for inputting a bias current.
It should be noted that, the bias current at the PIBR terminal 1 is provided by an external bias circuit, and the SEL1 terminal is connected to the control signal output terminal of the frequency division feedback circuit 104, so as to select the output frequency mode of the oscillating circuit. When the signal at the SEL1 terminal is at a high level, the first switching device 1024 is turned on in a high frequency mode, and when the signal at the SEL1 terminal is at a low level, the first switching device 1024 is turned off in a low frequency mode. The signal at the CTR terminal may be a signal fed back from the comparator 103 after being buffered by the two inverters, when the signal at the CTR terminal is at a high level, the second switching device 1025 is turned on, the first capacitor 1023 is rapidly discharged, then the second switching device 1025 is turned off, and the first capacitor 1023 is continuously charged.
Optionally, fig. 4 is a schematic structural diagram of a comparator according to an embodiment of the present application, and as shown in fig. 4, the comparator 103 includes an eleventh switching device 1031, a twelfth switching device 1032, a thirteenth switching device 1033, a fourteenth switching device 1034, a fifteenth switching device 1035, a sixteenth switching device 1036, a seventeenth switching device 1037, an eighteenth switching device 1038, a nineteenth switching device 1039, and a twentieth switching device 1040.
The source of the eleventh switching device 1031, the source of the twelfth switching device 1032, the source of the thirteenth switching device 1033, and the source of the fourteenth switching device 1034 are connected to the VDD terminal, the gate of the eleventh switching device 1031, the drain of the eleventh switching device 1031, the gate of the twelfth switching device 1032, the gate of the thirteenth switching device 1033, and the gate of the fourteenth switching device 1034 are connected to PIBR and the PIBR terminal is used for inputting the bias current. The drain of the twelfth switching device 1032 is connected to the source of the sixteenth switching device 1036 and the source of the seventeenth switching device 1037, respectively, and the drain of the twelfth switching device 1032 is also connected to the drain of the thirteenth switching device 1033 through the drain and the source of the fifteenth switching device 1035, and the gate of the fifteenth switching device 1035 is connected to the SEL2 terminal.
The sixteenth switching device 1036 has a gate connected to the VN terminal, a gate connected to the VP terminal of the seventeenth switching device 1037, a positive input terminal of the comparator 103 and a negative input terminal of the comparator 103, the sixteenth switching device 1036 has a drain connected to the VSS terminal through the drain and source of the eighteenth switching device 1038, the seventeenth switching device 1037 has a drain connected to the VSS terminal through the drain and source of the nineteenth switching device 1039, and the eighteenth switching device 1038 has a gate connected to the gate of the nineteenth switching device 1039. The drain of the eighteenth switching device 1038 is connected to the gate of the eighteenth switching device 1038, the drain of the nineteenth switching device 1039 is connected to the gate of the twentieth switching device 1040, the drain of the fourteenth switching device 1034 is connected to the VSS terminal via the drain and source of the twentieth switching device 1040, and the drain of the twentieth switching device 1040 is the output terminal of the comparator 103.
The comparator 103 in fig. 3 has a two-stage structure of a five-tube amplifier and a source follower. The mode select SEL2 signal controls the five-tube bias current switch, which is closed in the high frequency mode, with the five-tube bias current being 10I, where the bias current I is the externally provided bias current PIBR2, and open in the low frequency mode, with the five-tube bias current being 5I, with the larger bias current and the larger gain bandwidth product for the two-stage op-amp. When the SEL1 signal is at a high level, the SEL2 signal is at a low level, and the fifteenth switching device 1035 is turned on as a bias current switch, and the current is turned on.
Optionally, fig. 5 is a schematic diagram of a frequency division feedback circuit according to an embodiment of the present application, as shown in fig. 5, the frequency division feedback circuit 104 includes a first sub-frequency division feedback circuit 1041, a second sub-frequency division feedback circuit 1042, a third sub-frequency division feedback circuit 1043, and an or gate circuit 1044;
The control output end of the first sub frequency division feedback circuit 1041 is connected with the control end of the first sub frequency division feedback circuit 1041, and the output end of the first sub frequency division feedback circuit 1041 is respectively connected with the clock input end of the second sub frequency division feedback circuit 1042 and the clock input end of the third sub frequency division feedback circuit 1043;
The control end of the second sub frequency division feedback circuit 1042 is the control end of the frequency division feedback circuit 104, the control signal output end of the second sub frequency division feedback circuit 1042 is the control signal output end of the frequency division feedback circuit 104, the output end of the second sub frequency division feedback circuit 1042 is connected with the first input end of the OR gate 1044;
The output end of the third sub frequency division feedback circuit 1043 is connected to the second input end of the or circuit 1044, the reset end of the third sub frequency division feedback circuit 1043 is connected to the reset signal output end of the second sub frequency division feedback circuit 1042, the output end of the third sub frequency division feedback circuit 1043 is connected to the control end of the third sub frequency division feedback circuit 1043, and the output end of the or circuit 1044 is the oscillation signal output end of the frequency division feedback circuit 104.
In the embodiment of the present application, the control end of the second sub-frequency-dividing feedback circuit 1042 inputs a frequency control signal, the frequency control signal is a low level signal, the second sub-frequency-dividing feedback circuit 1042 controls the third sub-frequency-dividing feedback circuit 1043 to reset, and the third sub-frequency-dividing feedback circuit 1043 does not perform the frequency division function, so that the output end of the or circuit 1044 can output an oscillation signal with high frequency.
In addition, the control end of the second sub-frequency-dividing feedback circuit 1042 inputs a frequency control signal, the frequency control signal is a high level signal, the second sub-frequency-dividing feedback circuit 1042 controls the third sub-frequency-dividing feedback circuit 1043 to work normally, the third sub-frequency-dividing feedback circuit 1043 plays a role of frequency division, and thus the output end of the or circuit 1044 can output an oscillation signal with low frequency.
Optionally, as shown in FIG. 2, the first sub-divide feedback circuit 1041 includes a first flip-flop 1041a and a first inverter 1041b;
The clock input end of the first trigger 1041a is the clock input end of the frequency division feedback circuit 104, the control output end of the first trigger 1041a is the control output end of the first sub frequency division feedback circuit 1041, the output end of the first trigger 1041a is connected with the input end of the first inverter 1041b, and the output end of the first inverter 1041b is the output end of the first sub frequency division feedback circuit 1041.
In the embodiment of the present application, as shown in fig. 2, the clock input terminal of the first flip-flop 1041a may be referred to as Clk terminal, the control terminal of the first flip-flop 1041a may be referred to as D terminal, the output terminal of the first flip-flop 1041a may be referred to as Q terminal, and the control output terminal of the first flip-flop 1041a may be referred to asAnd (3) an end.
Wherein the first trigger 1041aThe terminal is connected to the D terminal of the first trigger 1041 a.
Optionally, as shown in fig. 2, the second sub-divide feedback circuit 1042 includes a second flip-flop 1042a, a second inverter 1042b, and an and circuit 1042c;
The clock input end of the second trigger 1042a is the clock input end of the second sub-frequency-division feedback circuit 1042, the control end of the second trigger 1042a is the control end of the second sub-frequency-division feedback circuit 1042, the output end of the second trigger 1042a is the reset signal output end of the second sub-frequency-division feedback circuit 1042, the output end of the second trigger 1042a is connected with the input end of the second inverter 1042b, the output end of the second inverter 1042b is the control signal output end of the second sub-frequency-division feedback circuit 1042, and is connected with the first input end of the AND gate circuit 1042 c;
The output end of the first sub-frequency-division feedback circuit 1041 is connected to the second input end of the and circuit 1042c, and the output end of the and circuit 1042c is the output end of the second sub-frequency-division feedback circuit 1042.
As shown in fig. 2, the clock input terminal of the second flip-flop 1042a may be referred to as the Clk terminal of the second flip-flop 1042a, the control terminal of the second flip-flop 1042a may be referred to as the D terminal of the second flip-flop 1042a, and the output terminal of the second flip-flop 1042a may be referred to as the Q terminal of the second flip-flop 1042 a.
Optionally, as shown in FIG. 2, the third sub-divide feedback circuit 1043 includes a third flip-flop 1043a, a third inverter 1043b, a fourth inverter 1043c, and a fifth inverter 1043d, including:
The clock input end of the third trigger 1043a is the clock input end of the third sub-frequency division feedback circuit 1043, the reset end of the third trigger 1043a is the reset end of the third sub-frequency division feedback circuit 1043, and the output end of the third trigger 1043a is connected with the input end of the fifth inverter 1043d through the fourth inverter 1043 c;
The output end of the fifth inverter 1043d is the output end of the third sub-frequency division feedback circuit 1043, the control end of the third trigger 1043a is the control end of the third sub-frequency division feedback circuit 1043, the output end of the fifth inverter 1043d is connected with the input end of the third inverter 1043b, and the output end of the third inverter 1043b is connected with the control end of the third trigger 1043 a.
As shown in fig. 2, the clock input terminal of the third flip-flop 1043a may be referred to as a Clk terminal of the third flip-flop 1043a, the control terminal of the third flip-flop 1043a may be referred to as a D terminal of the third flip-flop 1043a, and the output terminal of the third flip-flop 1043a may be referred to as a Q terminal of the second flip-flop 1042 a.
It should be noted that, the Q terminal of the second trigger 1042a outputs a low level, which controls the reset of the third trigger 1043a, the oscillating circuit outputs an oscillating signal with a high frequency, the Q terminal of the second trigger 1042a outputs a high level, which controls the third trigger 1043a to work normally, and the oscillating circuit outputs an oscillating signal with a low frequency. The resistance of the first resistor 1021 may be R, the resistance of the second resistor 1022 may be 3R, and when the third trigger 1043a works normally, the frequency output by the third trigger 1043a is half of the output frequency of the first trigger 1041 a.
Optionally, fig. 6 is a schematic diagram of a second structure of a signal generating circuit according to an embodiment of the present application, and as shown in fig. 6, the signal generating circuit further includes a failure detecting circuit 200.
The oscillation signal output end of the frequency division feedback circuit 104 is connected with the input end of the failure detection circuit 200, the failure detection circuit 200 is used for performing frequency failure detection on the oscillation signal, the output end of the failure detection circuit 200 is used for outputting a detection signal aiming at the oscillation signal, and the detection signal is used for indicating whether the oscillation signal has frequency failure or not.
In a state where the frequency of the oscillation signal is normal, the output terminal of the failure detection circuit 200 outputs a detection signal for the oscillation signal, which is a low-level signal indicating that the frequency of the oscillation signal output by the oscillation circuit is normal, that is, that the oscillation signal output by the oscillation circuit is valid. In a state where the frequency of the oscillation signal is too low, the output terminal of the failure detection circuit 200 outputs a detection signal for the oscillation signal, which is a high-level signal, and the low-level signal indicates that the frequency of the oscillation signal output by the oscillation circuit is too low, that is, the oscillation signal output by the oscillation circuit fails. So that the frequency detection function of the oscillating circuit can be implemented by the failure detection circuit 200.
Optionally, fig. 7 is a schematic structural diagram of a failure detection circuit according to an embodiment of the present application, and as shown in fig. 7, the failure detection circuit 200 includes a pulse generating circuit 201, a capacitor discharging ramp circuit 202, and a digital latch circuit 203;
the input end of the pulse generating circuit 201 is the input end of the failure detecting circuit 200, the output end of the pulse generating circuit 201 is connected with the input end of the capacitor discharging ramp circuit, the output end of the capacitor discharging ramp circuit is connected with the input end of the digital latch circuit 203, and the output end of the digital latch circuit 203 is the output end of the failure detecting circuit 200.
In some embodiments, the oscillation circuit outputs an oscillation signal to the pulse generation circuit 201, the pulse generation circuit 201 generates a pulse signal according to the oscillation signal, the pulse generation circuit 201 outputs the pulse signal to the capacitor discharge ramp circuit, the capacitor discharge ramp circuit generates a ramp signal according to the pulse signal, the capacitor discharge ramp circuit 202 outputs a ramp signal to the digital latch circuit 203, and the digital latch circuit 203 generates a detection signal according to the ramp signal.
Wherein, the ramp signal can be a triangular wave signal.
Optionally, fig. 8 is a schematic diagram of a pulse generating circuit according to an embodiment of the present application, as shown in fig. 8, the pulse generating circuit 201 includes a sixth inverter 2011, a seventh inverter 2012, a third resistor 2013, an eighth inverter 2014, a first nand gate 2015, a fourth resistor 2016, a ninth inverter 2017, a second nand gate 2018, a fourth capacitor 2019, and a fifth capacitor 2020.
As shown in fig. 8, the input terminal of the sixth inverter 2011 is connected to the osc_out terminal, wherein the osc_out terminal is an oscillation signal output terminal of the frequency division feedback circuit 104, the output terminal of the sixth inverter 2011 is connected to the input terminal of the seventh inverter 2012 and one terminal of the fourth resistor 2016, respectively, the output terminal of the seventh inverter 2012 is connected to the input terminal of the eighth inverter 2014 through the third resistor 2013, the output terminal of the seventh inverter 2012 is further grounded to the fourth capacitor 2019 through the third resistor 2013, and the output terminal of the seventh inverter 2012 and the output terminal of the eighth inverter 2014 are both connected to the input terminal of the first nand gate 2015, and the output terminal of the first nand gate 2015 is denoted as V o1.
The other end of the fourth resistor 2016 is grounded via a fifth capacitor 2020, the other end of the fourth resistor 2016 is further connected to the input of a ninth inverter 2017, the output of the ninth inverter 2017 and one end of the fourth resistor 2016 are connected to the input of a second nand gate 2018, and the output of the second nand gate 2018 is denoted as V o2. The first nand gate 2015 outputs a first pulse signal, and the second nand gate 2018 outputs a second pulse signal.
It should be noted that, the main delay of the pulse generating circuit 201 is implemented by resistor and capacitor delay, the pulse signal is obtained by inverting the inverter and processing the nand gate, the pulse signal width is the delay time of the resistor and the capacitor, and the time difference between the two pulse signals is the half period of the square wave signal output by the oscillating circuit minus the pulse width.
Optionally, fig. 9 is a schematic structural diagram of a capacitive discharge ramp circuit according to an embodiment of the present application, as shown in fig. 9, where the capacitive discharge ramp circuit includes a second capacitor 2021, a third capacitor 2022, a third switching device 2023, a fourth switching device 2024, a fifth switching device 2025, a sixth switching device 2026, and a seventh switching device 2027;
The input end of the capacitor discharging ramp circuit comprises a control end of a third switch device 2023 and a control end of a fourth switch device 2024, wherein the first end of the third switch device 2023 and the first end of the fourth switch device 2024 are both connected with a VDD power supply voltage end, the output end of the capacitor discharging ramp circuit comprises a second end of the third switch device 2023 and a second end of the fourth switch device 2024, one end of a second capacitor 2021 and one end of a third capacitor 2022 are both connected with the power supply voltage end, the other end of the second capacitor 2022 is connected with the second end of the third switch device 2023, and the other end of the third capacitor 2022 is connected with the second end of the fourth switch device 2024.
The control terminal of the fifth switching device 2025, the first terminal of the fifth switching device 2025, the control terminal of the sixth switching device 2026, and the control terminal of the seventh switching device 2027 are respectively configured to receive a bias current input through the NIBR terminal, the second terminal of the fifth switching device is grounded, the first terminal of the sixth switching device 2026 is connected to the second terminal of the third switching device 2023, the second terminal of the sixth switching device 2026 is grounded, the first terminal of the seventh switching device 2027 is connected to the second terminal of the fourth switching device 2024, and the second terminal of the seventh switching device 2027 is grounded to VSS.
As shown in fig. 9, the third switching device 2023 and the fourth switching device 2024 are P-type MOS transistors, and the fifth switching device, the sixth switching device 2026 and the seventh switching device 2027 are N-type MOS transistors. The control terminal of the third switching device 2023 and the control terminal of the fourth switching device 2024 are gates, the first terminal of the third switching device 2023 and the first terminal of the fourth switching device 2024 are sources, the second terminal of the third switching device 2023 and the second terminal of the fourth switching device 2024 are drains. In addition, the control terminal of the fifth switching device 2025, the control terminal of the sixth switching device 2026, and the control terminal of the seventh switching device 2027 are gates, the first terminal of the fifth switching device 2025, the first terminal of the sixth switching device 2026, and the first terminal of the seventh switching device 2027 are drains, and the second terminal of the fifth switching device 2025, the second terminal of the sixth switching device 2026, and the second terminal of the seventh switching device 2027 are sources.
The control terminal of the third switching device 2023 is connected to the VN terminal, the control terminal of the fourth switching device 2024 is connected to the VP terminal, the VN terminal is connected to the V o1 in the pulse generating circuit 201 so that the pulse generating circuit 201 inputs the first pulse signal to the control terminal of the third switching device 2023, and the VP terminal is connected to the V o2 in the pulse generating circuit 201 so that the pulse generating circuit 201 inputs the second pulse signal to the control terminal of the fourth switching device 2024. The drain of the third switching device 2023 is connected to the OUTN terminal, through which the first ramp signal is output, and the drain OUTP terminal of the fourth switching device 2024, through which the second ramp signal is output.
In the embodiment of the present application, the dual-end output of the pulse generating signal is connected to the two input terminals VN and VP of the capacitor discharging ramp circuit, and the upper plates of the second capacitor 2021 and the third capacitor 2022 are directly connected to the working voltage, and the lower plates of the second capacitor 2021 and the third capacitor 2022 are connected to each other, and there are two paths, one path is connected to the working voltage through the input P pipe and the other path is connected to the ground through the N pipe. When the grid end of the P tube is input with low level, the on-resistance of the P tube is very small, the lower polar plate can be rapidly charged to working voltage, when the grid end of the P tube is high level, the lower polar plate only has one passage with the ground, the on-resistance of the N tube also exists on the passage, the current on the passage is determined by the current of the N tube current mirror, and the discharge is slowed down.
It should be noted that, the OUTN terminal rapidly jumps to the high level at the falling edge of the input signal at the VN terminal, and starts to discharge slowly at the rising edge of the input signal. The OUTP end is the same. The frequency of the oscillating circuit determines the time from the start of the slow discharge of the OUTP terminal and the OUTN terminal to the next transition to the high level, and since the second capacitor 2021 and the third capacitor 2022 are fixed in size, it can be said that the frequency of the oscillating circuit and the width of the input pulse signal determine the level transition point from the start of the slow discharge of the OUTP terminal and the OUTN terminal to the next transition to the high level, and the level transition point decreases with the decrease of the frequency of the oscillating circuit. In a normal state, the frequency of the oscillating circuit can ensure that the level inversion point is kept at a higher potential, and the NAND gate output of the subsequent stage is kept at a low level. If the oscillating circuit frequency is too low, the level inversion point is at a lower potential, then the NAND gate output of the subsequent stage remains at a high level, and finally outputs a high level. The function of frequency detection of the oscillating circuit is realized.
Alternatively, fig. 10 is a schematic diagram of a digital latch circuit according to an embodiment of the present application, and as shown in fig. 10, the digital latch circuit 203 includes a tenth inverter 2031, a first or gate 2032, an eleventh inverter 2033, a first and gate 2034, a second or gate 2035, a first schmitt trigger 2036, a second schmitt trigger 2037, a nand gate 2038, a third or gate 2039, and a twelfth inverter 2040.
The input terminal of the tenth inverter 2031 is connected to the EN terminal (enable terminal), the output terminal of the tenth inverter 2031 is connected to the first input terminal of the first or gate 2032, the output terminal of the first or gate 2032 is connected to the input terminal of the eleventh inverter 2033, the output terminal of the eleventh inverter 2033 is connected to the first input terminal of the first and gate 2034, the EN terminal is further connected to the second input terminal of the first and gate 2034, the output terminal of the first and gate 2034 is connected to the first input terminal of the second or gate 2035, the output terminal of the second or gate 2035 is connected to the OUT terminal, and the OUT terminal outputs a detection signal.
IN addition, the IN1 end is connected to the input end of the first schmitt trigger 2036, the IN2 end is connected to the input end of the first schmitt trigger 2036, the IN1 end is connected to the OUTN end IN the capacitive discharge ramp circuit, the IN2 end is connected to the OUTP end IN the capacitive discharge ramp circuit, the output end of the first schmitt trigger 2036 and the output end of the second schmitt trigger 2037 are respectively connected to the first input end and the second input end of the nand gate 2038, the output end of the nand gate 2038 is respectively connected to the first input end of the third or gate 2039, the second input end of the third or gate 2039 is connected to the output end of the eleventh inverter 2033, the output end of the third or gate 2039 is connected to the input end of the twelfth inverter 2040, and the output end of the twelfth inverter 2040 is connected to the second input end of the first or gate 2032, and the output end of the nand gate 2038 is connected to the second input end of the second or gate 2035.
In the embodiment of the present application, the measurement frequency of the failure detection module of the oscillating circuit is mainly determined by the bias current input at the NIBR end of the capacitor discharging ramp circuit and the second capacitor 2021 and the third capacitor 2022 in the main circuit. The larger the bias current, the smaller the capacitance, the faster the discharge speed, and the higher the detected oscillator frequency threshold.
In summary, the embodiment of the present application provides a signal generating circuit, in which the control end of the frequency division feedback circuit 104 inputs a frequency control signal, the charging time of the charging and discharging circuit 102 is controlled by the control signal output end of the frequency division feedback circuit 104 and the second control end of the charging and discharging circuit 102 according to the frequency control signal, and the charging time of the charging and discharging circuit 102 is controlled by the output end of the comparator 103 and the first control end of the charging and discharging circuit 102, so that the oscillating circuit outputs oscillating signals corresponding to the frequency control signal, that is, the oscillating signals output for different frequency control signals are different, and the oscillating signals with different frequencies are output by the same oscillating circuit.
By adjusting the resistances of the first resistor 1021 and the second resistor 1022, the oscillating circuit can have two modes of high frequency and low frequency, the oscillating circuit can output an oscillating signal with high frequency in the high frequency mode, and the oscillating circuit can output an oscillating signal with low frequency in the low frequency mode. The oscillating circuit may be an RC relaxation oscillator, and the charge voltage inversion threshold in the charge-discharge circuit 102 is changed by a control signal to generate square wave signals with different frequencies, where the charge-discharge inversion threshold is realized by changing the resistance value of the current path.
And the oscillation signal is processed into pulse signals with about half period difference, and the discharge path of the capacitor is controlled by the pulse signals, so that the frequency failure detection of the oscillator is realized. When the frequency of the oscillation signal is too low, the failure detection circuit 200 jumps.
The above is only a preferred embodiment of the present application, and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. The signal generating circuit is characterized by comprising an oscillating circuit, a voltage divider and a voltage divider, wherein the oscillating circuit comprises a current source, a charge-discharge circuit, a comparator and a frequency division feedback circuit;
the power supply end of the current source is respectively connected with the first end of the charge-discharge circuit and the second end of the charge-discharge circuit, the first end of the charge-discharge circuit is connected with the negative input end of the comparator, and the second end of the charge-discharge circuit is connected with the positive input end of the comparator;
The output end of the comparator is connected with the clock input end of the frequency division feedback circuit, the output end of the comparator is also connected with the first control end of the charge-discharge circuit, the control end of the frequency division feedback circuit is used for inputting a frequency control signal, the control signal output end of the frequency division feedback circuit is connected with the second control end of the charge-discharge circuit, and the oscillation signal output end of the frequency division feedback circuit is used for outputting an oscillation signal corresponding to the frequency control signal.
2. The circuit of claim 1, wherein the charge-discharge circuit comprises a first resistor, a second resistor, a first capacitor, a first switching device, and a second switching device;
one end of the first resistor is a first end of the charge-discharge circuit, one end of the first capacitor is a second end of the charge-discharge circuit, and a control end of the first switching device is a second control end of the charge-discharge circuit;
the other end of the first capacitor is grounded, one end of the first capacitor is grounded through the second switching device, and the control end of the second switching device is a first control end of the charge-discharge circuit.
3. The circuit of claim 1, wherein the divide feedback circuit comprises a first sub-divide feedback circuit, a second sub-divide feedback circuit, a third sub-divide feedback circuit, an OR gate circuit;
The control output end of the first sub frequency division feedback circuit is connected with the control end of the first sub frequency division feedback circuit, and the output end of the first sub frequency division feedback circuit is respectively connected with the clock input end of the second sub frequency division feedback circuit and the clock input end of the third sub frequency division feedback circuit;
The control end of the second sub frequency division feedback circuit is a control end of the frequency division feedback circuit, and the control signal output end of the second sub frequency division feedback circuit is a control signal output end of the frequency division feedback circuit;
The output end of the third sub frequency division feedback circuit is connected with the second input end of the OR gate circuit, the reset end of the third sub frequency division feedback circuit is connected with the reset signal output end of the second sub frequency division feedback circuit, the output end of the third sub frequency division feedback circuit is connected with the control end of the third sub frequency division feedback circuit, and the output end of the OR gate circuit is the oscillation signal output end of the frequency division feedback circuit.
4. The circuit of claim 3, wherein the first sub-divide feedback circuit comprises a first flip-flop and a first inverter;
The clock input end of the first trigger is the clock input end of the frequency division feedback circuit, the control output end of the first trigger is the control output end of the first sub frequency division feedback circuit, the output end of the first trigger is connected with the input end of the first inverter, and the output end of the first inverter is the output end of the first sub frequency division feedback circuit.
5. The circuit of claim 3, wherein the second sub-divide feedback circuit comprises a second flip-flop, a second inverter, and an AND circuit;
The clock input end of the second trigger is the clock input end of the second sub frequency division feedback circuit, the control end of the second trigger is the control end of the second sub frequency division feedback circuit, the output end of the second trigger is the reset signal output end of the second sub frequency division feedback circuit, and the output end of the second trigger is connected with the input end of the second inverter;
the output end of the first sub frequency division feedback circuit is connected with the second input end of the AND gate circuit, and the output end of the AND gate circuit is the output end of the second sub frequency division feedback circuit.
6. The circuit of claim 3, wherein the third sub-divide feedback circuit comprises a third flip-flop, a third inverter, a fourth inverter, and a fifth inverter, comprising:
the clock input end of the third trigger is the clock input end of the third sub-frequency division feedback circuit, the reset end of the third trigger is the reset end of the third sub-frequency division feedback circuit, and the output end of the third trigger is connected with the input end of the fifth inverter through the fourth inverter;
The output end of the fifth inverter is the output end of the third sub-frequency division feedback circuit, the control end of the third trigger is the control end of the third sub-frequency division feedback circuit, the output end of the fifth inverter is connected with the input end of the third inverter, and the output end of the third inverter is connected with the control end of the third trigger.
7. The circuit of claim 1, wherein the signal generation circuit further comprises a failure detection circuit;
The output end of the oscillating signal of the frequency division feedback circuit is connected with the input end of the failure detection circuit, the failure detection circuit is used for carrying out frequency failure detection on the oscillating signal, the output end of the failure detection circuit is used for outputting a detection signal aiming at the oscillating signal, and the detection signal is used for indicating whether the oscillating signal has frequency failure or not.
8. The circuit of claim 7, wherein the failure detection circuit comprises a pulse generation circuit, a capacitive discharge ramp circuit, and a digital latch circuit;
The input end of the pulse generating circuit is the input end of the failure detection circuit, the output end of the pulse generating circuit is connected with the input end of the capacitor discharging ramp circuit, the output end of the capacitor discharging ramp circuit is connected with the input end of the digital latch circuit, and the output end of the digital latch circuit is the output end of the failure detection circuit.
9. The circuit of claim 8, wherein the capacitive discharge ramp circuit comprises a second capacitor, a third switching device, a fourth switching device, a fifth switching device, a sixth switching device, a seventh switching device;
The input end of the capacitor discharging ramp circuit comprises a control end of the third switching device and a control end of the fourth switching device, wherein the first end of the third switching device and the first end of the fourth switching device are both connected with a power supply voltage end, and the output end of the capacitor discharging ramp circuit comprises a second end of the third switching device and a second end of the fourth switching device;
The control end of the fifth switching device, the first end of the fifth switching device, the control end of the sixth switching device and the control end of the seventh switching device are respectively used for receiving input bias current, the second end of the fifth switching device is grounded, the first end of the sixth switching device is connected with the second end of the third switching device, the second end of the sixth switching device is grounded, the first end of the seventh switching device is connected with the second end of the fourth switching device, and the second end of the seventh switching device is grounded.
10. The circuit of claim 9, wherein the third switching device and the fourth switching device are P-type metal-oxide semiconductor field effect transistor, MOS, transistors of the fifth switching device, the sixth switching device, and the seventh switching device are N-type MOS.
CN202411204978.XA 2024-08-29 2024-08-29 Signal generating circuit Pending CN119109419A (en)

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CN202411204978.XA CN119109419A (en) 2024-08-29 2024-08-29 Signal generating circuit

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