CN118969840A - The original cell structure and process method of trench superjunction MOSFET - Google Patents
The original cell structure and process method of trench superjunction MOSFET Download PDFInfo
- Publication number
- CN118969840A CN118969840A CN202411009094.9A CN202411009094A CN118969840A CN 118969840 A CN118969840 A CN 118969840A CN 202411009094 A CN202411009094 A CN 202411009094A CN 118969840 A CN118969840 A CN 118969840A
- Authority
- CN
- China
- Prior art keywords
- trench
- epitaxial layer
- super junction
- gate
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 128
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000002513 implantation Methods 0.000 claims description 114
- 239000007924 injection Substances 0.000 claims description 77
- 238000002347 injection Methods 0.000 claims description 77
- 238000005530 etching Methods 0.000 claims description 73
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 70
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 70
- 238000005468 ion implantation Methods 0.000 claims description 68
- 239000004065 semiconductor Substances 0.000 claims description 59
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 25
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 18
- 238000000137 annealing Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 16
- 238000011049 filling Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 230000005684 electric field Effects 0.000 claims description 9
- 239000012300 argon atmosphere Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims 6
- 229910052759 nickel Inorganic materials 0.000 claims 4
- 238000000926 separation method Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 310
- 229910052782 aluminium Inorganic materials 0.000 description 37
- -1 Aluminum ions Chemical class 0.000 description 34
- 238000005516 engineering process Methods 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 230000008021 deposition Effects 0.000 description 9
- 238000000605 extraction Methods 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- WSNMPAVSZJSIMT-UHFFFAOYSA-N COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 Chemical compound COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 WSNMPAVSZJSIMT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000012995 silicone-based technology Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- LFQCEHFDDXELDD-UHFFFAOYSA-N tetramethyl orthosilicate Chemical compound CO[Si](OC)(OC)OC LFQCEHFDDXELDD-UHFFFAOYSA-N 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a primitive cell structure of a trench super junction MOSFET, which at least comprises two epitaxial layers on a substrate; the epitaxial layer comprises a grid electrode of the groove super junction MOSFET, and a super junction structure is arranged below the groove; the depth of the P column of the super junction structure is consistent with the thickness of an epitaxial layer where the P column is located, the side wall in the groove is provided with a gate dielectric layer with uniform thickness, or the lower part is provided with a thicker groove field oxide layer, the upper part is provided with a thinner gate dielectric layer, and the grid can be of an integral structure or a separation grid. The structure combines the advantages of the trench and the super-junction MOSFET cell structure, and greatly reduces the specific on-resistance of the super-junction MOSFET unit area. The process can produce MOSFET devices with the voltage of 600-10000V under a unified SiC process platform, greatly optimizes the performance of the MOSFET and reduces the cost problem that different voltage SiC MOSFET processes need to be independently developed.
Description
Technical Field
The invention relates to the field of semiconductor device and process manufacturing, in particular to a cell structure of a trench super junction MOSFET and a process method.
Background
The SiC MOSFET technology is a power semiconductor device technology based on silicon carbide materials, has excellent characteristics of high temperature, high voltage, high frequency and the like, and gradually becomes one of research hot spots of next-generation power electronic devices.
Silicon carbide has long been considered to have unique characteristics that make it superior to other commonly used semiconductor materials such as silicon (Si), gallium arsenide (GaAs), and indium phosphide (InP) formed semiconductor devices. Silicon carbide has a wide band gap, a high melting point, a low dielectric constant, a high breakdown field strength, a high thermal conductivity, and a high saturated electron drift velocity. These characteristics make it possible for devices made of silicon carbide to operate at higher temperatures, higher operating frequencies, and higher power levels, as well as other devices made of other semiconductor materials. Silicon carbide is a subverted technology, and with the development of new energy automobiles and photovoltaic energy storage fields, silicon-based technology is being replaced, and the silicon carbide is beginning to be widely focused on the market. The process and structure of SIC MOSFETs of different manufacturers are continuously advancing, and the product performance is also continuously improved.
When the power electronic device is in operation, the body diode of the SiC MOSFET device is often used as a freewheeling diode to work in the third quadrant, and the turn-on voltage of the body diode of the SiC MOSFET device is very high due to the fact that the forbidden band width of the SiC material is as high as 3.26eV, so that the loss when the SiC material is used as the freewheeling diode is greatly increased. After the body diode is forward conducted for a long time, the on-resistance and blocking capability of the MOSFET can be degraded; and the reverse recovery characteristic of the body diode is poor, so that quite large current peak and turn-off surge voltage can be generated in the process, and the semiconductor device can be damaged when the turn-on characteristic of the body diode is degraded and serious. After the body diode is forward conducted for a long time, the conduction characteristic of the body diode is degraded, and even the conduction resistance and blocking capability of the MOSFET are degraded.
Since 2010, the silicon carbide power MOSFET market has expanded significantly, and as SiC has replaced silicon technology in multiple markets such as automobiles, photovoltaics, railways, etc., many new participants have entered the market, hopefully achieving a two-digit composite annual growth rate. Typically, siC power MOSFETs operate at 1200 or 1700V, which is intended to replace IGBT technology in some areas.
The device structure of the SiC MOSFET mainly comprises: a channel region, source and drain regions, and a gate region. The channel region is composed of p-type SiC, the source region is composed of n+ type SiC, the drain region is composed of an n+ doped SiC substrate and a metal contact layer, and the gate region is composed of metal or Poly.
The conventional trench SiC MOSFET cell (pitch) structure, the deep trench and the Source SHIELD PLATE electrode can deplete the high-concentration N-type region in the reverse voltage-withstanding process of the device like a superjunction P column, so that the electric field of the gate oxide layer of the GATE TRENCH (gate trench) region is reduced, and meanwhile, the forward conduction of the device has lower specific on-Resistance (RSPA). For example, the P columns with the depth of 2 mu m are formed by implantation, and in the reverse voltage-resistant process of the device, the N-type region with higher concentration between the two P columns can be exhausted, so that the electric field of the grid oxide layer in the GATE TRENCH region is reduced, and meanwhile, the forward conduction of the device has lower specific on-resistance.
A vertical channel SiC MOSFET structure having low on-resistance and high temperature range features that it is formed on the C-face of a silicon carbide substrate, an N-drift layer is formed over an N+ substrate, and then a P-channel layer is formed. The trench gate penetrates the P-channel layer and forms an n+ source region. The metal source and drain electrodes are located at the top and bottom of the die, respectively. This trench architecture is sometimes referred to as a Μmos (U-gate) to distinguish it from a planar DMOS (VDMOS) design.
The Cree of the known LED illumination manufacturer focuses on the planar SiC MOSFET technology, three generations of products are developed, and the latest generation is switched to a trench gate structure. Other manufacturers, including Infrax, rohm, boshi, fuji, use trench or mMOS technology. In contrast, the intentional semiconductor (STMicroelectronics) is also focused on planar SiC MOSFET technology. The trench gate MOSFET structure of the roman company differs from the structure of the Μmos in that the third generation trench SIC MOSFET of the roman company uses some of the structural characteristics of some of the vertical trench SIC MOSFETs, the cell size of the fourth generation trench SIC MOSFET pitch structure of the roman company is reduced to 2 μm, and the cell size of the BOSCH TMOS trench SIC MOSFET pitch structure is 3.3 μm.
In recent years, siC MOSFET technology has been developed, mainly in the following aspects:
1. The device performance is improved: by optimizing the technological process of the SiC MOSFET and the pitch structure of the device, such as a groove structure, a super junction structure and the like, the performance improvement of the SiC MOSFET, such as low leakage current, high switching speed, low on-resistance, low switching loss and the like, is realized.
2. Improvement of packaging technology: packaging technology is one of the important factors affecting SiC MOSFET performance and reliability. At present, common SiC MOSFET packaging technologies comprise TO-220, TO-247, D2PAK and the like, and the latest packaging technologies adopt high-end technologies such as SiC substrate, silver-free solder, sintering and the like, so that the working junction temperature and heat dissipation performance of the device can be effectively improved.
3. Application expansion: siC MOSFET technology is widely used in the fields of electric automobiles, solar inverters, wind energy inverters, high-speed trains, power grid power transmission, and the like. As technology continues to develop, siC MOSFETs will find application in more application scenarios.
The development direction of the SiC MOSFET power device is to reduce the area of the device as much as possible under the condition of ensuring low specific on-resistance, improve the power density and reduce the cost.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a primitive cell structure of a trench super junction MOSFET, which has higher performance and more compact primitive cell structure.
The invention also solves the technical problem of providing a process method of the primitive cell structure of the trench super junction MOSFET.
In order to solve the above problems, the cell structure of the trench super junction MOSFET of the present invention includes:
providing a semiconductor substrate, wherein the semiconductor substrate comprises an epitaxial layer;
the epitaxial layer comprises a primitive cell structure of the trench super-junction MOSFET, wherein the trench forms a grid electrode of the super-junction MOSFET, and a super-junction structure is arranged below the trench;
The super junction structure comprises a P column and an N column; the P column is positioned right below the groove and is in abutting contact with the bottom surface of the groove; the N column is formed by the epitaxial layer;
The side wall of the groove is provided with a gate dielectric layer with uniform thickness, and the gate conductive material filled in the groove is electrically isolated from the epitaxial layer;
The epitaxial layer near the upper part of the groove is provided with a P well of the groove super junction MOSFET, and the surface epitaxial layer of the P well comprises a source N+ leading-out region of the groove super junction MOSFET and a P+ contact hole leading-out region of the P well which is in abutting contact with the source N+ leading-out region.
Further, the semiconductor substrate is a silicon carbide substrate, the thickness of the semiconductor substrate is 300 mu m, and the resistivity of the semiconductor substrate is 0.01-0.02 ohm cm -2; the epitaxial layer at least comprises two epitaxial layers, namely a second epitaxial layer and a third epitaxial layer; the super junction structure is formed in the second epitaxial layer, the third epitaxial layer is located on the second epitaxial layer, and the groove is located in the third epitaxial layer.
Further, the epitaxial layer further comprises a first epitaxial layer located between the second epitaxial layer and the semiconductor substrate to achieve a higher withstand voltage exceeding 1700V.
Further, the concentration and doping concentration of the P column of the super junction structure are matched with the doping concentration of an epitaxial layer forming the super junction structure with the P column, so that charge balance is achieved.
Further, in the epitaxial layer, the depth of the trench is 2-6 μm, and the depth of the P-pillar of the superjunction structure is 2-6 μm.
Further, the thickness of the second epitaxial layer in the epitaxial layers is 3 mu m, and the doping concentration is 3e 16-1 e17cm -3; the thickness of the second epitaxial layer is consistent with the implantation depth of the P column; the thickness of the third epitaxial layer is 3 mu m, and the doping concentration is 1e 16-1 e17cm -3.
Further, the gate dielectric layer is a thin gate oxide layer with uniform thickness, and the thickness of the gate oxide layer is 350-1200A.
Further, the surface of the epitaxial layer is also provided with a source metal layer, and the source metal layer is connected with the source N+ leading-out area and the P+ contact hole leading-out area through the contact hole.
The process method for manufacturing the primitive cell structure of the trench super junction MOSFET comprises the following process steps:
Providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate;
P-type ion implantation is carried out to form a P-well;
Forming a hard mask layer, carrying out a trench etching process, defining a trench region through the hard mask, etching the epitaxial layer to form a trench, and filling the trench to form a gate of the trench super junction MOSFET;
After the groove etching is finished, high-energy P-type ions are injected into the epitaxial layer at the bottom of the groove, and a P column with a certain depth is formed in the epitaxial layer at the bottom of the groove;
Forming a gate dielectric layer on the inner wall of the groove, filling a gate conductive material and etching back to form a gate of the super-junction MOSFET;
Photoetching and etching an N+ injection window, and performing N+ ion injection to form a source N+ leading-out region of a primitive cell structure of the trench super junction MOSFET in the P well; and photoetching and etching again to open an injection window of P+ and performing ion injection of P+ to form a P+ contact hole leading-out region of the P well.
Further, the semiconductor substrate is a silicon carbide substrate, the thickness of the silicon carbide substrate is 300 mu m, and the resistivity is 0.01-0.02 ohm cm -2.
Further, the P column with the super junction structure is formed by performing high-energy P-type ion implantation on the epitaxial layer at the bottom of the groove and is formed by performing multiple Al ion implantation; before the repeated Al ion implantation, a sacrificial oxide layer is formed in the groove, and then the repeated Al ion implantation of the P column with the super junction structure is carried out; the thickness of the sacrificial oxide layer is 300-1000A.
Further, the hard mask layer is any single material layer of an oxide layer, polysilicon and metallic nickel, or is formed by any combination; in the case of a single material layer, the oxide layer has a thickness of 4 to 5 μm or a thickness of 2 to 3 μm.
Further, the repeated Al ion implantation of the P column has an implantation depth of 2-6 mu m, and the implantation depth is consistent with the thickness of the second epitaxial layer; the energy range of the repeated Al ion implantation is 20-4250 KeV, the dosage range is 5.5e11-4.8e12, and the implantation temperature is 500 ℃.
Further, the multi-time Al ion implantation further comprises an annealing process after the implantation is completed, and the annealing condition is 1700 ℃ for 30 minutes under the argon atmosphere.
Further, the implantation energy range of the ion implantation of the source electrode N+ leading-out region is 40-90 KeV, the implantation dosage is 4.5e14-1.0e15, and the implantation temperature is 500 ℃; the injection condition of the P well is adjusted according to the thickness of different gate dielectric layers and the requirements of threshold values, the injection energy range is 50-300 KeV, and the injection dosage is 1.0e12-1.5e12; the implantation window of the P+ contact hole extraction region is used for determining implantation energy and dose according to the distance between the P+ implantation window and the trench gate, and the implantation energy is lower as the required distance is smaller; the implantation energy range is 60-100 KeV, the implantation dosage is 1.0e15, and the implantation temperature is 500 ℃.
Further, the process step further comprises the steps of depositing a metal layer on the surface of the epitaxial layer and etching to form source metal, wherein the source metal is connected with the source N+ leading-out region and the P+ contact hole leading-out region.
The invention also provides a primitive cell structure of the trench super junction MOSFET, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises an epitaxial layer;
the epitaxial layer comprises a primitive cell structure of the trench super-junction MOSFET, wherein the trench forms a grid electrode of the super-junction MOSFET, and a super-junction structure is arranged below the trench;
The super junction structure comprises a P column and an N column; the P column is positioned right below the groove and is in abutting contact with the bottom surface of the groove; the N column is formed by the epitaxial layer;
The groove comprises a grid structure of the groove super junction MOSFET; the grid structure comprises a grid and an insulating medium layer between the grid and the epitaxial layer; the gate has a section with a shape of a torch-shaped section with a wide upper part and a narrow lower part, a thinner gate dielectric layer is arranged between the gate of the torch head part with a wider upper part and the side wall of the groove, and a thicker groove field oxide layer is arranged between the gate of the torch tail handle with a narrower lower part and the side wall of the groove;
The epitaxial layer near the upper part of the groove is provided with a P well of the groove super junction MOSFET, and the surface epitaxial layer of the P well comprises a source N+ leading-out region of the groove super junction MOSFET and a P+ contact hole leading-out region of the P well which is in abutting contact with the source N+ leading-out region.
Further, the semiconductor substrate is a silicon carbide substrate, the thickness of the semiconductor substrate is 300 mu m, and the resistivity of the semiconductor substrate is 0.01-0.02 ohm cm < -2 >; the epitaxial layer at least comprises two epitaxial layers, namely a second epitaxial layer and a third epitaxial layer; the super junction structure is formed in the second epitaxial layer, the third epitaxial layer is located on the second epitaxial layer, and the groove is located in the third epitaxial layer.
Further, the epitaxial layer also comprises a first epitaxial layer which is positioned between the second epitaxial layer and the semiconductor substrate so as to realize higher withstand voltage exceeding 1700V.
Further, the concentration and doping concentration of the P column of the super junction structure are matched with the doping concentration of an epitaxial layer forming the super junction structure with the P column, so that charge balance is achieved; the depth of the P column in the super junction structure is consistent with the thickness of the second epitaxial layer, so that the P column and N type charges are balanced when the device is in reverse voltage resistance, the high-concentration N type region is exhausted, and the electric field intensity of the gate dielectric layer of the trench gate region is reduced.
Further, in the epitaxial layer, the depth of the trench is 2-6 μm, and the depth of the P column of the superjunction structure, i.e., the thickness of the second epitaxial layer is 2-6 μm.
Further, the height of the gate of the torch-shaped head part at the upper part of the gate is 0.6-1.5 mu m, and the thickness of the thinner gate dielectric layer between the gate and the side wall of the groove is 350-1200A; the thickness of the thicker trench field oxide layer between the gate electrode of the lower narrower and longer torch tail handle and the trench sidewall is 1000-3000A.
Further, the gate dielectric layer is a gate oxide layer, and the forming process is a thermal oxidation process; the forming process of the trench field oxide layer is thermal oxidation or combination of deposition process and oxidation process.
Further, the grid electrode is made of polysilicon.
Further, the P column is formed by combining Al ions with different implantation energies and different implantation doses after high-temperature implantation.
The process method for manufacturing the primitive cell structure of the trench super junction MOSFET comprises the following process steps:
Providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate;
P-type ion implantation is carried out to form a P-well;
forming a hard mask layer, carrying out a trench etching process, defining a trench region through the hard mask, etching the epitaxial layer to form a trench, and filling the trench to form a gate of the trench super junction MOSFET;
After the groove etching is finished, implanting high-energy P-type ions into the epitaxial layer at the bottom of the groove, and forming a P column with a certain depth in the epitaxial layer at the bottom of the groove;
Forming a thicker trench field oxide layer on the inner wall of the trench, filling a gate conductive material, back-etching to form a tail handle structure at the lower part of the torch-shaped gate, forming a thinner gate dielectric layer at the upper part of the trench, then continuously filling the gate conductive material, back-etching to be flush with the surface of the epitaxial layer, and integrally forming a gate structure with a torch-shaped section, namely, a thin gate dielectric layer is arranged between the gate of the upper part of the torch head and the side wall of the trench, and a thick trench field oxide layer is arranged between the gate of the lower part of the torch tail handle and the side wall of the trench;
Photoetching and etching an N+ injection window, and performing N+ ion injection to form a source N+ leading-out region of a primitive cell structure of the trench super junction MOSFET in the P well; and photoetching and etching again to open an injection window of P+ and performing ion injection of P+ to form a P+ contact hole leading-out region of the P well.
Further, the semiconductor substrate is a silicon carbide substrate, the thickness of the semiconductor substrate is 300 mu m, and the resistivity of the semiconductor substrate is 0.01-0.02 ohm cm -2.
Further, the epitaxial layer at least comprises a second epitaxial layer and a third epitaxial layer; the second epitaxial layer contains the super junction structure of the super junction MOSFET, and the third epitaxial layer contains the gate structure of the super junction MOSFET.
Further, the epitaxial layer further comprises a first epitaxial layer located between the second epitaxial layer and the semiconductor substrate to achieve a higher withstand voltage exceeding 1700V.
Further, the thickness of the second epitaxial layer is 3um, and the doping concentration is 2e 16-1 e17cm & lt-3 & gt; the thickness of the third epitaxial layer is 3 mu m, and the doping concentration is 1e 16-1 e17cm < -3 >.
Further, the thickness of the first epitaxial layer is 4 mu m, and the doping concentration is 8e 15-1 e16cm < -3 >.
Further, the P column with the super junction structure is formed by performing high-energy P-type ion implantation on the epitaxial layer at the bottom of the groove and is formed by performing multiple Al ion implantation; before the repeated Al ion implantation, a sacrificial oxide layer is formed in the groove, and then the repeated Al ion implantation of the P column with the super junction structure is carried out; the thickness of the sacrificial oxide layer is 300-1000A.
Further, the hard mask layer is any single material layer of an oxide layer, polysilicon and metallic nickel, or is formed by any combination; in the case of a single material layer, the oxide layer has a thickness of 4 to 5 μm or a thickness of 2 to 3 μm.
Further, the repeated Al ion implantation of the P column has an implantation depth of 2-6 mu m, and the implantation depth is consistent with the thickness of the second epitaxial layer; the energy range of the repeated Al ion implantation is 20-4250 Kev, the dosage range is 5.5e11-4.8e12, and the implantation temperature is 500 ℃.
Further, the multi-time Al ion implantation further comprises an annealing process after the implantation is completed, and the annealing condition is 1700 ℃ for 30 minutes under the argon atmosphere.
Further, a thicker trench field oxide layer is formed on the inner wall of the trench, the thickness of the trench field oxide layer is 1000-3000A, etching is carried out after the grid electrode conductive material is deposited, the etching depth is 0.6-1.5 mu m downwards from the top surface of the epitaxial layer, a channel region is formed by wet etching the thickness of the trench field oxide layer by 0.3 mu m, and then the grid electrode conductive material is removed; and then forming a gate dielectric layer with the thickness of 350-1200A on the inner wall of the upper part of the groove, depositing polysilicon and etching back to form a gate with a complete structure.
Further, the implantation energy range of the ion implantation of the source electrode N+ leading-out region is 40-90 KeV, the implantation dosage is 4.5e14-1.0e15, and the implantation temperature is 500 ℃; the injection condition of the P well is adjusted according to the thickness of different gate dielectric layers and the requirements of threshold values, the injection energy range is 50-300 KeV, and the injection dosage is 1.0e12-1.5e12; the implantation window of the P+ contact hole extraction region is used for determining implantation energy and dose according to the distance between the P+ implantation window and the trench gate, and the implantation energy is lower as the required distance is smaller; the implantation energy range is 60-100 KeV, the implantation dosage is 1.0e15, and the implantation temperature is 500 ℃.
Further, the process step further comprises the steps of depositing a metal layer on the surface of the epitaxial layer and etching to form source metal, wherein the source metal is connected with the source N+ leading-out region and the P+ contact hole leading-out region.
The invention also provides a primitive cell structure of the trench super junction MOSFET, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises an epitaxial layer;
the epitaxial layer comprises a primitive cell structure of the trench super-junction MOSFET, wherein the trench forms a grid electrode of the super-junction MOSFET, and a super-junction structure is arranged below the trench;
The super junction structure comprises a P column and an N column; the P column is positioned right below the groove and is in abutting contact with the bottom surface of the groove; the N column is formed by the epitaxial layer;
the groove comprises a grid structure of the groove super junction MOSFET; the grid structure is a separated grid structure formed by two parts which are independent from each other up and down; the shielding grid electrode positioned at the lower part of the groove is in an elongated rod shape, and a thicker groove field oxide layer is arranged between the shielding grid electrode and the side wall of the groove; the transverse width of the device grid electrode positioned at the upper part of the groove is larger than that of the shielding grid electrode, and the longitudinal length of the device grid electrode is smaller than that of the shielding grid electrode; a gate dielectric layer with a thickness thinner than that of the trench field oxide layer is arranged between the device gate and the trench side wall;
The epitaxial layer near the upper part of the groove is provided with a P well of the groove super junction MOSFET, and the surface epitaxial layer of the P well comprises a source N+ leading-out region of the groove super junction MOSFET and a P+ contact hole leading-out region of the P well which is in abutting contact with the source N+ leading-out region.
Further, the semiconductor substrate is a silicon carbide substrate, the thickness of the semiconductor substrate is 300 mu m, and the resistivity of the semiconductor substrate is 0.01-0.02 ohm cm < -2 >; the epitaxial layer at least comprises two epitaxial layers, namely a second epitaxial layer and a third epitaxial layer; the super junction structure is formed in the second epitaxial layer, the third epitaxial layer is located on the second epitaxial layer, and the groove is located in the third epitaxial layer.
Further, the epitaxial layer further comprises a first epitaxial layer located between the second epitaxial layer and the semiconductor substrate to achieve a higher withstand voltage exceeding 1700V.
Further, the thickness of the second epitaxial layer is 3um, and the doping concentration is 2e 16-1 e17cm & lt-3 & gt; the thickness of the third epitaxial layer is 3 mu m, and the doping concentration is 1e 16-1 e17cm < -3 >.
Further, the thickness of the first epitaxial layer is 4 mu m, and the doping concentration is 8e 15-1 e16cm < -3 >.
Further, the depth of the groove is 2-6 mu m, the thickness of the second epitaxial layer is consistent with the depth of the P column of the super junction structure, so that the electric field intensity of the gate dielectric layer of the groove is reduced while the N-type region of the high-concentration epitaxial layer is exhausted.
Further, the P column is formed by combining Al ions with different implantation energies and different implantation doses after high-temperature implantation.
Further, the longitudinal length of the device grid electrode at the upper part of the groove is 0.6-1.5 mu m, and the thickness of the grid dielectric layer is 350-1200A; the thickness of the trench field oxide layer at the periphery of the shielding grid electrode is 1000-3000A.
Further, the device gate is the gate of the superjunction MOSFET, and the shielding gate and the source electrode are in the same potential and are connected with the source electrode through source electrode metal.
Further, the gate dielectric layer is a gate oxide layer, and the forming process is a thermal oxidation process; the forming process of the trench field oxide layer is thermal oxidation or combination of deposition process and oxidation process.
Further, the gate dielectric layer is a gate oxide layer, and the gate is made of polysilicon.
The process method for manufacturing the primitive cell structure of the trench super junction MOSFET comprises the following process steps:
Providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate;
P-type ion implantation is carried out to form a P-well;
forming a hard mask layer, carrying out a trench etching process, defining a trench region through the hard mask, etching the epitaxial layer to form a trench, and filling the trench to form a gate of the trench super junction MOSFET;
After the groove etching is finished, implanting high-energy P-type ions into the epitaxial layer at the bottom of the groove, and forming a P column with a certain depth in the epitaxial layer at the bottom of the groove;
Forming a thicker trench field oxide layer on the inner wall of the trench, then depositing and filling a gate conductive material, and etching back to form a lower shielding gate; then wet etching the trench field oxide layer to a certain thickness to form a channel region; forming a thin gate dielectric layer, depositing a gate conductive material and etching back to form a device gate; the formed shielding grid electrode and the device grid electrode are electrically isolated from each other;
Photoetching and etching an N+ injection window, and performing N+ ion injection to form a source N+ leading-out region of a primitive cell structure of the trench super junction MOSFET in the P well; and photoetching and etching again to open an injection window of P+ and performing ion injection of P+ to form a P+ contact hole leading-out region of the P well.
Further, the semiconductor substrate is a silicon carbide substrate, the thickness of the silicon carbide substrate is 300 mu m, and the resistivity is 0.01-0.02 ohm cm < -2 >.
Further, the epitaxial layer at least comprises a second epitaxial layer and a third epitaxial layer; the second epitaxial layer contains the super junction structure of the super junction MOSFET, the third epitaxial layer is provided with a groove, and the groove contains the grid structure of the separation grid structure of the super junction MOSFET.
Further, the epitaxial layer further comprises a first epitaxial layer located between the second epitaxial layer and the semiconductor substrate to achieve a higher withstand voltage exceeding 1700V.
Further, the thickness of the second epitaxial layer is 3um, and the doping concentration is 2e 16-1 e17cm & lt-3 & gt; the thickness of the third epitaxial layer is 3 mu m, and the doping concentration is 1e 16-1 e17cm < -3 >.
Further, the thickness of the first epitaxial layer is 4 mu m, and the doping concentration is 8e 15-1 e16cm < -3 >.
Further, the width of the trench and the thickness of the trench field oxide layer or the gate dielectric layer at two sides of the trench need to be matched with the thickness and the concentration of the third epitaxial layer; the thickness of the third epitaxial layer is consistent with the depth of the groove, and the thickness of the second epitaxial layer is consistent with the depth of the P column formed by multiple high-energy injection; the high-concentration N-type region is exhausted, and meanwhile, the electric field of the gate dielectric layer of the trench gate region is reduced.
Further, the P column with the super junction structure is formed by performing high-energy P-type ion implantation on the epitaxial layer at the bottom of the groove and is formed by performing multiple Al ion implantation; before the repeated Al ion implantation, forming a sacrificial oxide layer in the trench, and then carrying out the repeated Al ion implantation to form a P column with a super junction structure; the thickness of the sacrificial oxide layer is 300-1000A.
Further, the hard mask layer is any single material layer of an oxide layer, polysilicon and metallic nickel, or is formed by any combination; in the case of a single material layer, the oxide layer has a thickness of 4 to 5 μm or a thickness of 2 to 3 μm.
Further, the repeated Al ion implantation of the P column has an implantation depth of 2-6 mu m, and the implantation depth is consistent with the thickness of the second epitaxial layer; the energy range of the repeated Al ion implantation is 20-4250 KeV, the dosage range is 5.5e11-4.8e12, and the implantation temperature is 500 ℃.
Further, after the P column is formed by the multiple Al ion implantation, an annealing process is further included, and the annealing condition is 1700 ℃/30min under the argon atmosphere.
Further, a thicker trench field oxide layer is formed on the inner wall of the trench, the thickness of the trench field oxide layer is 1000-3000A, the etching is performed after the grid electrode conductive material is deposited, and the etching depth is 0.6-1.5 mu m downwards from the top surface of the epitaxial layer, so that a lower shielding electrode is formed; wet etching the thickness of the groove field oxide layer to form a channel region with the thickness of 0.2-0.4 mu m; then forming a gate dielectric layer with the thickness of 350-1200A on the inner wall of the upper part of the groove, depositing polysilicon and etching back to form the upper part of the device grid electrode 6.
Further, the implantation energy range of the ion implantation of the source electrode N+ leading-out region is 40-90 KeV, the implantation dosage is 4.5e14-1.0e15cm < -2 >, and the implantation temperature is 500 ℃; the injection condition of the P well is adjusted according to the thickness and threshold requirements of different gate dielectric layers, the injection energy range is 50-300 KeV, and the injection dosage is 1.0e12-1.5e12 cm < -2 >; the implantation window of the P+ contact hole extraction region is used for determining implantation energy and dose according to the distance between the P+ implantation window and the trench gate, and the implantation energy is lower as the required distance is smaller; the implantation energy range is 60-100 KeV, the implantation dosage is 1.0e15cm < -2 >, and the implantation temperature is 500 ℃.
Further, the process step further comprises the steps of depositing a metal layer on the surface of the epitaxial layer and etching to form source metal, wherein the source metal is connected with the source N+ leading-out area and the P+ contact hole leading-out area; the source metal is also connected with the shielding electrode, and the shielding electrode and the source are in the same potential.
The cell structure of the trench super-junction MOSFET combines the advantages of the trench and the super-junction MOSFET cell structure, and greatly reduces the specific on-Resistance (RSPA) of the super-junction MOSFET unit area. By utilizing the primitive cell structure and the process, the MOSFET device with the voltage of 600-10000V can be produced under a unified SIC process platform, the performance of the MOSFET is greatly optimized, and the cost problem that different voltage SIC MOSFET processes need to be independently developed is solved.
Drawings
Fig. 1 shows a primitive cell structure of a trench superjunction MOSFET with a uniform thickness gate dielectric layer.
Fig. 2 is a schematic diagram of a cell structure of a trench superjunction MOSFET with a second structure according to the present invention, having a torch-shaped gate with a wide top and a narrow bottom.
Fig. 3 is a schematic diagram of a cell structure of a trench superjunction MOSFET with a split gate structure according to a third embodiment of the present invention.
Description of the reference numerals
1 Is an n+ extraction region (Source), 2 is a p+ contact hole extraction region, 3 is a Pwell (P-well), 4 is Source metal, 5 is a gate dielectric layer, 6 is a gate, 7 is a column implant region, 8 is a first epitaxial layer, 9 is a second epitaxial layer, 10 is a third epitaxial layer, 11 is a substrate, 12 is a trench field oxide layer, and 13 is a Source field plate.
Detailed Description
The following description of the embodiments of the present invention will be given with reference to the accompanying drawings, in which the technical solutions of the present invention are clearly and completely described, but the present invention is not limited to the following embodiments. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. Advantages and features of the invention will become more apparent from the following description and from the claims. It is noted that the drawings are in a very simplified form and use non-precise ratios for convenience and clarity in assisting in illustrating embodiments of the invention. All other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present invention.
This application may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for the same elements throughout. In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The embodiment of the invention provides a primitive cell structure of a trench super junction MOSFET with three structures, wherein the primitive cell structures all adopt a 3-layer epitaxial layer structure, and higher voltage-withstanding capability can be realized. In some cases below 1700V, a dual-layer epitaxial structure may be used, i.e. the first epitaxial layer 8 is omitted in the embodiments of the present invention.
The 3-layer EPI and the structural parameters adopted by the invention are not limited to the 1200V SiC MOSFET structural parameters listed below, wherein the thickness of the SiC substrate is 300 mu m, and the resistivity is 0.01-0.02ohm cm < -2 >. The thickness of the first epitaxial layer 8 is 4 mu m, and the doping concentration is 8e 15-1 e16; the thickness of the second epitaxial layer 9 is 3 mu m, and the doping concentration is 3e 16-1 e17; the thickness of the third epitaxial layer 10 is 3 mu m, and the doping concentration is 1e 16-1 e17; taking a 1200V SiC MOSFET as an example, the total thickness of the tri-epitaxial layer is approximately 10 μm. The primitive cell structure and the process can produce SIC MOSFET devices of 600-10000V and above under a unified process platform.
As shown in FIG. 1, the trench super-junction MOSFET structure of the first structure is mainly characterized in that a trench gate with a gate dielectric layer with uniform thickness is formed, and another epitaxial layer below the trench gate comprises a P column with a super-junction structure.
Specifically, fig. 1 has three epitaxial layers including a first epitaxial layer 8, a second epitaxial layer 9, and a third epitaxial layer 10 in this order on a SiC substrate 11. The second epitaxial layer 9 contains the super junction structure of the super junction MOSFET, the super junction structure is an N column formed by an N type epitaxial layer, and a P column 7 of the super junction structure is arranged right below the groove. The P-pillar 7 is formed by implanting P-type ions (such as Al) at the bottom of the trench and annealing the P-type ions. The depth of the P column is consistent with the thickness of the second epitaxial layer. The concentration of the P column is matched with the doping concentration of an epitaxial layer forming a super junction structure with the P column, a groove reaching the upper part of charge balance is positioned in a third epitaxial layer, a gate oxide layer with uniform thickness is attached to the inside of the groove to serve as a gate dielectric layer 5, for example, the thickness of the gate oxide layer is generally 350-1200A. Polysilicon within the trench forms a trench-type gate of the MOSFET.
The surface layer of the third epitaxial layer is provided with a P well 3, and meanwhile, two sides of the groove are respectively provided with a source N+ leading-out area 1 and a P+ contact hole leading-out area 2. The epitaxial layer surface also has a source metal layer 4. The source metal layer 4 is connected with the source N+ leading-out region 1 and the P+ contact hole leading-out region 2 through contact holes.
As shown in fig. 2, the trench super junction MOSFET structure of the second structure provided by the invention has the main distinguishing characteristic that the lower part of the trench is provided with a thick field oxide layer compared with the structure shown in fig. 1, so that the cross section of a grid electrode in the trench is in a torch shape with a wide upper part and a narrow lower part. The other epitaxial layer below the trench gate still comprises a super junction structure, and a P column of the super junction structure is positioned right below the trench. A thin gate oxide layer is arranged between the gate of the torch head and the side wall of the groove, and the thickness of the thin gate oxide layer is 350-1200A. A thick field oxide layer 12 is arranged between the gate electrode at the tail handle of the torch and the side wall of the groove, and the thickness of the field oxide layer is 1000-3000A. Also, it may be determined whether the first epitaxial layer 8 is required according to the actual voltage-withstanding requirement of the device.
The depth of the P column of the super junction structure is consistent with the structure, the depth of the P column is consistent with the thickness of the second epitaxial layer, and the doping concentration requirement of N-type region depletion is met.
As shown in fig. 3, in the trench super-junction MOSFET structure of the third structure provided by the present invention, compared with the first structure shown in fig. 1 and the second structure shown in fig. 2, the main difference of the third structure is that the trench gate adopts a split gate structure, that is, the gate in the trench is divided into two gates with upper and lower parts independent of each other, that is, the head of the torch-shaped gate of the second structure shown in fig. 2 is separated from the handle body. The upper part in the groove is a device grid electrode 6, and the lower part in the groove is a shielding electrode 13. A thick trench field oxide layer 12 is formed between the shield electrode 13 and the trench sidewall and between the shield electrode and the device gate 6 above. The shielding electrode 13 and the device grid electrode 6 are made of polysilicon, and are formed by step deposition and back etching. The thickness of the gate dielectric layer 5 and the trench field oxide layer 12 are consistent with those of the first structure and the second structure. The shield electrode 13 is connected to the source electrode through the source metal and is at the same potential as the source electrode.
The super junction structure is still arranged below the groove, the P column of the super junction structure is arranged right below the groove, the depth of the P column is consistent with the thickness of the second epitaxial layer where the super junction structure is arranged, and the concentration of the P column also meets the doping concentration requirement of the depletion of the N type region.
The above is the primitive cell structure of the three trench super junction MOSFETs provided by the embodiment of the invention. The differences between them are mainly concentrated in the part of the trench gate, with the topography of the different trench gates.
The SiC MOSFET combines the advantages of the groove and the super-junction SiC MOSFET primary cell structure, and greatly reduces the specific on-Resistance (RSPA) of the unit area of the SiC MOSFET. The dimension of the primitive cell structure is 1.0-3.0 mu m, and the depth of the groove is 2-6 mu m; the depth of the super junction P column is 2-6 mu m.
The trench super junction MOSFET with the structure can be manufactured by adopting the following embodiment process, and the main differences of the three structures are concentrated on the part of the trench gate, and the main process steps are the same. In the embodiment of the manufacturing process of the present invention, a three-layer epitaxial layer structure is adopted, and in some cases, the first epitaxial layer 8 may be omitted. The method comprises the following specific steps:
1. First, an N-type epitaxial layer SiC substrate wafer with three epitaxial layers is prepared. The thickness of the SiC substrate of the 1200V trench super junction SiC MOSFET is 300 mu m, and the resistivity is 0.01-0.02 ohm cm < -2 >.
The thickness of the first epitaxial layer 8 is 4 mu m, and the doping concentration is 8e 15-1 e16cm < -3 >; the thickness of the second epitaxial layer 9 is 3 mu m, and the doping concentration is 2e 16-1 e17cm < -3 >; the thickness of the third epitaxial layer 10 is 3 μm, and the doping concentration is 1e 16-1 e17cm < -3 >. The total thickness of the three epitaxial layers of the 1200V SiC MOSFET is 10 μm.
If the super junction SiC MOSFET with 650V grooves is adopted, the first epitaxial layer 8 is omitted. The thickness of the SiC substrate is 300 mu m, and the doping concentration is 0.01-0.02ohm cm < -3 >. The thickness of the second epitaxial layer 9 is 3 mu m, and the doping concentration is 2e 16-1 e17cm < -3 >; the thickness of the third epitaxial layer 10 is 3 μm, and the doping concentration is 1e 16-1 e17cm < -3 >. The total thickness of the two epitaxial layers of the 650V SiC MOSFET is 6 mu m.
Namely: a set of epitaxial layer parameters selected for a 1200V SiC MOSFET:
first epitaxial layer: thickness 4 μm, doping concentration 1e16;
second epitaxial layer: thickness 3 μm, doping concentration 1e17;
And a third epitaxial layer: thickness 3 μm, doping concentration 4e16;
a set of epitaxial layer parameters selected for 650V SiC MOSFETs:
First epitaxial layer: thickness 0 μm;
second epitaxial layer: thickness 3 μm, doping concentration 1e17;
And a third epitaxial layer: thickness 3 μm, doping concentration 4e16;
then ion implantation is performed to form a P-well 3, and a source n+ extraction region 1 and a p+ contact hole extraction region 2.
The implantation conditions of the Pwell are to adjust the implantation dose according to different gate oxide thickness and threshold Vth requirements:
The first implantation, the Aluminum ion implantation energy is 50KeV, and the implantation dosage is 1.0e12cm < -2 >;
the second implantation, the Aluminum ion implantation energy is 150KeV, the implantation dosage is 1.5e12cm < -2 >;
And thirdly, injecting Aluminum ions with the injection energy of 300KeV and the injection dosage of 1.5e12cm < -2 >.
High temperature implantation conditions for source n+ extraction region 1:
the first injection, nitrogen 40Kev 4.5e14cm-2, 500 ℃;
A second injection, nitrogen 70Kev 6.0e14 cm-2,500 ℃;
a third injection, nitrogen 90Kev 1.0e15 cm-2,500 ℃;
The p+ contact hole extraction region 2 of the Pwell is implanted, and an implantation window is formed by photoetching and etching a hard mask.
P+ injection conditions: the implantation energy and the dose are determined according to the P+ implantation window and the space between the trench gates, and the implantation energy is lower when the required space is smaller.
The first injection, the Aluminum ion, the injection energy is 60KeV, the injection dosage is 1.0e15cm < -2 >, and the temperature is 500 ℃;
The second implantation, aluminum ion implantation energy of 100KeV, implantation dose of 1.0e15cm < -2 >, 500 ℃.
2. A trench gate and superjunction structure fabrication process. The trench process adopts the conventional trench SiC MOSFET cell structure forming process. After the groove is formed, high-energy P-type impurities (AL) are introduced and injected into the second epitaxial layer at the bottom of the groove to form a super junction P column;
The manufacturing process of the trench gate with the first structure comprises the following steps:
And etching the groove, and forming a hard mask. The hard mask is formed by single or combination of oxide layer/Poly/metallic nickel. The thickness of the hard mask is generally 2-6 μm, and the highest implantation energy of the P column with the depth of 3 μm is about 4MeV, and the thickness of the hard mask is 4-5 μm of oxide layer or 2-3 μm of metallic nickel. The hard mask serves as a shielding layer for trench etching and P-pillar ion implantation.
And opening a groove etching window of the hard mask, and etching in the third epitaxial layer to form a groove with the depth of 2-6 mu m. And then forming an oxidation process of a sacrificial oxide layer with the thickness of 300-1000A in the groove and performing wet etching to remove the sacrificial oxide layer so as to eliminate the damage defect of the epitaxial layer caused by the groove etching.
P column injection of the multi-time super junction structure at the lower part of the groove is carried out:
super junction P is injected, high-energy high-temperature injection is carried out for many times, different epitaxial doping is matched with different injection doses, and super junction charge balance is achieved:
The first injection, aluminum ions, 20Kev 5.5e11.500 ℃;
injecting Aluminum ions for the second time, wherein the temperature is 40Kev 1.0e12 500C ℃;
injecting Aluminum ions for the third time, wherein the temperature is 100Kev 2.0e12 500 ℃;
Fourth implantation, aluminum ions, 200Kev 2.2e12 500 ℃;
Fifth injection, aluminum ions, 320Kev 2.8e12 500 ℃;
A sixth injection, aluminum ions, 480Kev 3.4e12 500 ℃;
seventh injection, aluminum ions, 680Kev 4.0e12 500 ℃;
Eighth injection, aluminum ions, 950Kev 4.6e12 500 ℃;
ninth injection, aluminum ions, 1250Kev 4.6e12 500 ℃;
Tenth injection, aluminum ions, 1600Kev 4.6e12 500 ℃;
eleventh implantation, aluminum ions, 2000Kev 4.8e12 500 ℃;
twelfth implantation, aluminum ions, 2500Kev 4.8e12 500 ℃;
Thirteenth injection, aluminum ions, 3000Kev 4.8e12 500 ℃;
fourteenth implantation, aluminum ions, 3500Kev 4.8e12 500 ℃;
fifteenth implantation, aluminum ions, 4000Kev 4.8e12 500 ℃;
sixteenth implantation, aluminum ions, 4250Kev 2.0e12 500 ℃.
A thermal anneal is performed after the implantation is completed, annealing conditions: under Ar atmosphere, 1700 ℃ for 30 min.
A trench gate is then formed within the trench. A gate oxide layer 5 with a thickness of 350-1200A is formed by a thermal oxidation process, a layer of 12000A is deposited to fill the trench, and then the polysilicon in the trench is etched back to a position slightly lower than the surface of the epitaxial layer to form a gate.
For structure two:
the manufacturing process of the trench gate with the structure II comprises the following steps:
And etching the groove, and forming a hard mask. The hard mask is formed by single or combination of oxide layer/Poly/metallic nickel. The thickness of the hard mask is generally 2-6 μm, and the highest implantation energy of the P column with the depth of 3 μm is about 4MeV, and the thickness of the hard mask is 4-5 μm of oxide layer or 2-3 μm of metallic nickel. The hard mask serves as a shielding layer for trench etching and P-pillar ion implantation.
And opening a groove etching window of the hard mask, and etching in the third epitaxial layer to form a groove with the depth of 2-6 mu m. And then forming an oxidation process of a sacrificial oxide layer with the thickness of 300-1000A in the groove and performing wet etching to remove the sacrificial oxide layer so as to eliminate the damage defect of the epitaxial layer caused by the groove etching.
P injection of the multi-time super junction structure at the lower part of the groove is carried out:
super junction P is injected, high-energy high-temperature injection is carried out for many times, different epitaxial doping is matched with different injection doses, and super junction charge balance is achieved:
The first injection, aluminum ions, 20Kev 5.5e11.500 ℃;
the second implantation, aluminum ions, 40Kev 1.0e12, 500 ℃;
injecting Aluminum ions for the third time, wherein the temperature is 100Kev 2.0e12 500 ℃;
Fourth implantation, aluminum ions, 200Kev 2.2e12 500 ℃;
Fifth injection, aluminum ions, 320Kev 2.8e12 500 ℃;
A sixth injection, aluminum ions, 480Kev 3.4e12 500 ℃;
seventh injection, aluminum ions, 680Kev 4.0e12 500 ℃;
Eighth injection, aluminum ions, 950Kev 4.6e12 500 ℃;
ninth injection, aluminum ions, 1250Kev 4.6e12 500 ℃;
Tenth injection, aluminum ions, 1600Kev 4.6e12 500 ℃;
eleventh implantation, aluminum ions, 2000Kev 4.8e12 500 ℃;
twelfth implantation, aluminum ions, 2500Kev 4.8e12 500 ℃;
Thirteenth injection, aluminum ions, 3000Kev 4.8e12 500 ℃;
fourteenth implantation, aluminum ions, 3500Kev 4.8e12 500 ℃;
fifteenth implantation, aluminum ions, 4000Kev 4.8e12 500 ℃;
sixteenth implantation, aluminum ions, 4250Kev 2.0e12 500 ℃.
A thermal anneal is performed after the implantation is completed, annealing conditions: under Ar atmosphere, 1700 ℃ for 30min.
A trench gate is then formed within the trench. Firstly oxidizing to form a groove field oxide layer 12 with the thickness of 1000-3000A, then depositing a layer of polysilicon with the thickness of 12000A, back etching the polysilicon to the surface of the SiC epitaxial layer by 0.6-1.5 mu m, etching the groove field oxide layer by a wet method by 0.23 mu m to form a thin gate oxide channel region, and then back etching the polysilicon layer by the wet method to remove the polysilicon at the upper part. And forming a gate oxide layer 5 with the thickness of 350-1200A by thermal oxidation, filling polysilicon, and etching back to form a complete device gate.
For structure three:
For the primitive cell structure III of the trench super junction SiC MOSFET, the trench etching and P column injection processes are the same as the processes described above, and when the structure process in the trench is carried out, a layer of trench Field Oxide layer 12 with the thickness of 1000-3000A is formed by oxidation, then polysilicon with the thickness of 12000A is deposited, the polysilicon is etched back to 0.6-1.5 mu m below the surface of the SiC epitaxial layer, and Field Oxide etching is carried out by a wet method for 0.2-0.4 mu m to form a thin gate Oxide channel region.
The gate oxide layer 5 is grown and polysilicon of the device gate 6 is filled and etched back. The thickness of the gate oxide layer is 350-1200A, the gate oxide layer can be generated by dry oxygen, wet oxygen or the combination of the dry oxygen and the wet oxygen, and then N2O or NO is nitrided; the gate Oxide layer may also be formed by thermally oxidizing a thin Oxide layer and then depositing Oxide at a high temperature. The polysilicon filling of the device gate 6 is to deposit a layer of 12000 a thickness polysilicon and then etch back to 0.05-0.15 μm below the surface of the SiC epitaxial layer. Unlike structure two, the present structure forms two independent gates, a lower shield gate 13, and an upper device gate 6. The potential of the shielding electrode is the same as the potential of the source electrode, and the shielding electrode can be directly connected to the source electrode through a contact hole in the layout design.
Then the subsequent process is carried out, and the process steps of the three structures are basically the same:
and depositing a dielectric layer ILD and etching a source contact hole.
The deposition thickness of the dielectric layer ILD is 4000-12000A, and the dielectric layer can be formed by USG/BSG/BPSG or USG+BSG or USG+BPSG.
And etching the contact hole to form a source electrode contact hole.
Metal Ni deposition, ni silicide annealing and Ni removal, gate contact hole etching, metal W deposition and metal AL deposition and etching, passivation layer deposition and etching, back thinning, back injection, back laser annealing and back metal deposition.
Wherein:
the metallic Ni is deposited to a thickness of 1000 a.
Metallic Ni rapid thermal annealing: RTP at 800-1000 ℃ in nitrogen atmosphere, and thermal annealing time of 30-60S.
And (5) cleaning the metal Ni.
And etching the grid contact hole.
Metal W deposition and metal AL deposition: ti/TiN+W+AlSiCu sputtering process.
Metal lithography and etching.
And (3) passivation layer deposition: siO2/SiN/SION+Polyimide single layer or multi-layer bonding.
The back surface is thinned to a thickness of 200 μm, or 150 μm, or 100 μm for different withstand voltage specifications.
Back surface N injection and laser annealing;
backside metal deposition: ti/Ni/Ag.
And (5) completing the chip CP test.
The cell size of the trench super junction MOSFET is 1.0-3.0 mu m, the depth of the trench is 2-6 mu m deep, the trench is etched and then subjected to multi-time high-energy injection AL under the shielding of a hard mask to form a P-type P column structure, the concentration and the width of the P column are required to be matched with the doping concentration of the second epitaxial layer where the P column is positioned, the charge balance is achieved, the depth of the P column is generally 2-6 mu m, the P column and N-type charge in the region are balanced in the reverse voltage-resistant process of the device, the high-concentration N-type region is exhausted, and the electric field of a grid oxide layer in the GATE TRENCH region is reduced. The novel primitive cell structure has different groove depths, different P column depths, different doping concentration thicknesses of the epitaxial layers and multi-layer/single-layer epitaxial layer structures/doping concentrations, and the doping concentrations are all within the structural range of the invention.
In some embodiments, the total depth of the trench plus P-pillar is 4-12 μm, the depth of the 600V SiC MOSFET device is theoretically 5 μm deep, and the depth of the 1200V SiC MOSFET device is theoretically 10 μm deep. For SiC MOSFETs with a withstand voltage exceeding 1700V, the first epitaxial layer 8 shown in the figure can be added, and the first epitaxial layer 8 with different resistivity and thickness is matched with the primitive cell structure and the process of the present invention, so that SiC MOSFETs with higher withstand voltage, for example, ultra-high withstand voltage SiC MOSFETs of 6500V, 10000V, etc., can be theoretically produced. The same set of process flows can be used to produce SiC MOSFETs of different withstand voltages, except that the first layer is epitaxial with different thickness and resistivity, which is one of the main advantages of the cell structure of the present invention.
The SiC MOSFET combines the advantages of the groove and the super junction SiC MOSFET primary cell structure, and greatly reduces the specific on-Resistance (RSPA) of the unit area of the SiC MOSFET.
The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (45)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411009094.9A CN118969840A (en) | 2024-07-26 | 2024-07-26 | The original cell structure and process method of trench superjunction MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411009094.9A CN118969840A (en) | 2024-07-26 | 2024-07-26 | The original cell structure and process method of trench superjunction MOSFET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118969840A true CN118969840A (en) | 2024-11-15 |
Family
ID=93400500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411009094.9A Pending CN118969840A (en) | 2024-07-26 | 2024-07-26 | The original cell structure and process method of trench superjunction MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118969840A (en) |
-
2024
- 2024-07-26 CN CN202411009094.9A patent/CN118969840A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11094810B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| US10763351B2 (en) | Vertical trench DMOSFET having integrated implants forming enhancement diodes in parallel with the body diode | |
| JP5449094B2 (en) | Semiconductor device | |
| JP5557581B2 (en) | Semiconductor device and power conversion device | |
| JP6524666B2 (en) | Semiconductor device | |
| TWI453919B (en) | Diode structure with controlled injection efficiency for fast switching | |
| JP5693851B2 (en) | Semiconductor device | |
| TWI467662B (en) | Split gate structure in trench-based tantalum carbide power devices | |
| JP6950290B2 (en) | Semiconductor devices and manufacturing methods for semiconductor devices | |
| JP7243094B2 (en) | semiconductor equipment | |
| WO2011136272A1 (en) | Semiconductor device | |
| US9276075B2 (en) | Semiconductor device having vertical MOSFET structure that utilizes a trench-type gate electrode and method of producing the same | |
| JP2018182234A (en) | Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device | |
| CN113451392A (en) | Semiconductor device with a plurality of semiconductor chips | |
| JP2002009082A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| CN116314279B (en) | A power electronic chip terminal protection structure | |
| JP7613042B2 (en) | Silicon carbide semiconductor device | |
| CN112838126B (en) | Asymmetric silicon carbide UMOSFET device with shielding area and preparation method | |
| JP2023043336A (en) | Semiconductor device, method for manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator | |
| JP2014207460A (en) | Semiconductor device and electric power conversion device | |
| TWM583123U (en) | Trench-gated wide-bandgap devices | |
| CN118969840A (en) | The original cell structure and process method of trench superjunction MOSFET | |
| CN118693160B (en) | Silicon carbide MOSFET device with gate oxide protection structure and preparation method | |
| JP7371426B2 (en) | semiconductor equipment | |
| CN113809179A (en) | A SIC DMOS device structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |