CN118944670A - Display device, chip, analog-to-digital converter and control method thereof - Google Patents

Abstract

The invention discloses a display device, a chip, an analog-to-digital converter and a control method thereof, wherein the operation of the analog-to-digital converter comprises a sampling stage and a subsequent conversion stage, the analog-to-digital converter comprises a sampling and holding circuit, and the input analog signal is sampled and held to obtain a voltage sampling signal; a digital-to-analog converter generating a first analog voltage and a second analog voltage; the comparison circuit is used for respectively comparing the first analog voltage and the second analog voltage with the voltage sampling signal to obtain comparison signals; the logic control circuit is used for performing successive approximation control on the digital-to-analog converter according to the comparison signals in the conversion stage, so that the comparison circuit outputs the comparison signals successively, and outputs digital signals corresponding to the input analog signals according to the comparison signals.

Description

Display device, chip, analog-to-digital converter and control method thereof

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a display device, a chip, an analog-to-digital converter, and a control method thereof.

Background

The analog-to-digital converter (Analog to Digital Converter, ADC) is a device capable of converting continuous analog signals into discrete digital signals that can be processed by a computer, and is a key component of an interface between an analog system and a digital system, and has been widely used in fields of radar, communication, measurement and control, medical treatment, instruments, images, audio and the like for a long time. The rapid development of digital signal processing technology and communication industry has pushed ADC to develop in the direction of high speed, high precision and low power consumption.

Successive approximation type analog-to-digital converter (Successive Approximation Register Analog to)

Digital Converter, SAR ADC), using a binary search method, continuously generating new analog voltage to approximate to the original input analog signal by using an internally integrated digital-to-analog converter (Digital to Analog Converter, DAC), and finally using the digital input corresponding to the DAC as the output of the ADC. The SAR ADC has the advantages of medium speed, medium precision, low power consumption, low cost and the like compared with other types of ADC, so the SAR ADC has wide application fields.

The SAR ADC mainly comprises a DAC, a comparator and an SAR logic control circuit. SAR ADCs are classified into single-ended inputs and differential inputs according to the type of their input signals. The structure of the DAC inside the SAR ADC can be classified into a resistance voltage division type, a current superposition type, a charge redistribution type, etc., among which the most commonly used structure is a charge redistribution type, which can be classified into a serial DAC and a parallel DAC according to a conversion process. Parallel DACs are typically constructed from binary weight distributed capacitive, resistive or MOS current sources, which can convert all bits simultaneously. The serial DAC can only convert 1-bit analog output at a time, and thus requires a conversion time NT, where N is the number of bits and T is the time taken to convert 1-bit output. The offset error of the SAR ADC with single-ended input and serial DAC is mainly derived from the offset voltage of the comparator, and the input common mode of the comparator changes with the change of the input signal, which causes the offset of the comparator to be related to the input signal, so that the offset of the comparator has nonlinear offset.

Therefore, a new analog-to-digital converter has to be proposed to improve its non-linearity offset.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a display device, a chip, an analog-to-digital converter, and a control method thereof, whereby nonlinear offset of the analog-to-digital converter can be improved.

According to an aspect of the present invention, there is provided an analog-to-digital converter, the operation of which comprises a sampling stage followed by a conversion stage, wherein the analog-to-digital converter comprises a sample-and-hold circuit for sampling and holding an input analog signal to obtain a voltage sampled signal; a digital-to-analog converter for generating a first analog voltage and a second analog voltage; a comparison circuit for comparing the first analog voltage and the second analog voltage with the voltage sampling signal, respectively, to obtain a comparison signal; and the logic control circuit is used for performing successive approximation control on the digital-to-analog converter according to the comparison signals in the conversion stage so that the comparison circuit outputs the comparison signals successively and outputs digital signals corresponding to the input analog signals according to a plurality of comparison signals, and the logic control circuit is also used for controlling the first analog voltage and the second analog voltage to be equal to the input analog signals in the sampling stage and calibrating offset voltages of the comparison circuit.

Optionally, the digital-to-analog converter is a serial digital-to-analog converter.

Optionally, the digital-to-analog converter includes a first reference voltage switch connected between a first reference voltage and the first analog voltage; the second reference voltage switch is connected between a second reference voltage and the second analog voltage; the first sampling switch is connected between the input analog signal and the first analog voltage; the second sampling switch is connected between the input analog signal and the second analog voltage; a charge redistribution switch connected between the first analog voltage and the second analog voltage; the first storage capacitor is connected between the first analog voltage and the ground terminal; and the second storage capacitor is connected between the second analog voltage and the ground terminal.

Optionally, during the sampling phase, the first sampling switch and the second sampling switch are turned on, and the first reference voltage switch, the second reference voltage switch, and the charge redistribution switch are turned off; in the conversion stage, the first sampling switch and the second sampling switch are turned off, and one or two of the first reference voltage switch, the second reference voltage switch and the charge redistribution switch are selectively turned on.

Optionally, the comparing circuit includes a first operational amplifier, a positive input terminal receives the first analog voltage, and a negative input terminal receives the voltage sampling signal; the positive input end of the second operational amplifier receives the second analog voltage, the negative input end of the second operational amplifier receives the voltage sampling signal, the positive output end of the second operational amplifier is connected with the positive output end of the first operational amplifier, and the negative output end of the second operational amplifier is connected with the negative output end of the first operational amplifier; the first end of the first offset storage capacitor is connected with the positive output end of the first operational amplifier; the first end of the second offset storage capacitor is connected with the negative output end of the first operational amplifier; the positive input end of the third operational amplifier is connected with the second end of the first offset storage capacitor, and the negative input end of the third operational amplifier is connected with the second end of the second offset storage capacitor; the first offset cancellation switch is connected between the positive input end and the negative output end of the third operational amplifier; the second offset cancellation switch is connected between the negative input end and the positive output end of the third operational amplifier; the positive input end of the latch is connected with the negative output end of the third operational amplifier, the negative input end of the latch is connected with the positive output end of the third operational amplifier, the output end of the latch provides a first comparison signal and a second comparison signal, and the comparison signals are differential signals of the first comparison signal and the second comparison signal.

Optionally, the latch selectively operates in a reset state or a latch state according to a state control signal provided by the logic control circuit.

Optionally, the first operational amplifier selectively shorts two output ends of the latch according to the state of the latch; the second operational amplifier selectively short-circuits two output ends of the second operational amplifier according to the state of the latch; the third operational amplifier selectively shorts two output ends of the latch according to the state of the latch, wherein when the latch is in a latch state, the two output ends of the first to third operational amplifiers are shorted, and when the latch is in a reset state, the connection between the two output ends of the first to third operational amplifiers is disconnected.

Optionally, the comparison circuit further includes an exclusive or gate, the two input terminals respectively receive a first comparison signal and a second comparison signal, and the output terminal provides a feedback signal to the first to the third operational amplifiers, the feedback signal representing the state of the latch.

Optionally, the first operational amplifier and the second operational amplifier have the same structure and each include a first operational amplifier unit and a second operational amplifier unit, the third operational amplifier has the same structure as the first operational amplifier unit, the first operational amplifier unit includes a first transistor connected between a first output end and a second output end, and a control end of the first operational amplifier unit is connected to receive the feedback signal; the second transistor, the third transistor and the fourth transistor are sequentially connected between a power supply voltage and a ground terminal, the control terminal of the second transistor is connected with the second output terminal, the control terminal of the third transistor is connected with the first input terminal, the control terminal of the fourth transistor is connected with the first bias terminal, and the middle node of the second transistor and the third transistor is the first output terminal; a fifth transistor and a sixth transistor sequentially connected between a power supply voltage and intermediate nodes of the third transistor and the fourth transistor, wherein a control end of the fifth transistor is connected with the first output end, a control end of the sixth transistor is connected with the second input end, and the intermediate nodes of the fifth transistor and the sixth transistor are the second output end; a seventh transistor connected between a power supply voltage and the first output terminal, a control terminal of the seventh transistor being connected to the first output terminal; the eighth transistor is connected between the power supply voltage and the second output end, the control end of the eighth transistor is connected with the second output end, the second operational amplifier unit comprises a ninth transistor, a tenth transistor and an eleventh transistor, the ninth transistor and the eleventh transistor are sequentially connected between the power supply voltage and the ground end, the control end of the ninth transistor is connected with the second bias end, the control end of the tenth transistor is connected with the second input end, and the control end of the eleventh transistor is connected with the intermediate node of the tenth transistor and the eleventh transistor; a twelfth transistor and a thirteenth transistor sequentially connected between the intermediate nodes of the ninth transistor and the tenth transistor and a ground terminal, wherein a control terminal of the twelfth transistor is connected to the first input terminal, and a control terminal of the thirteenth transistor is connected to the intermediate nodes of the twelfth transistor and the thirteenth transistor; a fourteenth transistor connected between the first output terminal and a ground terminal, the control terminal being connected to the control terminal of the eleventh transistor; and a fifteenth transistor connected between the second output terminal and the ground terminal, and a control terminal connected with the control terminal of the thirteenth transistor.

Optionally, the latch includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor, which are sequentially connected between a power supply voltage and a ground terminal, wherein control terminals of the sixteenth transistor and the seventeenth transistor are connected to a second output terminal, a control terminal of the eighteenth transistor is connected to a first input terminal, a control terminal of the nineteenth transistor receives a clock signal, and intermediate nodes of the sixteenth transistor and the seventeenth transistor are first output terminals; a twentieth transistor, a twenty-first transistor and a twenty-first transistor, which are sequentially connected between a power supply voltage and intermediate nodes of the eighteenth transistor and the nineteenth transistor, wherein control ends of the twentieth transistor and the twenty-first transistor are connected with the first output end, a control end of the second transistor is connected with the second input end, and the intermediate nodes of the twentieth transistor and the twenty-first transistor are the second output end; a twenty-third transistor connected between a power supply voltage and the first output terminal, the control terminal receiving the clock signal; a twenty-fourth transistor connected between a power supply voltage and the second output terminal, the control terminal receiving the clock signal; a twenty-fifth transistor connected between a power supply voltage and intermediate nodes of the seventeenth transistor and the eighteenth transistor, a control terminal receiving the clock signal; and a twenty-sixth transistor connected between a power supply voltage and intermediate nodes of the twenty-first transistor and the twenty-second transistor, wherein a control terminal receives the clock signal.

According to a second aspect of the present invention there is provided a control method of an analogue to digital converter as described above, the operation of the analogue to digital converter comprising a sampling stage and a subsequent conversion stage, wherein the control method comprises sampling and holding an input analogue signal using a sample and hold circuit to obtain a voltage sampled signal; generating a first analog voltage and a second analog voltage using a digital-to-analog converter; comparing the voltage sampling signal with the first analog voltage and the second analog voltage using a comparison circuit to generate a comparison signal; and performing successive approximation control on the digital-to-analog converter by using a logic control circuit in the conversion stage according to the comparison signals, so that the comparison circuit outputs comparison signals successively and outputs digital signals corresponding to the input analog signals according to a plurality of comparison signals, wherein the control method further comprises enabling the logic control circuit to control the first analog voltage and the second analog voltage to be equal to the input analog signals in the sampling stage, and calibrating offset voltages of the comparison circuit.

According to a third aspect of the invention there is provided a chip comprising an analogue to digital converter as described above.

According to a fourth aspect of the present invention, there is provided a display device including a display panel for displaying an image; a driving circuit for controlling a display state of the display panel; an analog-to-digital converter as described above for converting a received analog signal into a digital signal; and the processing unit is used for providing the processed digital signals to the driving circuit.

According to the display device, the chip, the analog-to-digital converter and the control method thereof, the SAR ADC adopting the serial DAC can be applied to application occasions of rail-to-rail (full swing) input through the comparison circuit with the four-input structure. By adopting the first to second operational amplifiers connected in parallel as the first stage amplification circuit of the comparison circuit, parasitic capacitance mismatch of two capacitors in the digital-to-analog converter is reduced, thereby improving errors of the analog-to-digital converter when a serial DAC is used. The serial DAC can generate required analog voltage and can participate in the sampling process, so that voltages of four input ends of the comparison circuit are equal in the sampling stage, and therefore conditions are provided for offset elimination of the comparison circuit. After each sampling and offset elimination of the ADC is finished, the offset eliminated is the offset when the input signal of the comparison circuit is an analog input signal, so that the nonlinear offset of the comparison circuit is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of a SAR ADC;

FIG. 2 shows a schematic circuit diagram of a serial DAC;

FIG. 3 shows a schematic diagram of the structure of a SAR DAC using the serial DAC shown in FIG. 2;

FIG. 4 shows the conversion sequence of the serial DAC shown in FIG. 2;

Fig. 5 shows a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present invention;

Fig. 6 shows a schematic diagram of a sample-and-hold circuit according to an embodiment of the invention;

FIG. 7 shows a schematic diagram of a digital-to-analog converter according to an embodiment of the invention;

fig. 8 shows a schematic diagram of a comparison circuit according to an embodiment of the invention;

Fig. 9 shows a circuit schematic of an operational amplifier AMP1/AMP2 according to an embodiment of the invention;

Fig. 10 shows a circuit schematic of an operational amplifier AMP3 according to an embodiment of the invention;

FIG. 11 shows a circuit schematic of a latch according to an embodiment of the invention;

FIG. 12 shows a timing diagram of an analog-to-digital converter according to an embodiment of the invention;

fig. 13 shows a flowchart of a control method of an analog-to-digital converter according to an embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same elements or modules are denoted by the same or similar reference numerals in the various figures. For clarity, the various features of the drawings are not drawn to scale.

It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or circuit is "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

Also, certain terms are used throughout the description and claims to refer to particular components. It will be appreciated by those of ordinary skill in the art that a hardware manufacturer may refer to the same component by different names. The present patent specification and claims do not take the form of an element or components as a functional element or components as a rule.

Furthermore, it should be noted that relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Fig. 1 shows a schematic structure of a SAR ADC. Referring to fig. 1, SAR ADC 100 is a single-ended input SAR ADC, which includes a digital-to-analog converter (DAC) 110, a sample-and-hold circuit 120, a comparator COMP, and a SAR logic control circuit 130. The sample-and-hold circuit 120 samples and holds the input analog signal Vin, and its output terminal is connected to the positive input terminal of the comparator COMP. The negative input terminal of the comparator COMP receives the analog voltage supplied from the digital-to-analog converter 110, compares the input analog signal Vin with the analog voltage, and supplies the comparison result to the SAR logic control circuit 130. The SAR logic control circuit 130 generates a logic control signal, which is an N-bit binary number, according to the comparison result of the comparator COMP. The digital-to-analog converter 110 receives the reference voltage VREF and the logic control signal provided by the SAR logic control circuit 130, and generates an analog voltage according to the reference voltage VREF and the logic control signal to approximate the input analog signal Vin, until the input analog signal Vin is approximately equal to the analog voltage, and takes the logic control signal corresponding to the analog voltage as the output signal of the SAR DAC 100.

The operating principle of the SAR ADC 100 is: the most significant bit MSB of the N-bit binary number initially output by the SAR logic control circuit 130 is 1, the remaining bits are 0, the digital-to-analog converter 110 obtains an analog voltage of 0.5VREF according to the initial digital code, the comparator COMP compares the analog voltage of 0.5VREF with the input analog signal Vin, if the comparator COMP outputs a high level, the most significant bit MSB of the N-bit binary number finally output to the SAR DAC 100 is obtained as 1, otherwise, 0 is obtained, then the next most significant bit MSB-1 of the N-bit binary number next output to the digital-to-analog converter 110 is set as 1, the remaining bits are 0, and the digital code is input to the digital-to-analog converter 110 again with the known MSB bit, then the input analog signal Vin is compared with the analog voltage of the digital-to-analog converter 110 by the comparator COMP, if the comparator COMP outputs a high level, the next most significant bit MSB-1 of the N-bit code finally output to the SAR DAC 100 is obtained as 1, otherwise, 0 is set until all bits of the N-bit binary number finally output to the SAR DAC 100 are determined.

Fig. 2 shows a schematic circuit diagram of a serial DAC. Referring to FIG. 2, the serial DAC includes a reference voltage source that provides a reference voltage VREF, capacitors C1-C2, and switches S1-S4. After switch S1 is turned on, capacitors C1 and C2 are connected in parallel, and the charges on capacitors C1 and C2 are redistributed so that the voltage on capacitor C1 is equal to the voltage on capacitor C2. If the i-th binary digit of the received logic control signal is 1, the switch S2 is turned on to charge the capacitor C1 to the reference voltage VREF, and if the i-th binary digit of the received logic control signal is 0, the switch S3 is turned on to discharge the capacitor C1 to 0. Switch S4 discharges capacitor C2 at the beginning of the digital-to-analog conversion. The conversion of bits generally starts from the least significant bit LSB to the most significant bit MSB. Taking c1=c2, the binary number to be converted is b0=1, b1=1, b2=0, and b3=1 as an example, the conversion process is that the switch S4 is conducted to lead the switch S4 to cause the vc2=0, then the switch S2 is conducted to cause the vc1=vref, the switch S1 is conducted to cause the vc1=vc2=0.5 VREF, then the switch S3 is conducted to cause the vc1=vc2=0.25 VREF, then the switch S2 is conducted to cause the vc1=vref, the switch S1 is conducted to cause the vc1=vc2=5/8 VREF, and finally the switch S2 is conducted to cause the vc1=vref, and the switch S1 is conducted to cause the vc1=vc2=5/16 VREF, and the whole process needs to conduct the switch in order for 9 times to complete the conversion.

Although the serial DAC has a simple structure and small area requirement, the performance of the serial DAC is obviously affected by various error sources, so that the serial DAC is limited to be widely popularized in practical application. Taking the parasitic capacitance with the error source as the capacitance as an example, when key capacitances such as C1 and C2 are required to be matched within the precision of the Least Significant Bit (LSB), the matching difficulty is greatly increased due to the parasitic capacitance, and the overall performance of the DAC is further affected. Taking the error source as the parasitic capacitance of the switch as an example, in the charge redistribution process, the on and off of the switch can introduce extra charge transfer, and the charge injection effect caused by the parasitic capacitance of the switch can directly influence the output voltage of the DAC. In addition, the on-resistance and switching speed of the switch also limit the slew rate and accuracy of the DAC. Taking an error source as a clock feedthrough error as an example, under the driving of a high-speed clock signal, the clock signal may be coupled into the capacitor array through the parasitic capacitance of the switch, so as to cause unnecessary charge disturbance, thereby generating the clock feedthrough error. Such errors can disrupt the linearity of the DAC, reducing its output accuracy.

FIG. 3 shows a schematic diagram of a SAR ADC employing the serial DAC shown in FIG. 2; fig. 4 shows a conversion sequence of the serial DAC shown in fig. 2.

Referring to fig. 3, the data storage register, DAC control register, and timing and control logic circuit of SAR ADC 200 together constitute the SAR logic control circuit of SAR ADC 200.

Referring to fig. 4, the sar ADC 200 first determines the value of the highest bit aN-1 of the binary number it ultimately outputs, and then sequentially determines the value of the middle bit aN-2-a1 until the value of the lowest bit a0 is determined. Taking the value of the i (i > 1) th bit of the binary number finally output by the SAR DAC 200 as an example, the i-1 binary number which has been determined in the data storage register is added with 1 and 1 is taken as the i-th binary number, thereby forming a digital code having i binary numbers in the DAC control register, which is then converted into an analog voltage via a digital-to-analog converter, and the analog voltage is compared with the input analog signal Vin to determine the value of the i-th bit, which is then stored in the data storage register. As can be seen from fig. 4, the N-bit SAR ADC 200 requires at least N (n+1) clock cycles in total to complete one conversion.

Since the input common mode of the comparator COMP varies with the variation of the input signal, a nonlinear error may be caused in the offset of the comparator COMP, and the offset error of the single-ended SAR ADC shown in fig. 1 and 3 mainly comes from the offset voltage of the comparator COMP, so the offset error of the single-ended SAR ADC shown in fig. 1 and 3 also has a nonlinear error. In the prior art, different schemes are adopted to eliminate the offset error of the SAR ADC, one scheme is to adopt a chopping technology, namely, two inputs of a switching comparison circuit are used for quantizing the same input signal twice, and finally, an average value of the two results is output, the scheme needs twice conversion time, the conversion speed of the SAR ADC is further reduced, and another scheme is to adopt a comparison circuit of cascade connection of Output Offset Storage (OOS) and Input Offset Storage (IOS), and the scheme is generally suitable for occasions that the input common mode of the comparator is independent of the size of the sampling signal and does not change in the comparison process, such as some fully differential input SAR ADCs.

If the SAR ADC 200 shown in fig. 3 is applied to a single-ended rail-to-rail (full swing) input, the comparator must be optimized to operate normally under rail-to-rail input, whereas when the existing rail-to-rail input comparator structure is applied to a SAR ADC using a parallel DAC, the input common mode of the comparator is also extended to rail-to-rail range as the input signal range increases, thereby exacerbating the nonlinear error of the offset voltage.

Therefore, a new analog-to-digital converter has to be proposed to solve the above-mentioned problems.

Fig. 5 shows a schematic structural diagram of an analog-to-digital converter according to an embodiment of the invention.

Referring to fig. 5, analog-to-digital converter 300 is a single-ended input SAR ADC. Analog-to-digital converter 300 includes sample-and-hold circuit 310, digital-to-analog converter 320, comparison circuit 330, and logic control circuit 340. Wherein the sample-and-hold circuit 310, the digital-to-analog converter 320, and the comparison circuit 330 are controlled by a logic control circuit 340.

The operation of the analog-to-digital converter 300 includes a sampling stage and a subsequent conversion stage. The sample-and-hold circuit 310 is used for sampling and holding the input analog signal VIN to obtain a voltage sampling signal vin_sah. The voltage value of the voltage sampling signal vin_sah is equal to the voltage value of the input analog signal VIN.

The digital-to-analog converter 320 employs a serial DAC, for example. The digital-to-analog converter 320 is used to generate the analog voltage DA1 VRH and the analog voltage DA2 VRL. In the sampling stage, the digital-to-analog converter 320 samples the input analog signal VIN and outputs an analog voltage DA1 VRH and an analog voltage DA2 VRL equal to the voltage value of the input analog signal VIN; and in the conversion stage, the digital-to-analog converter 320 is controlled by the logic control circuit 340 to perform a successive approximation operation to successively generate the analog voltage DA1_vrh and the analog voltage DA2_vrl, wherein the voltage values of the analog voltage DA1_vrh and the analog voltage DA2_vrl are equal.

The comparison circuit 330 has first to fourth input terminals for receiving the analog voltage DA2_vrl, the analog voltage DA1_vrh, the voltage sampling signal vin_sah, and the voltage sampling signal vin_sah, respectively, and outputting the comparison signal adc_out. The comparison circuit 330 compares the analog voltage DA1_vrh and the analog voltage DA2_vrl sequentially generated by the digital-to-analog converter 320 with the voltage sampling signal vin_sah, respectively, to sequentially output the comparison signal adc_out.

The logic control circuit 340 is configured to perform successive approximation operation on the digital-to-analog converter 320 according to the comparison signal adc_out and output a digital signal DATA [ N-1,0] corresponding to the input analog signal VIN according to the comparison signals adc_out in the conversion stage; and in the sampling stage, the digital-to-analog converter 320 is controlled to generate an analog voltage DA1 VRH and an analog voltage DA2 VRL equal to the voltage value of the input analog signal VIN, and to calibrate the offset voltage of the comparison circuit 330. The phase of the logic control circuit 340 for calibrating the offset voltage of the comparison circuit 330 is one period from the beginning to the end of the sampling phase.

Specifically, the logic control circuit 340 receives the start signal and the clock signal CLK, generates the effective OFFSET cancellation signal OFFSET in one period from the start to the end of the sampling phase according to the start signal and the clock signal CLK, and generates the effective sampling control signal en_sam and the state control signal CMPCTR that controls the comparing circuit 330 to be in the reset state in the sampling phase.

The logic control circuit 340 also receives the comparison signal adc_out during the conversion phase, and sequentially generates an intermediate digital signal corresponding to each bit of the digital signal DATA [ N-1,0], and outputs a logic control signal according to the intermediate digital signal to control the digital-to-analog converter 320 to sequentially generate the corresponding analog voltage DA1_vrh and the analog voltage DA2_vrl, and the output state control signal CMPCTR controls the comparison circuit 330 to sequentially generate the comparison signal adc_out.

Wherein, the generation sequence of the intermediate digital signal corresponding to each bit of the digital signal DATA [ N-1,0] is sequentially from the highest bit to the lowest bit. Specifically, the logic control circuit 340 generates the intermediate digital signal 1 corresponding to the most significant bit MSB of the digital signal DATA [ N-1,0] during the conversion stage, then controls the digital-to-analog converter 320 to generate the corresponding analog voltage DA1_vrh and the analog voltage DA2_vrl, then the comparison circuit 330 compares the analog voltage DA1_vrh and the analog voltage DA2_vrl with the voltage sampling signal vin_sah respectively to obtain the comparison signal adc_out, determines the value corresponding to the most significant bit MSB according to the comparison signal adc_out, for example, the comparison signal adc_out is at the high level, the MSB is 1, otherwise is 0, then the logic control circuit 340 generates the intermediate digital signal corresponding to the next significant bit MSB-1, assuming that the previously determined MSB is 1, the intermediate digital signal corresponding to MSB-1 is 11, assuming that the previously determined MSB is 0, then the intermediate digital signal corresponding to MSB-1 is 01, and then determines the value of the next significant bit MSB-1 through the digital-to-analog converter 320 and the comparison circuit 330, and then generates the intermediate digital signal corresponding to the next significant bit MSB-2 until each bit of the digital signal DATA [ N-1,0] output by the analog-to the analog converter 300 is determined.

Fig. 6 shows a schematic diagram of a sample-and-hold circuit according to an embodiment of the invention.

Referring to fig. 6, the sample-and-hold circuit 310 includes a sampling switch S11 and a storage capacitor C11. The sampling switch S11 is connected between the input analog signal VIN and the voltage sampling signal vin_sah, and the storage capacitor C11 is connected between the voltage sampling signal vin_sah and the ground, wherein the turn-off and turn-on of the sampling switch S11 are controlled by the sampling control signal en_sam. In the sampling phase, the sampling switch S11 is turned on, the sample-hold circuit 310 samples the input analog signal VIN and stores it in the storage capacitor C11, and in the conversion phase, the sampling switch S11 is turned off, and the voltage sampling signal vin_sah maintains the voltage value in the sampling phase through the storage capacitor C11.

Fig. 7 shows a schematic diagram of the structure of a digital-to-analog converter according to an embodiment of the invention.

Referring to fig. 7, the digital-to-analog converter 320 includes a conversion circuit 321. The conversion circuit 321 includes a reference voltage switch SL, a reference voltage switch SH, sampling switches S12-S13, a charge redistribution switch SR, and storage capacitors C12-C13. The reference voltage switch SL is connected between the reference voltage VRL and the analog voltage DA2 VRL, the reference voltage switch SH is connected between the reference voltage VRH and the analog voltage DA1 VRH, the sampling switch S12 is connected between the input analog signal VIN and the analog voltage DA2 VRL, the sampling switch S13 is connected between the input analog signal VIN and the analog voltage DA1 VRH, the charge redistribution switch SR is connected between the analog voltage DA2 VRL and the analog voltage DA1 VRH, the storage capacitor C12 is connected between the analog voltage DA2 VRL and the ground, and the storage capacitor C13 is connected between the analog voltage DA1 VRH and the ground. Wherein the reference voltage VRH is greater than the reference voltage VRL. The turning off and on of the sampling switches S12 and S13 is controlled by a sampling control signal en_sam.

In the sampling phase, the reference voltage switch SL and the reference voltage switch SH are turned off, the charge redistribution switch SR and the sampling switches S12 to S13 are turned on, the storage capacitors C12 to C13 store the sampled input analog signal VIN, and the analog voltages DA1_vrh and DA2_vrl are equal to the input analog signal VIN. In the switching phase, the sampling switches S12-S13 are turned off, and one or both of the reference voltage switch SL, the reference voltage switch SH, and the charge redistribution switch SR are selected to be turned on.

The turning on and off of the reference voltage switch SL, the reference voltage switch SH, and the charge redistribution switch SR are controlled by logic control signals. The logic control signals include control signals RDIST, VRCTR, PRECHG. The digital-to-analog converter 320 further includes a decoding circuit 322 for decoding the control signal RDIST, PRECHG, VRCTR into a switch control signal RST, CHGVH, CHGVL to control the turning on and off of the charge redistribution switch SR, the reference voltage switches SH and SL, respectively.

The control signal RDIST is used to control on and off of the charge redistribution switch SR (for example, when RDIST =1, the charge redistribution switch SR is turned off, and when RDIST =0, the charge redistribution switch SR is turned off). The control signal PRECHG is used to control the reference voltage switches SH and SL to change simultaneously according to the control signal RDIST (for example, if prechg=1, the reference voltage switches SH and SL are turned on simultaneously, and if prechg=0, the reference voltage switches SH and SL are turned off simultaneously, when RDIST =0). The control signal VRCTR is configured to sequentially output the values of the most significant MSB to the least significant LSB-1 of the intermediate digital signal to control one of the reference voltage switches SH and SL to be turned on according to the control signals RDIST and PRECHG (e.g., when VRCTR =1, if RDIST =1, prechg=0, the reference voltage switch SH is turned on, and when VRCTR =0, if RDIST =1, prechg=0, the reference voltage switch SL is turned on).

Fig. 8 shows a schematic diagram of a comparison circuit according to an embodiment of the invention.

Referring to fig. 8, the comparison circuit 330 includes operational amplifiers AMP1-AMP3, offset storage capacitors C14-C15, offset cancellation switches S14-S15, a latch 331, an not gate 332, and an exclusive or gate 333. Wherein the first stage amplification circuit of the comparison circuit 330 is constituted by operational amplifiers AMP1-AMP2, the operational amplifiers AMP1 and AMP2 being connected in parallel. The second stage amplification circuit of the comparison circuit 330 is constituted by an operational amplifier AMP 3. Latch 331 adopts a strong arm structure. By providing the operational amplifiers AMP1 and AMP2 connected in parallel, parasitic capacitances of the storage capacitances C12 and C13 are matched, the error of the digital-to-analog converter 320 is reduced, and thus the error of the analog-to-digital converter 300 is reduced.

The positive and negative input terminals of the operational amplifier AMP1 respectively receive the analog voltage DA1 VRH and the voltage sampling signal vin_sah, the positive and negative input terminals of the operational amplifier AMP2 respectively receive the analog voltage DA2 VRL and the voltage sampling signal vin_sah, the positive output terminals of the operational amplifiers AMP1 and AMP2 are connected and provide the analog signal VIP at their common node, and the negative output terminals of the operational amplifiers AMP1 and AMP2 are connected and provide the analog signal VIN at their common node. The offset storage capacitor C14 is connected between the positive output terminal of the operational amplifier AMP1 and the positive input terminal of the operational amplifier AMP3, and the offset storage capacitor C15 is connected between the negative output terminal of the operational amplifier AMP1 and the negative input terminal of the operational amplifier AMP 3. The OFFSET canceling switch S14 is connected between the positive input terminal and the negative output terminal of the operational amplifier AMP3, and the OFFSET canceling switch S15 is connected between the negative input terminal and the positive output terminal of the operational amplifier AMP3, wherein the on and off of the OFFSET canceling switches S14 and S15 are controlled by an OFFSET canceling signal OFFSET. The positive input of the latch 331 is connected to the negative output of the operational amplifier AMP3, and the negative input of the latch 331 is connected to the positive output of the operational amplifier AMP 3. The latch 331 further receives the state control signal CMPCTR via the not gate 332, and outputs the comparison signal adc_outp and the comparison signal adc_outn, which are differential signals of the comparison signal adc_outp and the comparison signal adc_outn. The two inputs of the exclusive-or gate 333 receive the comparison signal adc_outp and the comparison signal adc_outn, respectively, and the output provides a feedback signal KICKBACK, the feedback signal KICKBACK being indicative of the operational state of the latch 331. Feedback signal KICKBACK controls the selective shorting of the two outputs of operational amplifiers AMP1-AMP 3. Wherein the feedback signal KICKBACK controls the shorting of the two outputs of each of the operational amplifiers AMP1-AMP3 when the latch 331 is in the latched state, and the feedback signal KICKBACK controls the disconnection of the two outputs of each of the operational amplifiers AMP1-AMP3 when the latch 331 is in the reset state.

In the offset voltage calibration stage of the comparison circuit 330, the voltages at the two input ends of the operational amplifier AMP1 are both equal to the input analog signal VIN, and the voltages at the two input ends of the operational amplifier AMP2 are both equal to the input analog signal VIN, so that the offset voltages of the operational amplifiers AMP1 and AMP2 are amplified and stored in the offset storage capacitors C14 and C15, so that the offset voltages generated by the operational amplifiers AMP1 and AMP2 and the voltages stored in the offset storage capacitors C14 and C15 are mutually offset in the conversion stage, and offset cancellation of the operational amplifiers AMP1 and AMP2 is realized; the offset canceling switches S14 and S15 are turned on to connect the operational amplifier AMP3 as a unit gain negative feedback structure, thereby reversely amplifying the offset voltage of the operational amplifier AMP3 to the input terminal thereof to cancel the offset voltage of the operational amplifier AMP 3. The offset voltage of latch 331 is attenuated to 0.5LSB by setting the gain of operational amplifiers AMP1-AMP3, and is thus ignored. At this time, the latch 331 is controlled by the state control signal CMPCTR to be in a reset state, outputs the comparison signal adc_outp and the comparison signal adc_outn of high level, and makes the feedback signal KICKBACK output from the exclusive or gate 333 of high level, so that the connection between the two output terminals of the operational amplifiers AMP1-AMP3 is disconnected. In comparison to a comparison circuit in which an Output Offset Store (OOS) and an Input Offset Store (IOS) are cascaded, the comparison circuit 330 does not need to set an excessive reference voltage and perform a switching operation related to the reference voltage during offset voltage calibration.

In the conversion stage, the comparison circuit 330 compares the analog voltage DA1_vrh and the analog voltage DA2_vrl sequentially generated by the digital-to-analog converter 320 with the voltage sampling signal vin_sah, respectively, to sequentially output the comparison signal adc_outp and the comparison signal adc_outn.

Specifically, after the first two-stage amplifying circuit of the comparing circuit 330 amplifies the difference between the analog voltage DA 1_vrh/the analog voltage DA2_vrl and the input analog signal VIN, the latch 331 is controlled by the state control signal CMPCTR to switch from the reset state to the latch state, so as to output the comparing signal adc_outp and the comparing signal adc_outn according to the difference between the positive and negative input terminals thereof, and generate the low-level feedback signal KICKBACK according to the comparing signal adc_outp and the comparing signal adc_outn, so that the two output terminals of the operational amplifiers AMP1-AMP3 are shorted, thereby reducing the feedback noise output to the input.

Fig. 9 shows a circuit schematic of operational amplifiers AMP1-AMP2 according to an embodiment of the invention.

Referring to fig. 9, the operational amplifier AMP1/AMP2 is a full differential operational amplifier structure shared by the PMOS differential pair and the NMOS differential pair. The operational amplifier AMP1/AMP2 includes a first operational amplifier unit 330_1 and a second operational amplifier unit 330_2.

The first operational amplifier 330_1 includes transistors MN1-MN3 and MP1-MP5. Wherein the transistor MP1 is connected between the output terminals VON1 and VOP1, the control terminal thereof receives the feedback signal KICKBACK, when the feedback signal KICKBACK is at a low level, the transistor MP1 is turned on to short the two output terminals of the operational amplifier AMP1/AMP2, and when the feedback signal KICKBACK is at a high level, the transistor MP1 is turned off to control the connection between the two output terminals of the operational amplifier AMP1/AMP2 to be disconnected; the transistors MP3, MN1 and MN3 are sequentially connected between the power supply voltage AVDD and the grounding terminal AVSS, the transistors MP4 and MN2 are sequentially connected between the power supply voltage AVDD and the intermediate nodes of the transistors MN1 and MN3, the transistor MP2 is connected between the power supply voltage AVDD and the output terminal VON1 which is the intermediate node of the transistors MP3 and MN1, the transistor MP5 is connected between the power supply voltage AVDD and the output terminal VOP1 which is the intermediate node of the transistors MP4 and MN2, the control terminals of the transistors MP2 and MP4 are connected with the output terminal VON1, the control terminals of the transistors MP3 and MP5 are connected with the output terminal VOP1, the control terminals of the transistors MN1 and MN2 are respectively connected with the input terminals VIP1 and VIN1, and the control terminal of the transistor MN3 is connected with the bias terminal VBN.

The second operational amplifier 330_2 includes transistors MN4-MN7 and MP6-MP8. The transistors MP6, MP7 and MN5 are sequentially connected between the power supply voltage AVDD and the ground terminal AVSS, the transistors MP8 and MN6 are sequentially connected between the intermediate nodes of the transistors MP6 and MP7 and the ground terminal AVSS, the transistor MN4 is connected between the output terminal VON1 and the ground terminal AVSS, the transistor MN7 is connected between the output terminal VOP1 and the ground terminal AVSS, the control terminals of the transistors MN4 and MN5 are connected with the intermediate nodes of the transistors MP7 and MN5, the control terminals of the transistors MN6 and MN7 are connected with the intermediate nodes of the transistors MP8 and MN6, the control terminals of the transistors MP7 and MP8 are respectively connected with the input terminals VIN1 and VIP1, and the control terminal of the transistor MP6 is connected with the bias terminal VBP. After the transistor MN3 and the transistor MP6 are turned on, the operational amplifier AMP1/AMP2 is started.

Fig. 10 shows a circuit schematic of an operational amplifier AMP3 according to an embodiment of the invention.

Referring to fig. 10, the operational amplifier AMP3 is a full differential operational amplifier structure employing an NMOS differential pair. The structure of the operational amplifier AMP3 shown in fig. 10 is the same as the structure of the first operational amplifier unit 330_1 of the operational amplifier AMP1/AMP2 shown in fig. 9, and will not be described again.

Fig. 11 shows a circuit schematic of a latch according to an embodiment of the invention.

Referring to fig. 11, the latch 311 includes transistors MP14, MN11, and MN13 sequentially connected between a power supply voltage AVDD and a ground terminal AVSS, transistors MP15, MN15, and MN12 sequentially connected between power supply voltage AVDD and intermediate nodes of transistors MN11 and MN13, transistor MP13 connected between power supply voltage AVDD and output terminal VON2, transistor MP11 connected between power supply voltage AVDD and intermediate nodes of MN14 and MN11, transistor MP16 connected between power supply voltage AVDD and output terminal VOP2, transistor MP12 connected between power supply voltage AVDD and intermediate nodes of transistors MN15 and MN12, wherein control terminals of transistors MP14 and MN14 are connected to output terminal VOP2, control terminals of transistors MP15 and MN15 are connected to output terminal VON2, control terminals of transistors MP11-MP13, MP16, and MN13 receive the clock signal CLK1, and control terminals of transistors MN11 and MN12 are connected to input terminals vipvin 2 and vipvin, respectively.

The latch 311 is controlled by the state control signal CMPCTR to switch between the reset state and the latch state, specifically, when the state control signal CMPCTR is at a high level, the latch 311 enters the reset state so that VON2 and VOP2 become at a high level, and when the state control signal CMPCTR is at a low level, the latch 311 enters the latch state so that VON2 and VOP2 become at a high level. The clock signal CLK1 is an inverse of the state control signal CMPCTR.

Fig. 12 shows a timing diagram of an analog-to-digital converter according to an embodiment of the invention.

Referring to fig. 12, the offset voltage calibration phase of the comparison circuit 330 is performed within one period from the start to the end of the sampling phase. In the sampling stage, the sampling control signal en_sam is at a high level, the sample-hold circuit 310 samples the input analog signal VIN and holds it, and the digital-to-analog converter 320 samples the input analog signal VIN and outputs the analog voltages DA1_vrh and DA2_vrl equal to the voltage value of the input analog signal VIN. In the OFFSET voltage calibration stage, the voltages at the four input terminals of the comparison circuit 330 are equal to the input analog signal VIN, the OFFSET cancellation signal OFFSET is in an active state (high level), and the state control signal CMPCTR is also in a high level to control the comparison circuit 330 to enter a reset state, so that the comparison circuit 330 can perform OFFSET cancellation.

After switching from the sampling phase to the transition phase, both the OFFSET cancellation signal OFFSET and the sampling control signal en_sam are in an inactive state (low level), and the state control signal CMPCTR remains high. After the conversion stage starts, the conversion of the most significant MSB is performed first, specifically, the logic control circuit 340 generates the intermediate digital signal 1 corresponding to the most significant MSB of the digital signal DATA [ N-1,0], and in the first clock cycle, it outputs the high-level control signals RDIST and PRECHG and the low-level control signal VRCTR, so that the charge redistribution switch SR is turned off, the reference voltage switches SH and SL are turned on, and the storage capacitors C12 and C13 are charged to the reference voltages VRL and VRH, respectively; in the second clock period, the logic control circuit 340 outputs the control signals RDIST, PRECHG and VRCTR of low level, so that the charge redistribution switch SR is turned on, the reference voltage switches SH and SL are turned off, the analog voltage DA1_vrh and the analog voltage DA2_vrl equal to (vrh+vrl)/2 are obtained, and the difference between the analog voltage DA 1_vrh/the analog voltage DA2_vrl and the voltage sampling signal vin_sah is amplified by the first two-stage amplifying circuit of the comparing circuit 330; in the third clock cycle, the state control signal CMPCTR is switched from high level to low level in the first two clock cycles, so that the latch 331 enters a latch state, i.e. obtains the comparison signal adc_out according to the difference value of the input signals, and the exclusive-or gate 333 outputs the feedback signal KICKBACK with low level according to the comparison signal adc_out, so that the respective two output ends of the operational amplifiers AMP1-AMP3 are short-circuited, and thus the feedback noise output to the input is reduced.

Then, the next-highest bit MSB-1 is converted, specifically, the logic control circuit 340 obtains the value of the MSB after receiving the comparison signal adc_out, and generates an intermediate digital signal i1 corresponding to the next-highest bit MSB-1, taking MSB as 1 as an example, and the intermediate digital signal corresponding to the next-highest bit MSB-1 is 11; in the fourth clock period, it outputs high-level control signals RDIST and PRECHG and low-level control signal VRCTR, so that charge redistribution switch SR is turned off, reference voltage switches SH and SL are turned on simultaneously, and storage capacitors C12 and C13 are charged to reference voltages VRL and VRH, respectively; in the fifth clock period, the logic control circuit 340 outputs the control signals RDIST, PRECHG and VRCTR of low level to turn on the charge redistribution switch SR, and the reference voltage switches SH and SL are turned off simultaneously to obtain the analog voltage DA1_vrh and the analog voltage DA2_vrl equal to (vrh+vrl)/2; in the sixth clock cycle, the logic control circuit 340 outputs the control signals RDIST and VRCTR of high level (here VRCTR is low if the previous MSB is 0) and the control signal PRECHG of low level, which turns off the charge redistribution switch SR, turns on the reference voltage switch SH, and turns off the reference voltage switch SL (here the reference voltage switch SH turns off if the previous MSB is 0, and the reference voltage switch SL turns on); In the seventh clock period, the logic control circuit 340 outputs the control signal RDIST, VRCTR, PRECHG of the low level to turn on the charge redistribution switch SR, and the reference voltage switches SH and SL are simultaneously turned off to obtain the analog voltages DA1_vrh and DA2_vrl equal to (2 x vrh+vrl)/4 (if the previous MSB is 0, the analog voltages DA1_vrh and DA2_vrl obtained here are equal to (vrh+2 x VRL)/4), and at the same time, the state control signal CMPCTR is switched from the low level to the high level to make the latch 331 enter the reset state, i.e., output the comparison signals adc_outp and adc_outn of the high level, The exclusive or gate 333 outputs a high-level feedback signal KICKBACK to turn off the connection between the two output terminals of the operational amplifiers AMP1-AMP3, and the first two-stage amplifying circuit of the comparing circuit 330 amplifies the difference between the analog voltage DA1_vrh and the analog voltage DA2_vrl and the voltage sampling signal vin_sah. In the eighth clock period, the state control signal CMPCTR is switched from high level to low level, so that the latch 331 enters a latch state, i.e. obtains the comparison signal adc_out according to the difference value of the input signals, and the exclusive-or gate 333 outputs the feedback signal KICKBACK with low level according to the comparison signal adc_out, so that the respective two output terminals of the operational amplifiers AMP1-AMP3 are shorted, and thus the feedback noise output to the input is reduced. The conversion of MSB-2-LSB is completed successively until digital signal DATA [ N-1,0] corresponding to input analog signal VIN is obtained.

From the timing diagram, it can be seen that, from the transition of the next highest MSB-1, the latch 311 is in the reset state only during the period in which the digital-to-analog converter 320 performs the last charge redistribution, and is in the latch state for the rest of the time.

Furthermore, the present invention provides a control method of the analog-to-digital converter 300, wherein the operation of the analog-to-digital converter 300 includes a sampling phase and a subsequent conversion phase, and the control method includes the following steps, referring to fig. 13:

Step S1: sampling and holding an input analog signal by using a sampling and holding circuit to obtain a voltage sampling signal;

Step S2: generating a first analog voltage and a second analog voltage using a digital-to-analog converter;

Step S3: comparing the voltage sampling signal with the first analog voltage and the second analog voltage using a comparison circuit to generate a comparison signal; and

Step S4: using a logic control circuit to perform successive approximation control on the digital-to-analog converter according to the comparison signals in the conversion stage so that the comparison circuit outputs the comparison signals successively and outputs digital signals corresponding to the input analog signals according to a plurality of comparison signals,

Wherein the control method further comprises:

Step S5: and in the sampling stage, the logic control circuit controls the first analog voltage and the second analog voltage to be equal to the input analog signal, and the offset voltage of the comparison circuit is calibrated.

The analog-to-digital converter provided by the invention enables the SAR ADC adopting the serial DAC to be applied to the application occasion of rail-to-rail (full swing) input through the comparison circuit with a four-input structure. By adopting the first to second operational amplifiers connected in parallel as the first stage amplification circuit of the comparison circuit, parasitic capacitance mismatch of two capacitors in the digital-to-analog converter is reduced, thereby improving errors of the analog-to-digital converter when a serial DAC is used. The serial DAC can generate required analog voltage and can participate in the sampling process, so that voltages of four input ends of the comparison circuit are equal in the sampling stage, and therefore conditions are provided for offset elimination of the comparison circuit. After each sampling and offset elimination of the ADC is finished, the offset eliminated is the offset when the input signal of the comparison circuit is an analog input signal, so that the nonlinear offset of the comparison circuit is improved.

Furthermore, the invention also provides a chip comprising the analog-to-digital converter.

Further, the present invention also provides a display device, which includes: a display panel for displaying an image; a driving circuit for controlling a display state of the display panel; and

An analog-to-digital converter for converting the received analog signal into a digital signal; and the processing unit is used for providing the digital signal provided by the analog-to-digital converter to the driving circuit.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the appended claims and their equivalents.

Claims (13)

1. An analog-to-digital converter, the operation of which comprises a sampling phase followed by a conversion phase, wherein the analog-to-digital converter comprises:

the sampling and holding circuit is used for sampling and holding an input analog signal to obtain a voltage sampling signal;

A digital-to-analog converter for generating a first analog voltage and a second analog voltage;

A comparison circuit for comparing the first analog voltage and the second analog voltage with the voltage sampling signal, respectively, to obtain a comparison signal; and

A logic control circuit for performing successive approximation control on the digital-to-analog converter according to the comparison signals in the conversion stage so that the comparison circuit outputs the comparison signals successively and outputs digital signals corresponding to the input analog signals according to a plurality of comparison signals,

The logic control circuit is further configured to control the first analog voltage and the second analog voltage to be equal to the input analog signal in the sampling stage, and calibrate the offset voltage of the comparison circuit.

2. The analog-to-digital converter of claim 1, wherein the digital-to-analog converter is a serial digital-to-analog converter.

3. The analog-to-digital converter of claim 2, wherein the digital-to-analog converter comprises:

The first reference voltage switch is connected between a first reference voltage and the first analog voltage;

the second reference voltage switch is connected between a second reference voltage and the second analog voltage;

the first sampling switch is connected between the input analog signal and the first analog voltage;

The second sampling switch is connected between the input analog signal and the second analog voltage;

A charge redistribution switch connected between the first analog voltage and the second analog voltage;

The first storage capacitor is connected between the first analog voltage and the ground terminal;

And the second storage capacitor is connected between the second analog voltage and the ground terminal.

4. The analog-to-digital converter of claim 3, wherein during the sampling phase, the first sampling switch and the second sampling switch are on, the first reference voltage switch, the second reference voltage switch, and the charge redistribution switch are off; in the conversion stage, the first sampling switch and the second sampling switch are turned off, and one or two of the first reference voltage switch, the second reference voltage switch and the charge redistribution switch are selectively turned on.

5. The analog-to-digital converter of claim 1, wherein the comparison circuit comprises:

a first operational amplifier, the positive input end of which receives the first analog voltage and the negative input end of which receives the voltage sampling signal;

The positive input end of the second operational amplifier receives the second analog voltage, the negative input end of the second operational amplifier receives the voltage sampling signal, the positive output end of the second operational amplifier is connected with the positive output end of the first operational amplifier, and the negative output end of the second operational amplifier is connected with the negative output end of the first operational amplifier;

the first end of the first offset storage capacitor is connected with the positive output end of the first operational amplifier;

The first end of the second offset storage capacitor is connected with the negative output end of the first operational amplifier;

The positive input end of the third operational amplifier is connected with the second end of the first offset storage capacitor, and the negative input end of the third operational amplifier is connected with the second end of the second offset storage capacitor;

The first offset cancellation switch is connected between the positive input end and the negative output end of the third operational amplifier;

The second offset cancellation switch is connected between the negative input end and the positive output end of the third operational amplifier;

The positive input end of the latch is connected with the negative output end of the third operational amplifier, the negative input end of the latch is connected with the positive output end of the third operational amplifier, the output end of the latch provides a first comparison signal and a second comparison signal, and the comparison signals are differential signals of the first comparison signal and the second comparison signal.

6. The analog-to-digital converter of claim 5, wherein the latch selectively operates in a reset state or a latched state in accordance with a state control signal provided by the logic control circuit.

7. The analog-to-digital converter of claim 6, wherein,

The first operational amplifier selectively short-circuits two output ends of the first operational amplifier according to the state of the latch;

The second operational amplifier selectively short-circuits two output ends of the second operational amplifier according to the state of the latch;

the third operational amplifier selectively shorts two output terminals of the latch according to the state of the latch,

Wherein, when the latch is in a latch state, the two output ends of the first to third operational amplifiers are in short circuit, and when the latch is in a reset state, the connection between the two output ends of the first to third operational amplifiers is disconnected.

8. The analog-to-digital converter of claim 7, wherein the comparison circuit further comprises:

And the two input ends of the exclusive-OR gate respectively receive a first comparison signal and a second comparison signal, and the output end provides feedback signals for the first operational amplifier to the third operational amplifier, wherein the feedback signals represent the state of the latch.

9. The analog-to-digital converter of claim 8, wherein the first and second operational amplifiers are identical in structure and each comprise a first operational amplifier unit and a second operational amplifier unit, the third operational amplifier is identical in structure to the first operational amplifier unit, and the first operational amplifier unit comprises:

The first transistor is connected between the first output end and the second output end, and the control end of the first transistor is connected with the feedback signal;

The second transistor, the third transistor and the fourth transistor are sequentially connected between a power supply voltage and a ground terminal, the control terminal of the second transistor is connected with the second output terminal, the control terminal of the third transistor is connected with the first input terminal, the control terminal of the fourth transistor is connected with the first bias terminal, and the middle node of the second transistor and the third transistor is the first output terminal;

A fifth transistor and a sixth transistor sequentially connected between a power supply voltage and intermediate nodes of the third transistor and the fourth transistor, wherein a control end of the fifth transistor is connected with the first output end, a control end of the sixth transistor is connected with the second input end, and the intermediate nodes of the fifth transistor and the sixth transistor are the second output end;

a seventh transistor connected between the power supply voltage and the first output terminal, the control terminal being connected to the first output terminal;

An eighth transistor connected between the power voltage and the second output terminal, a control terminal connected to the second output terminal,

The second operational amplifier unit includes:

A ninth transistor, a tenth transistor and an eleventh transistor, which are sequentially connected between a power supply voltage and a ground terminal, wherein a control terminal of the ninth transistor is connected to a second bias terminal, a control terminal of the tenth transistor is connected to the second input terminal, and a control terminal of the eleventh transistor is connected to intermediate nodes of the tenth transistor and the eleventh transistor;

A twelfth transistor and a thirteenth transistor sequentially connected between the intermediate nodes of the ninth transistor and the tenth transistor and a ground terminal, wherein a control terminal of the twelfth transistor is connected to the first input terminal, and a control terminal of the thirteenth transistor is connected to the intermediate nodes of the twelfth transistor and the thirteenth transistor;

a fourteenth transistor connected between the first output terminal and a ground terminal, the control terminal being connected to the control terminal of the eleventh transistor;

And a fifteenth transistor connected between the second output terminal and the ground terminal, and a control terminal connected with the control terminal of the thirteenth transistor.

10. The analog-to-digital converter of claim 6, wherein the latch comprises:

a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor which are sequentially connected between a power supply voltage and a ground terminal, wherein the control terminals of the sixteenth transistor and the seventeenth transistor are connected with a second output terminal, the control terminal of the eighteenth transistor is connected with a first input terminal, the control terminal of the nineteenth transistor receives a clock signal, and the intermediate nodes of the sixteenth transistor and the seventeenth transistor are the first output terminal;

A twentieth transistor, a twenty-first transistor and a twenty-first transistor, which are sequentially connected between a power supply voltage and intermediate nodes of the eighteenth transistor and the nineteenth transistor, wherein control ends of the twentieth transistor and the twenty-first transistor are connected with the first output end, a control end of the second transistor is connected with the second input end, and the intermediate nodes of the twentieth transistor and the twenty-first transistor are the second output end;

a twenty-third transistor connected between a power supply voltage and the first output terminal, the control terminal receiving the clock signal;

a twenty-fourth transistor connected between a power supply voltage and the second output terminal, the control terminal receiving the clock signal;

A twenty-fifth transistor connected between a power supply voltage and intermediate nodes of the seventeenth transistor and the eighteenth transistor, a control terminal receiving the clock signal;

And a twenty-sixth transistor connected between a power supply voltage and intermediate nodes of the twenty-first transistor and the twenty-second transistor, wherein a control terminal receives the clock signal.

11. A method of controlling an analog to digital converter as claimed in any of claims 1 to 10, the operation of the analog to digital converter comprising a sampling phase followed by a conversion phase, wherein the method of controlling comprises:

sampling and holding an input analog signal by using a sampling and holding circuit to obtain a voltage sampling signal;

generating a first analog voltage and a second analog voltage using a digital-to-analog converter;

comparing the voltage sampling signal with the first analog voltage and the second analog voltage using a comparison circuit to generate a comparison signal; and

Using a logic control circuit to perform successive approximation control on the digital-to-analog converter according to the comparison signals in the conversion stage so that the comparison circuit outputs the comparison signals successively and outputs digital signals corresponding to the input analog signals according to a plurality of comparison signals,

Wherein the control method further comprises:

and in the sampling stage, the logic control circuit controls the first analog voltage and the second analog voltage to be equal to the input analog signal, and the offset voltage of the comparison circuit is calibrated.

12. A chip comprising an analog-to-digital converter as claimed in any one of claims 1-10.

13. A display device, comprising:

A display panel for displaying an image;

a driving circuit for controlling a display state of the display panel;

an analog-to-digital converter as claimed in any one of claims 1 to 10, for converting a received analog signal to a digital signal;

and the processing unit is used for providing the processed digital signals to the driving circuit.