CN118860917B - Single-wire communication system - Google Patents
Single-wire communication system Download PDFInfo
- Publication number
- CN118860917B CN118860917B CN202411366728.6A CN202411366728A CN118860917B CN 118860917 B CN118860917 B CN 118860917B CN 202411366728 A CN202411366728 A CN 202411366728A CN 118860917 B CN118860917 B CN 118860917B
- Authority
- CN
- China
- Prior art keywords
- signal
- slave
- bus
- state
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000006854 communication Effects 0.000 title claims abstract description 57
- 238000004891 communication Methods 0.000 title claims abstract description 57
- 230000005540 biological transmission Effects 0.000 claims abstract description 64
- 230000004913 activation Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 27
- 238000012546 transfer Methods 0.000 description 22
- 238000000034 method Methods 0.000 description 8
- 238000005070 sampling Methods 0.000 description 7
- 230000008054 signal transmission Effects 0.000 description 7
- 238000012360 testing method Methods 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 230000007175 bidirectional communication Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 238000013024 troubleshooting Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Small-Scale Networks (AREA)
Abstract
The application provides a single-wire communication system, and relates to the technical field of communication. The system comprises a host, a slave and a first resistor, wherein the host and the slave are connected through a bus, one end of the first resistor is connected with the bus, the other end of the first resistor is connected with a power supply, when the bus is pulled down by the host for a period longer than a preset first period, the slave enters a reset state, when the slave is in the reset state and the bus is pulled down by the host for a period longer than a preset second period, the signal receiving end enters an activated state, the second period is shorter than the first period, when the signal receiving end is in the activated state and the bus is pulled down by the signal transmitting end for a period longer than a preset third period, the signal receiving end enters a transmission state, the third period is related to the second period, and when the signal receiving end is in the transmission state, the signal transmitting end transmits a data signal or a command signal to the signal receiving end. The application has the advantage of improving the system stability.
Description
Technical Field
The application relates to the technical field of chip testing and debugging, in particular to a single-wire communication system.
Background
At present, after the chip is produced, the voltage of the linear voltage stabilizer, the frequency of the clock oscillator and other modules inside the chip have larger deviation before calibration, and the deviation can influence the normal communication of the external communication interface.
At this time, if two-wire communication is used, in which one signal wire is used as a clock wire and the other signal wire is used as a data wire, the communication scheme will not generally fail. However, the communication method occupies two IO ports, and under the condition that the pin resources of some chips are extremely tense, the situation that the pins are insufficient exists. Therefore, in actual communication, a single-wire communication method is adopted.
However, the single-wire communication method has the problem of frequency sensitivity, and the voltage, temperature and process deviation in the chip can have influence on the frequency of the clock, and the influence has a larger influence on the stability of communication before the chip is not calibrated.
Therefore, the prior art has a problem that the communication stability of the single-wire communication system is poor.
Disclosure of Invention
The application aims to provide a single-wire communication system so as to solve the problem of poor communication stability of the single-wire communication system in the prior art.
In order to achieve the above object, the technical scheme adopted by the embodiment of the application is as follows:
The embodiment of the application provides a single-wire communication system, which comprises a host computer, a slave computer and a resistor, wherein the host computer is connected with the slave computer through a bus, one end of the resistor is connected with the bus, the other end of the resistor is connected with a power supply, one of the host computer and the slave computer is used as a signal transmitting end, the other is used as a signal receiving end,
The slave comprises a reset state, an activation state and a transmission state, and the host comprises an activation state and a transmission state;
When the duration of the bus pulled down by the host is longer than a preset first duration, the slave enters a reset state;
When the slave is in a reset state and the time length of the master pulling down the bus is equal to a preset second time length, the signal receiving end enters an activated state, wherein the second time length is smaller than the first time length;
When the signal receiving end is in an activated state and the time length of the signal sending end for pulling down the bus is equal to a preset third time length, the signal receiving end enters a transmission state, wherein the third time length is related to the second time length;
When the signal receiving end is in a transmission state, the signal transmitting end transmits a data signal or a command signal to the signal receiving end.
Optionally, when the third duration is equal to one half of the second duration and the bit period is equal to the second duration, the signal transmitted by the bus is logic 0;
When the third duration is equal to three-half of the second duration and the bit period is equal to twice the second duration, the signal transmitted by the bus is logic 1.
Optionally, when the signal receiving end is in a transmission state and the signal transmitting end transmits 8 signal bits to the signal receiving end through the bus, the signal receiving end returns to an active state.
Optionally, when the duration of pulling down the bus by the signal sending terminal is equal to a preset third duration, the signal sending terminal sends 1 status bit through the bus;
when the number of bits of logic 1 in the status bit and the signal bit is greater than or equal to 5, the signal transmitting end transmits a command signal to the signal receiving end through the bus;
and when the number of bits of logic 1 in the status bits and the signal bits is smaller than or equal to 4, the signal transmitting end transmits a data signal to the signal receiving end through the bus.
Optionally, when the number of logic 1 contained in the set command signal sent by the signal sending end is less than or equal to 4, generating a corresponding command signal, wherein the state bit is logic 1, and the signal bit is opposite to the signal bit in the set command signal;
when the signal transmitting end transmits a set command signal, and the number of the set command signal containing logic 1 is more than or equal to 5, generating a corresponding command signal, wherein the state bit is logic 0, and the signal bit is the same as the signal bit in the set command signal;
When the number of the logic 1 contained in the set data signals sent by the signal sending end is smaller than or equal to 4, corresponding data signals are generated, state bits are logic 0, and signal bits are the same as those in the set data signals;
When the number of the logic 1 contained in the set data signals sent by the signal sending end is greater than or equal to 5, corresponding data signals are generated, the state bit is logic 1, and the signal bit is opposite to the signal bit in the set data signals.
Optionally, when the clock period of the signal receiving end is T, the pulse width in the signal sent by the signal sending end is greater than or equal to 3T.
Optionally, the second time period is greater than or equal to 2T.
Optionally, the second duration is less than two-thirds of the first duration.
Optionally, when the master determines that the response of the slave is over time, the master pulls down the bus for a period of time longer than a preset first period of time, so that the slave enters a reset state.
Optionally, the slave resets when the master continuously transmits a plurality of reset command signals to the slave.
Compared with the prior art, the application has the following beneficial effects:
The embodiment of the application provides a single-wire communication system, which comprises a host, a slave and a first resistor, wherein one end of the first resistor is connected with the bus, the other end of the first resistor is connected with a power supply, one of the host and the slave is used as a signal transmitting end, the other of the host and the slave is used as a signal receiving end, the slave comprises a reset state, an activated state and a transmission state, the host comprises the activated state and the transmission state, when the length of time of the bus pulled down by the host is longer than a preset first length, the slave enters the reset state, when the slave is in the reset state and the length of time of the bus pulled down by the signal transmitting end is equal to a preset second length, the signal receiving end enters the activated state, wherein the second length of time is shorter than the first length of time, when the signal receiving end is in the activated state and the length of time of the bus pulled down by the signal transmitting end is equal to a preset third length of time, the signal receiving end enters the transmission state, the third length of time is associated with the second length of time, and the signal receiving end transmits a data signal or a command signal to the signal receiving end. In the single-wire communication system provided by the application, the slave sets three states, and the host sets two states, so that signal transmission can be performed only in a specific state. And the time slices of communication can be defined by the host, so that the influence caused by the frequency instability of the slave is eliminated, and the system stability is improved.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a single-wire communication system according to an embodiment of the present application.
Fig. 2 is another circuit schematic diagram of a single-wire communication system according to an embodiment of the present application.
Fig. 3 is a state transition diagram of a slave according to an embodiment of the present application.
Fig. 4 is a first timing diagram of state transition of a slave according to an embodiment of the present application.
Fig. 5 is a second timing diagram of state transition of a slave according to an embodiment of the present application.
Fig. 6 is a third timing diagram of state transition of a slave according to an embodiment of the present application.
Fig. 7 is a fourth timing diagram of state transition of a slave according to an embodiment of the present application.
Fig. 8 is a schematic diagram of signal bits according to an embodiment of the present application.
Fig. 9 is another schematic diagram of signal bits according to an embodiment of the present application.
Fig. 10 is a schematic diagram of high priority transmission according to an embodiment of the present application.
Fig. 11 is a schematic diagram illustrating the division of data signals and command signals according to an embodiment of the present application.
Fig. 12 is a first schematic diagram of signal compiling according to an embodiment of the application.
Fig. 13 is a second schematic diagram of signal compiling according to an embodiment of the application.
Fig. 14 is a third schematic diagram of signal compiling according to an embodiment of the application.
Fig. 15 is a schematic diagram of timing sampling according to an embodiment of the present application.
Fig. 16 is another schematic diagram of timing sampling according to an embodiment of the present application.
Fig. 17 is a schematic diagram of driving a bus by a master and a slave according to an embodiment of the present application.
Fig. 18 is a schematic diagram of a host to slave initiated reset operation according to an embodiment of the present application.
FIG. 19 is a diagram illustrating encoding of command usage according to an embodiment of the present application.
Fig. 20 is a schematic diagram of a data transmission command according to an embodiment of the present application.
Fig. 21 is a schematic diagram of an address transmission command according to an embodiment of the present application.
FIG. 22 is a schematic diagram of a read data command according to an embodiment of the present application.
FIG. 23 is a schematic diagram of a read status command according to an embodiment of the present application.
Fig. 24 is a schematic diagram of a read fixed identification command according to an embodiment of the present application.
Fig. 25 is a schematic diagram of a read chip ID according to an embodiment of the present application.
Fig. 26 is a schematic diagram of a reset command according to an embodiment of the present application.
Fig. 27 is a schematic diagram of a query command according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
After the chip is manufactured, the chip needs to be tested and debugged. The test refers to that a chip designer needs to test after the chip is produced, screen out a faulty chip, correct the deviation of an internal circuit, and burn relevant data into a nonvolatile memory in the chip. The debugging means that at the user side, the user can use the interface as a communication interface to read and write the internal register of the chip for troubleshooting the problem, or program burning, single-step operation, breakpoint debugging and the like in the CPU (Central Processing Unit ) chip.
In the process of testing and debugging the chip, as described in the background art, in order to save the IO port, a single-wire communication mode may be adopted. However, the single-wire communication method has the problem of frequency sensitivity, and the voltage, temperature and process deviation in the chip can have influence on the frequency of the clock, and the influence has a larger influence on the stability of communication before the chip is not calibrated.
In view of this, the present application provides a single-wire communication system, which can achieve the effect of improving the stability of single-wire communication by setting a plurality of slave states and master states and defining a communication time slice by the master.
The single-wire communication system provided by the application is exemplified below:
As an alternative implementation manner, referring to fig. 1, the single-wire communication system includes a host, a slave and a resistor R0, where the host and the slave are connected by a bus, one end of the resistor R0 is connected to the bus, and the other end is connected to a power supply, and one of the host and the slave is used as a signal transmitting end, and the other is used as a signal receiving end.
That is, in the application, the host can send signals to the slave, and the slave can also send signals to the host, thereby realizing single-wire bidirectional communication. When the host reads the data of the slave, the slave sends the data to the host, and the slave is used as the signal transmitting end and the host is used as the signal receiving end. Of course, the control of the bus is mainly implemented by the host, specifically, after power-up, the bus is driven to a high level by the host, and the slave does not drive the bus.
Therefore, the slave has three states, namely a reset state, an active state and a transmission state, and the host has two states, namely an active state and a transmission state. The reset signal can only be initiated by the host, and the slave cannot initiate the reset. The slave drives the bus only if the host releases the bus after receiving the read command from the host. After the slave has sent the data, the bus should be actively de-driven. During the master and slave hand-offs, the common drive is high and the bus level is pulled high by resistor R0.
Therefore, in practical application, a chip to be tested or debugged can be used as a slave, and equipment for testing or debugging can be used as a host, and single-wire bidirectional communication is realized between the chip and the host through a bus. When no signal is transmitted between the two, the bus is pulled up through the resistor R0, and when the signal is required to be transmitted between the two, the bus is pulled down. And by controlling the time length of the bus pull-down, the slave or the host can enter different states and transmit different signals. It can be appreciated that the duration of the bus pull-down may be determined by the host, so that the time slices of the communication may be defined by the host, thereby eliminating the influence caused by the unstable slave frequency and improving the stability of the whole single-wire communication system.
It should be noted that "pull-up" and "pull-down" are the opposite concepts described in the present application. Generally, the bus level is high when the bus voltage is greater than the set value, and is low when the bus voltage is less than the set value. In fig. 1, since the resistor R0 is connected to the power source, the bus voltage is pulled to VCC by the resistor R0 when no signal is transmitted between the master and the slave. The voltage value of VCC is greater than the set value, if the voltage value of VCC is 3.3V, the bus voltage is pulled up to 3.3V. When the signal transmission is carried out between the host computer and the slave computer, the port of the host computer or the slave computer can be grounded, and the bus voltage is pulled down to 0V. Therefore, "pull-up" in the present application refers to pulling the bus voltage to the power supply voltage, where the bus voltage is at a high level, and "pull-down" in the present application refers to pulling the bus voltage to ground, where the bus voltage is at a low level.
Of course, in order to ensure that no failure occurs between the master and the slave due to direct connection, as an implementation manner, referring to fig. 2, the single-wire communication system may also include a master, a slave, a first resistor R1, and a second resistor R2, where one end of the second resistor R2 is connected to the master, and the other end is connected to the first resistor R1 and the slave, respectively, and the first resistor R1 is also connected to a power supply.
Similarly, after power up, the bus is pulled high. In addition, the master and the slave provided by the application both adopt push-pull output so as to further improve the stability of communication.
Referring to fig. 3, the slave includes a reset state, an active state, and a transfer state. The jump relation among the three states is that the reset state can jump to the active state, the active state can jump to the reset state or the transmission state, and the transmission state can jump to the reset state or the active state.
The method comprises the steps that when a host machine pulls down a bus for a period of time longer than a preset first period of time, a slave machine enters a reset state, when the slave machine is in the reset state and the period of time when the host machine pulls down the bus is equal to a preset second period of time, a signal receiving end enters an active state, and the second period of time is shorter than the first period of time. When the signal receiving end is in an activated state and the time length of the signal sending end for pulling down the bus is equal to a preset third time length, the signal receiving end enters a transmission state, wherein the third time length is related to the second time length. For example, the third time period and the second time period exhibit a multiple relationship. When the signal receiving terminal is in a transmission state, the signal transmitting terminal may transmit a data signal or a command signal to the signal receiving terminal. When the slave is in the active state and the transmission state, if the master transmits a signal to the slave, the slave serves as a signal receiving end, and the slave enters the active state and the transmission state. If the slave transmits a signal to the host, the host is used as a signal receiving end, and the host enters an activated state and a transmission state. It can be understood that the signal receiving end can only transmit and receive signals between the host and the slave when the signal receiving end is in a transmission state. The signal receiving end needs to be in a transmission state and needs to pass through a reset state and an activation state.
Therefore, referring to fig. 4, in any state, the host can make the slave enter the reset state by pulling down the bus for a time longer than T1 (a preset first duration). For example, when the master and the slave do not perform signal transmission, the bus voltage is pulled up. At this time, if signal transmission is required, the host may output a low level, for example, the port to which the host is connected to the bus is grounded, and the bus level is pulled low. And once the time when the level of the bus is pulled down reaches a preset first time length T1, the slave machine enters a reset state after receiving the level change of the bus.
In order to ensure that the slave device enters the reset state, when the master device pulls down the bus level, the time for pulling down the bus level may be greater than T1, so that the slave device can be ensured to enter the reset state. Also, in order to prevent noise interference, the duration of T1 is generally set to be relatively long, for example, to be several tens or hundreds ms. Therefore, when the power supply interference occurs and the bus is suddenly pulled down, the slave machine cannot enter the reset state under the condition because the time for pulling down the bus by the interference is shorter, and the stability of the slave machine entering the reset state is ensured.
In addition, referring to fig. 5, in the reset state, the signal receiving end can be brought into the active state by pulling down the time T2 (the preset second duration) of the bus.
The duration of T2 is smaller than the duration of T1, so that there is a large difference between the time of entering the reset state and the time of entering the active state, and confusion of the states is avoided. For example, after the slave enters the reset state, if the time for the master to pull down the bus reaches T2, the slave enters the active state. If the host continues to pull the bus low and the time of the pull-down reaches T1, the slave enters the reset state again. When the communication device jumps to the active state in the reset state, the pulse width can calibrate the communication frequency, so that the self calibration of the communication frequency can be realized.
Referring to fig. 6, in the active state, when the duration of pulling down the bus is equal to T3 (a preset third duration), the signal receiving end can be brought into the transmission state. Wherein the third time period is associated with the second time period. After entering a transmission state, the master and the slave can transmit signals. When the host receives the signal, the host enters the transmission state.
The association of the third time length and the second time length refers to the multiple relationship between the third time length and the second time length. And, for a preset third duration, different durations thereof may characterize different logic of the digital signal. Wherein the bit period characterizing a logic 0 is smaller than the bit period characterizing a 1.
Specifically, as shown in fig. 6, when the third duration is equal to one half of the second duration and the bit period T0 is equal to the second duration, the signal transmitted by the bus is logic 0. As shown in fig. 7, when the third duration is equal to three-thirds of the second duration and the bit period T0 is equal to twice the second duration, the signal transmitted by the bus is logic 1.
It will be appreciated that, after the signal receiving terminal enters the active state, whether a logic 1 or a logic 0 is transmitted in the bus will trigger the signal receiving terminal to enter the transmission state.
In the present application, bits transmitted between a master and a slave are divided into status bits and signal bits. The status bits are bits transmitted when jumping from an active state to a transmit state. That is, in fig. 6 and 7, after the signal receiving terminal enters the active state, when the status bit is received, the signal receiving terminal enters the transmission state regardless of whether the status bit is logic 0 or logic 1. After entering the transmission state, the transmitted bit is the signal bit.
And when the signal receiving end is in a transmission state, and the signal transmitting end transmits 8 signal bits to the signal receiving end through the bus, the signal receiving end returns to an active state. That is, in the present application, the transmission of signals is performed in a cycle-by-cycle manner, and for each cycle, includes 1 bit indicating the entry from the active state into the transmission state, and 8 bits indicating the specific signal. I.e. 9 bits are included in each transmission period. After the transmission of 9 bits is completed, the signal receiving end returns to an active state, and if the signal of the next period needs to be transmitted, the transmission of 9 bits is continued.
For example, referring to fig. 8, after entering the active state, 8 signal bits are transmitted between the master and the slave, and the signal bits may be logic 0 or logic 1. Illustratively, the signal bits are 00000000, 00100000, and so on. After transmitting 8 signal bits, the signal receiving end jumps to an active state. If the signal needs to be retransmitted, the signal transmitting end needs to retransmit the status bits, and the signal receiving end continues to transmit 8 signal bits after reentering the transmission status.
Thus, in one transmission period defined by the present application, the first bit is a status bit and the other 8 bits are signal bits. Of course, when transmitting signal bits, a continuous high level is allowed to be inserted in the middle of the signal bits. As shown in fig. 9, a high level is inserted between the third signal bit and the fourth signal bit.
Referring to fig. 10, in the present application, 8 signal bits are logic bit high priority transmission. In the figure, LIE represents status bits, B0 to B7 represent signal bits, and after transmitting the status bits, the signal receiving end enters a transmission state, and sequentially transmits the signal bits according to the high-order priority order of B7, B6, B5..
In the present application, the signals transmitted between the master and the slave include data signals and command signals. The data signal refers to specific data transmitted, such as temperature data, current data, and the like. And command signals refer to commands transmitted, such as reset, enable, etc.
In distinguishing command signals from data signals, referring to fig. 11, when the number of bits of logic 1 in the status bit and the signal bit is greater than or equal to 5, the signal transmitting end transmits the command signals to the signal receiving end through the bus, and when the number of bits of logic 1 in the status bit and the signal bit is less than or equal to 4, the signal transmitting end transmits the data signals to the signal receiving end through the bus. I.e. 9 bits are included in each transmission cycle, which characterizes the command signal if the number of logical 1 s is greater than or equal to 5 out of the 9 bits, and which characterizes the data signal if the number of logical 1 s is less than 5. For example, the signal transmitted in a certain transmission period is 111111111, which indicates that the command signal is transmitted in the transmission period, and the signal transmitted in a certain transmission period is 111100000, which indicates that the data signal is transmitted in the transmission period.
It should be noted that, by setting the transmission period, accurate division of the command signal and the data signal is ensured. And, since the bit period of the logic 0 is the second time period T2, the bit period of the logic 1 is twice the second time period T2. And the number of logic 0 is dominant in the transmitted data signal, so that the signal transmitted in unit time can be more for the data signal, and the data signal can be transmitted at a faster rate.
In the signal transmission of the master and the slave, the command signal occupies a smaller area, and most of the command signals are transmission data signals, so that the transmission rate of the whole system can be faster, and the transmission efficiency can be higher. Also, since the bit periods of logical 0 and logical 1 are different, adaptation of the communication rate can be achieved when the master and the slave communicate. For example, 111100000 and 000000000 are both data signals, but the transmission rates of the two data signals may not be the same, so that the communication rate is self-adaptive through the above arrangement mode.
On the basis of the implementation manner, when the specific signal is compiled, and when the state bit is 1, the signal bit is inverted, and the specific data signal or command signal is determined. When the status bit is 0, then the signal bit is unchanged.
In one implementation, referring to fig. 12, when signal compiling is performed, the original signal and the status bits need to be xored before being output. For example, when the original signal to be transmitted to the slave is 01010101 and the status bit is 1, the output is 0 because the working principle of the exclusive or gate is the same as the input level, and the output is 1 because the input level is different. Therefore, the output signal bit is 10101010. I.e. when compiling, the signal bits are opposite to the original signal. And when the status bit is 0, the signal bit is identical to the original bit.
On the basis, when the signal transmitting end transmits a set command signal, the number of the set command signal containing logic 1 is smaller than or equal to 4, corresponding command signals are generated, state bits are logic 1, the signal bits are opposite to the signal bits in the set command signal, when the signal transmitting end transmits the set command signal, the number of the set command signal containing logic 1 is larger than or equal to 5, corresponding command signals are generated, the state bits are logic 0, the signal bits are identical to the signal bits in the set command signal, when the signal transmitting end transmits the set data signal, the number of the set command signal containing logic 1 is smaller than or equal to 4, the state bits are logic 0, the signal bits are identical to the signal bits in the set data signal, when the signal transmitting end transmits the set data signal, the number of the set command signal containing logic 1 is larger than or equal to 5, the corresponding data signals are generated, the state bits are logic 1, and the signal bits are opposite to the signal bits in the set data signal.
For example, referring to fig. 13, when the transmitted signal is a command signal, if the original command signal to be transmitted is C7-C0, the status bit is determined according to the number of logical 1 s included in the original signal, if the number of logical 1 s included in the original signal is less than or equal to 4, the status bit is 1, and meanwhile, the original command signal is negated, and the signals to be transmitted are compiled, wherein the signals are 0, C7, C6., and C0. If the number of logical 1's is greater than or equal to 5, then the status bit is 0, while keeping the original command signal unchanged, and the signal is compiled into a signal to be transmitted, which is 0, C7, C6..
Referring to fig. 14, when the transmitted signal is a data signal, if the original data signal to be transmitted is D7-D0, determining a status bit according to the number of logical 1 s included in the original data signal, if the number of logical 1 s included in the original data signal is greater than or equal to 5, the status bit is 1, and meanwhile, de-encoding the original data signal into a signal to be transmitted, where the signal is 0, D7, D6.. If the number of logical 1's is less than or equal to 4, then the status bit is 0 while the original data signal is kept unchanged, and the signal is compiled into a signal to be transmitted, which is 0, D7, D6..
In addition, in order to ensure that the signal receiving end can stably sample the bus signal for at least 2 times, as an implementation manner, when the clock period of the signal receiving end is T, the pulse width in the signal sent by the signal sending end is greater than or equal to 3T.
For example, referring to fig. 15, when the slave is used as the signal receiving end, if the clock period of the slave is T, the width of the pulse width tprose_min in the signal sent by the master is greater than or equal to 3T. Taking the example that the width of the pulse width tprose_min is equal to 3T, in an extreme case, even if the rising edge or the falling edge (x in the figure) is sampled from the machine end, the bus signal can still be sampled at least 2 times under each pulse width, and the system sampling stability is improved.
And, the low level T2 transmitted in the active state should be greater than or equal to 2 times tprose_min, i.e. Tactive > =2×tprose_min. Thus, the second time period is greater than or equal to 6T. After receiving the activation pulse, the signal receiving end should record the sampling times of the low level of the activation pulse, and if the counting times are smaller than the low level times of the activation pulse, the signal receiving end is recorded as logic 0. If the count is greater than the low count of the active pulse, it is counted as a logic 1.
Referring to fig. 16, in the extreme case, t2=2×tprose_min, when logic 0 is transmitted, the number of times of sampling low level by the signal receiving end may be 2,3, 4, when logic 1 is transmitted, the number of times of sampling low level by the signal receiving end may be 8, 9, 10, and the number of times of sampling active low level may be 5, 6, 7, so as to avoid erroneous judgment when logic 0 and logic 1 are determined.
And, as an implementation manner, the second duration is less than two thirds of the first duration, so that the existence of interference can be avoided to make the logic 1 be misjudged as reset. I.e. the low level T2 sent at activation should be less than 2/3 x T1, i.e. T2<2/3 x T1. By the arrangement mode, a certain distance is kept between T2 and 2/3 x T1, and the situation that logic 1 is misjudged to be reset is effectively avoided.
As one implementation, the time of T1 is 256 clock cycles of the slave, i.e., t1=256×t.
In the application, the priority of the host is higher than that of the slave. That is, after power-up, the bus is driven high by the master, and the slave does not drive the bus. The slave drives the bus only if the host releases the bus after receiving the read command from the host. After the slave has sent the data, the bus should be actively de-driven. During the handover of the master and slave, the common drive is in a high-impedance state, and the bus level is pulled up to be high by the pull-up resistor R1.
Referring to fig. 17, after the host sends the read command (B2, B1, B0), the host releases the bus, and the slave starts driving the bus after a period of high impedance state Z1. Wherein, the post-Z1 LIE represents the status bit sent by the slave, after which the slave returns a signal bit to the master in the transmission state. And when the slave machine transmits data, the drive of the bus is automatically canceled. At this time, after a period of time of the high-impedance state Z2, the host drives the bus again. Namely LIE, B7-B0 after Z2 are used as hosts to drive the bus.
The slave should not send reset and activate operations when sending data to the master, but only return state or data, and the timing should also follow the master-to-slave timing. The definition of the state is consistent with the commands sent by the host to the slave. After the slave acquires the control right of the bus, if the slave generates an error once, the slave should actively report the error to the host before returning the data, and then return the data.
And, the master can drive the slave to reenter the reset state when the slave fails. For example, after the host sends a read command to the slave, the slave waits for a response and returns status or data, and if the slave does not respond within a certain time (e.g., 25 ms), it is determined that the time-out occurs, the host should take over the bus drive, and re-initiate the reset operation.
Referring to fig. 18, after the master sends the read command (B2, B1, B0) to the slave, if the slave does not respond within 25ms, i.e. the bus is in the high impedance state Z of 25ms, the master re-initiates the reset operation, so that the slave enters the reset state again.
Or the master and slave should detect if the drive level and the bus level agree when driving the level to the bus. If, while the host is driving the bus, a drive level and bus level inconsistency is detected, the host initiates a reset operation. If the slave machine detects that the driving level is inconsistent with the bus level when the slave machine drives the bus, the slave machine gives up driving the bus, turns to passive interception and receives the reset operation of the host machine.
And, the master and the slave should continue with the next 8 logical bits after receiving the first logical bit. As shown in connection with fig. 9, after entering the transfer state, a high level is allowed to be inserted between the logic bits, but if the time between the logic bits exceeds the T1 time, the transfer state should be exited, and then the received logic bits should be regarded as a new start. If the slave is receiving, the slave should record the error and report to the host after the next read request.
In the transmission process of the host and the slave, the following command protocols need to be followed:
when data transmission is carried out, a total of 256 data from 0x00 to 0xff are matched with commands, and when the data is transmitted, the number of 1 after 8B- >9B coding is not more than 4. And the data should have a CRC (Cyclic Redundancy Check ) check at the time of transmission.
Referring to fig. 19, the commands use 44 codes, in which the number of commands 1 is 6 after 8B- >9B codes, and no more than 3 consecutive identical codes exist, and other commands are regarded as illegal commands.
Referring to fig. 20, there are 11 data transfer commands, 0x23 is a 1-byte data transfer command, 0x25 is a 2-byte data transfer command, 0x26 is a 4-byte data transfer command, 0x29 is an 8-byte data transfer command, 0x2a is a 16-byte data transfer command, 0x2c is a 32-byte data transfer command, 0x45 is a 64-byte data transfer command, 0x46 is a 128-byte data transfer command, 0x49 is a 256-byte data transfer command, 0x4a is a 512-byte data transfer command, and 0x4c is a 1024-byte data transfer command.
Of course, the slave can selectively support the above commands. These commands are employed both in the transmission of data from the host to the slave and in the transmission of data from the slave to the host.
Referring to fig. 21, the address transfer command is 4 in total, 0x31 is a 1-byte address transfer, 0x32 is a 2-byte address transfer, 0x34 is a 4-byte address transfer, and 0x38 is an 8-byte address transfer. The slaves should selectively support the bit width of the address according to the scenario.
Referring to fig. 22, 0xb7 is a read command, and after the host has issued the command packet, the host should release the drive to the bus, and then the slave drives the bus to return data. Wherein DT is the data transfer command in fig. 20.
Referring to fig. 23, in the read status command, 0xbb is a read status command of the host to the slave, the host should release the drive to the bus after sending the command packet, then the slave drives the bus, returns status information using command 0xee, and the slave should clear the previous error status after returning the status information. In addition, the slave receives any read command, and if there is an error in the slave, the slave should actively transmit the status report first and then transmit the data.
The definition of the status register is shown in Table one:
List one
Referring to fig. 24, a read fixed identifier, 0xc4 is a command of reading fixed identifier from a host to a slave, the host should release the drive to the bus after sending out the command packet, and then the slave drives the bus to return fixed identifier information, and the returned data is ASCII code of "SWID".
Referring to fig. 25, the read chip ID,0xc8 is a read chip ID command of the host to the slave, and the host should release the driving of the bus after sending the command packet, and then the slave drives the bus to return the slave chip ID information. This command is used to distinguish between different chips.
When the host determines that the response of the slave is overtime, the host pulls down the bus for a period of time longer than a preset first period of time so that the slave enters a reset state. Referring to fig. 26, a reset command is provided, 0x77 is a reset command from the host to the slave, and the host sends the command 3 times in succession, so that the slave can be reset.
Referring to fig. 27,0xd7 is a query command initiated by the host to the slave, and after the host has issued the command packet, the host should release the drive to the bus, and then the slave drives the bus to return the slave query information. The query information is the length of data that the slave needs to return, and a value of 0 indicates that the data does not need to be returned. This command is used by the slave to initiate a data transfer to the master. After receiving the inquiry information, the host initiates a read request according to the data length, and reads the data in the slave machine
It should be noted that, the CRC8 calculation method provided in the present application uses a polynomial 0x131, that is:
CRC8=X8+X5+X4+1
In summary, the embodiment of the application provides a single-wire communication system, which comprises a host, a slave and a first resistor, wherein the host and the slave are connected through a bus, one end of the first resistor is connected with the bus, the other end of the first resistor is connected with a power supply, one of the host and the slave is used as a signal transmitting end, the other of the host and the slave is used as a signal receiving end, the slave comprises a reset state, an active state and a transmission state, the host comprises the active state and the transmission state, when the length of time for which the host pulls down the bus is longer than a preset first length, the slave enters the reset state, when the slave is in the reset state and the length of time for which the signal transmitting end pulls down the bus is equal to a preset second length, the signal receiving end enters the active state, wherein the second length of time is shorter than the first length of time, when the signal receiving end is in the active state and the length of time for which the signal transmitting end pulls down the bus is equal to a preset third length of time, the signal receiving end enters the transmission state, the third length of time is associated with the second length of time, and when the signal receiving end is in the transmission state, the signal receiving end sends a data signal or a command signal to the signal receiving end. In the single-wire communication system provided by the application, the slave sets three states, and the host sets two states, so that signal transmission can be performed only in a specific state. And the time slices of communication can be defined by the host, so that the influence caused by the frequency instability of the slave is eliminated, and the system stability is improved.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411366728.6A CN118860917B (en) | 2024-09-29 | 2024-09-29 | Single-wire communication system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411366728.6A CN118860917B (en) | 2024-09-29 | 2024-09-29 | Single-wire communication system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118860917A CN118860917A (en) | 2024-10-29 |
| CN118860917B true CN118860917B (en) | 2024-12-10 |
Family
ID=93168363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411366728.6A Active CN118860917B (en) | 2024-09-29 | 2024-09-29 | Single-wire communication system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118860917B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111339001A (en) * | 2020-03-09 | 2020-06-26 | 厦门润积集成电路技术有限公司 | Low-power-consumption single bus communication method and system |
| CN118277311A (en) * | 2024-03-06 | 2024-07-02 | 珠海格力电器股份有限公司 | Single bus communication method and device and computer equipment |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7752365B2 (en) * | 2008-04-01 | 2010-07-06 | Kyocera Corporation | Bi-directional single conductor interrupt line for communication bus |
| EP2466481A1 (en) * | 2010-12-02 | 2012-06-20 | Research In Motion Limited | Single wire bus system |
-
2024
- 2024-09-29 CN CN202411366728.6A patent/CN118860917B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111339001A (en) * | 2020-03-09 | 2020-06-26 | 厦门润积集成电路技术有限公司 | Low-power-consumption single bus communication method and system |
| CN118277311A (en) * | 2024-03-06 | 2024-07-02 | 珠海格力电器股份有限公司 | Single bus communication method and device and computer equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118860917A (en) | 2024-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10108578B2 (en) | Single wire communications interface and protocol | |
| US10955461B2 (en) | Smart and efficient protocol logic analyzer configured within automated test equipment (ATE) hardware | |
| US10929260B2 (en) | Traffic capture and debugging tools for identifying root causes of device failure during automated testing | |
| CN105261329B (en) | More LED display modules management methods | |
| US10592376B2 (en) | Real-time hierarchical protocol decoding | |
| CN111508551B (en) | Multifunctional automatic test system and method for solid state disk | |
| CN103793307A (en) | Electronic device, management method thereof and cabinet servo system | |
| CN102576342A (en) | Adjustment of memory write timing based on error detection techniques | |
| TWI534607B (en) | Memory control circuit unit, data transmitting method and memory storage apparatus | |
| CN110162446A (en) | A kind of backboard hard disk ignition method based on BMC | |
| CN112564882A (en) | Single-wire digital communication interface based on AHB bus | |
| CN112599179B (en) | Parallel flash life testing device | |
| CN112559267B (en) | Inter-integrated circuit bus I2C slave and I2C controller test method | |
| KR20140136204A (en) | Semiconductor system | |
| CN103149468A (en) | Electron component parameter testing device | |
| CN118860917B (en) | Single-wire communication system | |
| US10581555B2 (en) | Information processing device and burst error reproducing method | |
| CN104102561A (en) | Universal sequence bus testing device | |
| CN113034873A (en) | Sensor communication method, device and system | |
| CN117608883A (en) | Method and system for detecting computer system start-up fault in prototype verification | |
| CN101071394A (en) | Inter-board transparent transmission bus test device and method | |
| CN113268444B (en) | Position sensing chip interface circuit based on many Chuan agreements of rubbing realize | |
| CN115982087B (en) | Signal transmission method, computer device and storage medium | |
| US20180123936A1 (en) | Embedding analyzer functionality in storage devices | |
| CN117914442B (en) | Clock calibration method, clock calibration device, computer equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |