CN118829312A - Display panel - Google Patents

Abstract

The application discloses a display panel, which is provided with a display area and a binding area positioned at one side of the display area; the display panel comprises an array substrate positioned in the display area and the binding area and a plurality of fan-out wires positioned on the array substrate; the array substrate comprises a plurality of signal lines positioned in the display area; the fan-out wires are positioned in the display area and are electrically connected with at least part of the signal wires in a one-to-one correspondence manner; the fanout wiring is overlapped with part of the signal wires in the direction vertical to the array substrate. The application can reduce parasitic capacitance generated between the fan-out wiring and each signal of the display area.

Description

Display panel

The application relates to a divisional application with the application date 2022, 01 month and 12 days, the application number 202210033044.9 and the name of a display panel.

Technical Field

The application relates to the technical field of display, in particular to a display panel.

Background

With the continuous improvement of the display area ratio of an OLED (Organic LIGHT EMITTING DISPLAY, organic light emitting diode) panel, the design space reserved for the frame (Border) is continuously compressed, and the special-shaped design of the panel frame makes the original conventional design unable to meet the requirements.

A relatively large percentage of the space in the Border design is the portion of the signal line leading from the IC (integrated circuit) into the display area, which is typically fan-shaped, also referred to as fanout (fan-out) traces. In conventional designs, the fanout traces are typically located in the non-display region. In order to compress the fanout wiring space in recent years, fanout wiring line width and line distance can be improved in technology; limited to the bottleneck of process capability improvement, there are also ways to use different layers of metal as fanout traces.

Therefore, compressing fanout traces from the IC into the display area becomes key to the border compression, including the design of disposing fanout traces into the display area, i.e., fanout traces distributed in pixels of the display area, which not only can solve the problem of reduced design space caused by the border compression, but also can avoid routing fanout traces at the chamfer border, thereby solving the problem of insufficient special-shaped border space. However, the fanout traces also have problems in the display area, for example, parasitic capacitance generated between the fanout traces and the signal lines in the pixels causes a larger signal load (loading), which results in insufficient IC thrust and increased crosstalk risk.

Disclosure of Invention

The application provides a display panel, which can reduce parasitic capacitance generated between a fan-out wiring and each signal in a sub-pixel area of a display area, reduce signal load in the sub-pixel area, avoid insufficient IC thrust and reduce crosstalk risk, thereby improving the stability of the display panel.

The application provides a display panel, which is provided with a display area and a binding area positioned at one side of the display area; the display panel comprises an array substrate positioned in the display area and the binding area and a plurality of fan-out wires positioned on the array substrate;

The array substrate comprises a plurality of signal lines which are positioned in the display area and are distributed at intervals in a first direction; each of the signal lines extends in a second direction perpendicular to the first direction;

The fan-out wires are positioned in the display area and are electrically connected with at least part of the signal wires in a one-to-one correspondence manner; each fan-out wire comprises a first wire part which is arranged close to the binding area and extends along the second direction, and a second wire part which is connected with one end of the first wire part far away from the binding area and extends along the first direction;

Each first wire part is overlapped with one of the plurality of signal wires in the direction perpendicular to the array substrate, and one end of the second wire part, which is far away from the first wire part, is electrically connected with the corresponding signal wire.

Optionally, the width of the first trace portion is smaller than or equal to the width of the corresponding signal line.

Optionally, the plurality of signal lines form a plurality of signal line groups that are adjacently disposed in sequence in the first direction, and each signal line group includes a data line and a power supply voltage signal line that are adjacently disposed;

The fan-out wires are electrically connected with the data wires in a one-to-one correspondence manner; each first wiring part is overlapped with one data line or one power supply voltage signal line in the direction perpendicular to the array substrate.

Optionally, the display panel further includes a shielding layer located at a side of the plurality of fan-out wires away from the plurality of signal wires and disposed corresponding to the plurality of fan-out wires; the shielding layer is electrically connected with the power supply voltage signal line.

Optionally, the shielding layer includes a plurality of shielding wires corresponding to the fan-out wires one to one;

the width of the shielding wire is larger than or equal to the width of the fan-out wire, and smaller than or equal to the width of the signal wire.

Optionally, the power supply voltage signal line includes a first sub power supply voltage signal line and a second sub power supply voltage signal line stacked in a direction perpendicular to the array substrate; wherein the first sub power supply voltage signal line is electrically connected with the second sub power supply voltage signal line; the data line and the second sub-power supply voltage signal line are arranged on the same layer.

Optionally, the array substrate further includes a plurality of sub-pixel regions disposed in a plurality of rows and columns in the first direction and the second direction; each row of the sub-pixel areas is correspondingly arranged with one signal line group;

The sub-pixel region comprises a driving thin film transistor which is positioned at one side of the power supply voltage signal line far away from the fanout wiring and is electrically connected with the power supply voltage signal line in the corresponding signal line group.

Optionally, the plurality of first wire-walking parts form a plurality of first wire-walking part groups which are adjacently arranged in sequence in the first direction, and each first wire-walking part group comprises two first wire-walking parts which are adjacently arranged;

the first wiring part groups are overlapped with part of the signal line groups in the direction perpendicular to the array substrate.

Optionally, the array substrate includes a plurality of scan lines located in the display area and extending along the first direction;

each second wiring part is overlapped with one of the scanning lines in the direction perpendicular to the array substrate.

Optionally, the display panel further includes an organic light emitting layer located on a side of the plurality of fan-out wires away from the array substrate and electrically connected to the array substrate.

According to the display panel provided by the application, the first wiring part of the fanout wiring is distributed on the data line and the power supply voltage signal line in the display area, the data line and the power supply voltage signal line can form shielding between the fanout wiring and the driving circuit of the sub-pixel area, the influence of various complex signals in the fanout wiring and the sub-pixel area can be reduced, for example, parasitic capacitance generated between the fanout wiring and various signals in the sub-pixel area is reduced, the signal load in the sub-pixel area is reduced, the shortage of IC thrust is avoided, and the crosstalk risk is reduced, so that the stability of the display panel is improved.

Drawings

The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a partial routing distribution of a display panel according to an embodiment of the present application.

Fig. 2 is a schematic cross-sectional structure of a display panel according to an embodiment of the application.

Fig. 3 is a top view of a portion of a trace of a display panel according to an embodiment of the present application.

Fig. 4 is a schematic cross-sectional structure of another display panel according to an embodiment of the application.

Fig. 5 is a top view of a portion of a trace of another display panel according to an embodiment of the present application.

Fig. 6 is a schematic cross-sectional structure of another display panel according to an embodiment of the application.

Fig. 7 is a schematic cross-sectional structure of another display panel according to an embodiment of the application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.

In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

In the present application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.

The following disclosure provides many different embodiments, or examples, for implementing different features of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.

In the existing design of wiring the fan-out wiring in the pixel region of the display region, the source fan-out (soruce fanout) wiring output from the source IC (source integrated circuit) enters the display region, and is connected to the data line (data line) of the display region through punching, and parasitic capacitance is generated between the fan-out wiring in the display region and complex signals in the pixel region, so that the load of each signal is increased, and the IC thrust shortage and crosstalk risk are also increased. In particular, the fan-out wiring in the display region forms parasitic capacitance with the gate (Q point) of the driving TFT (ThinFilm Transistor ), affecting the stability of the driving TFT, thereby degrading the display quality of the panel.

The application optimizes the existing design of arranging the fan-out wiring in the display area, and provides different wiring design schemes in the display area so as to reduce the parasitic capacitance generated by the fan-out wiring in the display area and various signals in the pixel area, and particularly, the application relates to the following description of several embodiments.

Example 1

As shown in fig. 1 and 2, an embodiment of the present application provides a display panel 1, the display panel 1 having a display area 2 and a binding area 3 located at one side of the display area 2; the display panel 1 comprises an array substrate 4 located in the display area 2 and the binding area 3, a plurality of fan-out wires 5 located on the array substrate 4, and an organic light emitting layer 6 located on one side of the plurality of fan-out wires 5 away from the array substrate 4 and electrically connected with the array substrate 4.

The array substrate 4 includes a plurality of signal lines 7 located in the display area 2 and arranged at intervals in a first direction (e.g., a horizontal direction); each signal line 7 extends in a second direction (for example, a vertical direction) perpendicular to the first direction.

Specifically, as shown in fig. 2, the array substrate 4 further includes a substrate 8, a buffer layer 9 and a thin film transistor layer 10 sequentially disposed on the substrate 8; the plurality of signal lines 7 are located on the thin film transistor layer 10 and electrically connected to the thin film transistors in the thin film transistor layer 10. In a specific embodiment, the substrate 8 is composed of a first PI (polyimide) substrate 11, a first glass substrate 12, a second PI substrate 13, and a second glass substrate 14 stacked in this order.

The fan-out wires 5 are located in the display area 2 and are electrically connected with at least part of the signal wires 7 in a one-to-one correspondence. As shown in fig. 1, each fan-out trace 5 includes a first trace portion 15 disposed near the binding region 3 and extending in the second direction, and a second trace portion 16 connected to an end of the first trace portion 15 remote from the binding region 3 and extending in the first direction. Each of the first routing portions 15 is disposed to overlap one of the plurality of signal lines 7 in a direction perpendicular to the array substrate 4, and one end of the second routing portion 16 remote from the first routing portion 15 is electrically connected to the corresponding signal line 7.

It will be appreciated that an insulating layer is provided between the plurality of fanout traces 5 and the plurality of signal lines 7.

It should be noted that, the overlapping arrangement in the present application refers to the projection overlapping of two traces of different layers (different layers) in the direction perpendicular to the array substrate 4.

Specifically, the second wiring portion 16 and the first wiring portion 15 may be disposed on the same layer or different layers, which is not limited by the present application. When the second wiring portion 16 and the first wiring portion 15 are arranged in different layers, the two are connected through a via hole.

Specifically, as shown in fig. 3, the width of the first trace portion 15 is smaller than or equal to the width of the corresponding signal line 7. In a specific embodiment, the width of the first trace portion 15 is the same as the width of the second trace portion 16.

In one embodiment, as shown in fig. 1 and 3, the plurality of signal lines 7 form a plurality of signal line groups 17 disposed adjacent to each other in the first direction, each signal line group 17 including a data line 18 and a power supply voltage signal line 19 disposed adjacent to each other; the fan-out wires 5 are electrically connected with the data wires 18 in a one-to-one correspondence manner; each of the first wiring portions 15 is disposed to overlap one of the data lines 18 or the power supply voltage signal lines 19 in a direction perpendicular to the array substrate 4.

It is to be understood that the plurality of signal lines 7 include a plurality of data lines (D1-Dn, where n is a positive integer) 18 and a plurality of power supply voltage signal lines 19 provided corresponding to the plurality of data lines 18.

Specifically, the power supply voltage signal line 19 includes a VDD trace. It will be appreciated that the VDD trace is connected to a high VDD signal.

Specifically, as shown in fig. 1, the binding area 3 is spaced from the display area 2 in the second direction. The display panel 1 further includes a source IC20 bonded to the bonding area 3, and the first trace portions 15 of the fan-out traces 5 extend to be connected to the source IC20 near a side of the bonding area 3, for transmitting an electrical signal output from the source IC20 to the data line 18.

Specifically, as shown in fig. 1, the plurality of first routing parts 15 form a plurality of first routing part groups 21 that are sequentially and adjacently arranged in the first direction, and each first routing part group 21 includes two first routing parts 15 that are adjacently arranged; the plurality of first routing part groups 21 are arranged to overlap with part of the signal line groups 17 in the plurality of signal line groups 17 in a direction perpendicular to the array substrate 4. In a specific embodiment, the plurality of signal line groups 17 overlapped with the plurality of first line groups 21 are located at the middle part of the display area 2 and are sequentially adjacent to each other, so that the area of the binding area 3 can be effectively reduced; of course, the specific positions of the plurality of signal line groups 17 disposed overlapping the plurality of first trace groups 21 may be adjusted according to the positions of the bonding regions 3. It can be understood that the first trace portions 15 of the fan-out trace 5 are sequentially and alternately arranged to overlap the data line 18 and the power supply voltage signal line 19, for example, an odd number of first trace portions 15 are arranged to overlap the data line 18, an even number of first trace portions 15 are arranged to overlap the power supply voltage signal line 19, and two first trace portions 15 in any one of the first trace portion groups 21 are arranged to overlap the adjacently arranged data line 18 and power supply voltage signal line 19. Since the number of the power supply voltage signal lines 19 is the same as the number of the data lines 18, the number of the first routing parts 15 overlapped with the data lines 18 is half of the number of the data lines 18, and the area occupied by the whole of the plurality of first routing parts 15 can be effectively reduced, so that the area of the binding area 3 is reduced.

Specifically, the array substrate 4 further includes a plurality of scan lines (not shown) located in the display area 2 and extending along the first direction. In a specific embodiment, each of the second trace portions 16 is disposed to overlap one of the plurality of scan lines in a direction perpendicular to the array substrate 4. Of course, in other embodiments, the second trace portion 16 is disposed only parallel to the scan line.

Specifically, the array substrate 4 further includes a plurality of sub-pixel regions 22 disposed in a plurality of rows and columns in the first direction and the second direction, and a driving circuit (not shown in the drawing) located in the sub-pixel regions 22. Each column of the sub-pixel regions 22 is disposed corresponding to one signal line group 17, and each row of the sub-pixel regions 22 is disposed corresponding to one scanning line.

Specifically, the driving circuit includes a driving thin film transistor 23 and a switching thin film transistor (not shown) in the thin film transistor layer 10; the source of the driving thin film transistor 23 is electrically connected to the power supply voltage signal line 19 in the corresponding signal line group 17, and the source of the switching thin film transistor is electrically connected to the data line 18 in the corresponding signal line group 17.

In one embodiment, as shown in fig. 2, the driving thin film transistor 23 includes a semiconductor layer 24 disposed on the buffer layer 9, a source electrode 25 and a drain electrode 26 disposed on both sides of the semiconductor layer 24, a first gate insulating layer 27 covering the semiconductor layer 24, the source electrode 25 and the drain electrode 26, a first gate electrode 28 disposed on the first gate insulating layer 27 and corresponding to the semiconductor layer 24, a second gate insulating layer 29 covering the first gate electrode 28 and the first gate insulating layer 27, a second gate electrode 30 disposed on the second gate insulating layer 29 and corresponding to the first gate electrode 28, an interlayer insulating layer 31 covering the second gate electrode 30 and the second gate insulating layer 29, a via hole penetrating the first gate insulating layer 27, the second gate insulating layer 29 and the interlayer insulating layer 31 and respectively connected to the source electrode 25 and the drain electrode 26, and a connector 32 filled in the via hole. Specifically, the connection body 32 connected to the source electrode 25 of the driving thin film transistor 23 is connected to the power supply voltage signal line 19.

In one embodiment, the material of the source electrode 25 and the drain electrode 26 is polysilicon (poly), however, the material of the source electrode 25 and the drain electrode 26 is not limited in the present application. The scan lines may be disposed in the same layer as the first gate electrode 28 and/or the second gate electrode 30, although the application is not limited in this respect.

It should be noted that, in the embodiment of the present application, the data line 18 is connected to the source of the switching thin film transistor, and in a specific embodiment, the source of the switching thin film transistor and the source 25 of the driving thin film transistor 23 may be disposed in the same layer and made of the same material. Of course, the position of the source electrode of the switching thin film transistor is not limited, and the structure of the switching thin film transistor is not limited.

Specifically, as shown in fig. 2, the display panel 1 further includes a first planarization layer 33 covering the data lines 18 and the power voltage signal lines 19, and a second planarization layer 34 covering the plurality of fan-out traces 5. It will be appreciated that the plurality of fan-out traces 5 are located on the first planarization layer 33.

Specifically, as shown in fig. 2, the organic light emitting layer 6 is disposed on the second planarization layer 34. The organic light emitting layer 6 specifically includes an anode layer 35, a pixel defining layer 36, a light emitting functional layer 37, a support layer 38, and a cathode layer 39. The anode layer 35 is disposed on the second flat layer 34, and the pixel defining layer 36 is disposed on the second flat layer 34 and has a plurality of pixel openings, wherein the pixel openings are disposed corresponding to the anode layer 35. The light emitting functional layer 37 is located on the anode layer 35 of the pixel opening; the support layer 38 is located on the pixel definition layer 36; the cathode layer 39 covers at least the light-emitting functional layer 37.

Specifically, the anode layer 35 is electrically connected to the drain electrode 26 of the driving thin film transistor 23. In a specific embodiment, the display panel 1 further includes a first source-drain electrode block 40 disposed at the same layer as the data line 18 and the power voltage signal line 19, and a second source-drain electrode block 41 disposed at the same layer as the plurality of fan-out wirings 5. Wherein the second source-drain electrode block 41 is electrically connected to the first source-drain electrode block 40 through a via hole penetrating the first planarization layer 33; the first source-drain electrode block 40 is electrically connected to the drain electrode 26 of the driving thin film transistor 23 through the connection body 32, and the anode layer 35 is also electrically connected to the second source-drain electrode block 41 through a via hole penetrating the second planarization layer 34.

It will be appreciated that the first source-drain electrode block 40 is integrally formed with the connector 32.

It should be noted that the present application is also applicable to gate fanout (gate fan-out) routing design of display products driven by gate ICs. The key point of the embodiment of the present application is that soruce fanout (i.e. data fanout) wirings are designed on the data line and the power supply voltage signal line of the display area, and the gate electrode can be a conventional design driven by GOA, which is not specifically described in the present application.

In this embodiment, the first wiring portion 15 of the fan-out wiring 5 is distributed on the data line 18 and the power supply voltage signal line 19 in the display area 2, and the data line 18 and the power supply voltage signal line 19 can form shielding between the fan-out wiring 5 and the driving circuit of the sub-pixel area 22, so that the influence of complex signals in the fan-out wiring 5 and the sub-pixel area 22 can be reduced, for example, parasitic capacitance generated between the fan-out wiring 5 and the signals in the sub-pixel area 22 is reduced, the signal load in the sub-pixel area 22 is reduced, the IC thrust shortage is avoided, and the crosstalk risk is reduced. In particular, the embodiment of the present application may reduce parasitic capacitance between the fanout line 5 and the gate electrode (e.g., the first gate electrode 28 and the second gate electrode 30) of the driving thin film transistor 23 in the sub-pixel region 22, and increase stability of the driving thin film transistor 23, thereby improving stability of the display panel 1.

Example two

As shown in fig. 1, 4 and 5, the embodiment of the present application further provides a display panel 1, which is different from the above embodiment in that the display panel 1 in the embodiment of the present application further includes a shielding layer 42 located on a side of the plurality of fan-out wires 5 away from the plurality of signal wires 7 and disposed corresponding to the plurality of fan-out wires 5; the shielding layer 42 is electrically connected to the power supply voltage signal line 19.

Specifically, as shown in fig. 5, the shielding layer 42 includes a plurality of shielding wires 43 that are disposed in one-to-one correspondence with the plurality of fan-out wires 5; the width of the shielding trace 43 is greater than or equal to the width of the corresponding fan-out trace 5 and less than or equal to the width of the corresponding signal line 7. It will be appreciated that each of the shadow traces 43 is connected to the VDD signal.

Specifically, as shown in fig. 4, the masking layer 42 is located on the second planarization layer 34. The display panel 1 further includes a third planarization layer 44 between the shielding layer 42 and the organic light emitting layer 6, and a third source-drain electrode block 45 disposed in the same layer as the shielding layer 42. The third source-drain electrode block 45 is electrically connected to the second source-drain electrode block 41 through a via hole penetrating the second planarization layer 34; the anode layer 35 is electrically connected to the third source-drain electrode block 45 through a via hole penetrating the third planarization layer 44.

Specifically, the shielding trace 43 is electrically connected to the corresponding power voltage signal line 19 through a via hole penetrating the first and second planarization layers 33 and 34 to access the VDD signal of high potential.

In this embodiment, a metal layer is added to the fan-out wire 5 distributed on the data line 18 and the power voltage signal line 19 to serve as the shielding layer 42, and the shielding layer 42 is connected to the VDD signal with high potential, so that parasitic capacitance generated between the fan-out wire 5 and each signal in the sub-pixel region 22 can be further reduced, especially parasitic capacitance generated between the fan-out wire 5 and the gate of the driving thin film transistor 23 is reduced, and stability of the driving thin film transistor 23 is increased. Therefore, the embodiment of the application further reduces the signal load in the sub-pixel area 22, avoids the shortage of the IC thrust, reduces the crosstalk risk and improves the stability of the display panel 1.

Example III

As shown in fig. 1 and 6, the embodiment of the present application further provides a display panel 1, which is different from the above-described embodiment in that the power supply voltage signal line 19 in the embodiment of the present application includes a first sub-power supply voltage signal line 46 and a second sub-power supply voltage signal line 47 that are stacked in different layers in a direction perpendicular to the array substrate 4; wherein the first sub power supply voltage signal line 46 is electrically connected to the second sub power supply voltage signal line 47; the data line 18 is arranged in the same layer as the second sub power supply voltage signal line 47. It will be appreciated that an insulating layer, hereinafter referred to as the first planarization layer 33, is provided between the first sub-power voltage signal line 46 and the second sub-power voltage signal line 47.

Specifically, as shown in fig. 6, the display panel 1 in the embodiment of the present application further includes a source electrode block 48 disposed on the same layer as the first sub-power voltage signal line 46 and disposed corresponding to the data line 18, the first planarization layer 33 in the embodiment of the present application is disposed between the first sub-power voltage signal line 46 and the second sub-power voltage signal line 47, and the second planarization layer 34 is disposed between the plurality of signal lines 7 and the plurality of fan-out traces 5; the first source-drain electrode block 40 is arranged in the same layer as the first sub power supply voltage signal line 46, and the second source-drain electrode block 41 is arranged in the same layer as the second sub power supply voltage signal line 47. The second sub power supply voltage signal line 47 is electrically connected to the first sub power supply voltage signal line 46 through a via hole penetrating the first planarization layer 33.

Specifically, the display panel 1in the embodiment of the present application further includes a third flat layer 44 disposed between the fanout line 5 and the organic light emitting layer 6, and a third source-drain electrode block 45 disposed on the same layer as the fanout line 5; the third source-drain electrode block 45 is electrically connected to the second source-drain electrode block 41 through a via hole penetrating the second planarization layer 34, and the anode layer 35 is electrically connected to the third source-drain electrode block 45 through a via hole penetrating the third planarization layer 44.

In this embodiment, the power supply voltage signal line 19 is formed by the first sub-power supply voltage signal line 46 and the second sub-power supply voltage signal line 47, and has a double-layer wiring structure, so that the distances between the fan-out wiring 5 and the data line 18 and the signal line (for example, the gate of the driving thin film transistor 23) in the sub-pixel region 22 are increased, and the parasitic capacitance is further reduced; and the power voltage signal line 19 adopts a double-layer wiring structure, so that the problem of overlarge VDD signal load can be reduced, and the display uniformity of the display panel 1 is improved. Therefore, the embodiment of the application further reduces the signal load in the sub-pixel area 22 and the VDD signal load, avoids the shortage of IC thrust, reduces the risk of crosstalk, and improves the stability and the display uniformity of the display panel 1.

Example IV

As shown in fig. 1 and fig. 7, the embodiment of the present application further provides a display panel 1, which is different from the third embodiment in that the display panel 1 in the embodiment of the present application further includes a shielding layer 42 located on a side of the plurality of fan-out wires 5 away from the plurality of signal wires 7 and disposed corresponding to the plurality of fan-out wires 5; the shielding layer 42 is electrically connected to the power supply voltage signal line 19, in particular to the second sub-power supply voltage signal line 47.

Specifically, the shielding layer 42 includes a plurality of shielding wires 43 that are disposed in one-to-one correspondence with the plurality of fan-out wires 5; the width of the shielding trace 43 is greater than or equal to the width of the corresponding fan-out trace 5 and less than or equal to the width of the corresponding signal line 7. It will be appreciated that each of the shadow traces 43 is connected to the VDD signal.

Specifically, the third planarization layer 44 in the embodiment of the present application is disposed between the shielding layer 42 and the organic light emitting layer 6, and the display panel 1 in the embodiment of the present application further includes a passivation layer 49 disposed between the fan-out line 5 and the shielding layer 42, and a fourth source-drain electrode block 50 disposed in the same layer as the shielding layer 42. The fourth source-drain electrode block 50 is electrically connected to the third source-drain electrode block 45 through a via hole penetrating the passivation layer 49; the anode layer 35 is electrically connected to the fourth source-drain electrode block 50 through a via hole penetrating the third planarization layer 44, and the shielding layer 42 is electrically connected to the second sub-power voltage signal line 47 through a via hole penetrating the passivation layer 49 and the second planarization layer 34.

In this embodiment, a metal layer is added on the basis of the shielding layer 42, so that the power supply voltage signal line 19 is a double-layer wiring structure formed by the first sub-power supply voltage signal line 46 and the second sub-power supply voltage signal line 47, and the distances between the fan-out wiring 5 and the data line 18 and the signal line (for example, the gate electrode of the driving thin film transistor 23) in the sub-pixel region 22 are increased, so that the parasitic capacitance is further reduced; and the power voltage signal line 19 adopts a double-layer wiring structure, so that the problem of overlarge VDD signal load can be reduced, and the display uniformity of the display panel 1 is improved. Therefore, the embodiment of the application further reduces the signal load in the sub-pixel area 22 and the VDD signal load, avoids the shortage of IC thrust, reduces the risk of crosstalk, and improves the stability and the display uniformity of the display panel 1.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The foregoing has described in detail a display panel provided by embodiments of the present application, and specific examples have been applied to illustrate the principles and embodiments of the present application, where the foregoing examples are only for aiding in understanding of the technical solution and core idea of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims (10)

1. A display panel, characterized by having a display area and a binding area located at one side of the display area; the display panel comprises an array substrate positioned in the display area and the binding area and a plurality of fan-out wires positioned on the array substrate;

The array substrate comprises a plurality of signal lines positioned in the display area; the fan-out wires are positioned in the display area and are electrically connected with at least part of the signal wires in a one-to-one correspondence manner; the fan-out wiring is overlapped with part of the signal lines in the plurality of signal lines in the direction perpendicular to the array substrate.

2. The display panel of claim 1, wherein the fan-out trace includes a first trace portion disposed proximate to the binding region and extending in a second direction and a second trace portion connected to an end of the first trace portion remote from the binding region and extending in the first direction; the first direction and the second direction are perpendicular to each other;

One end of the second wire part far away from the first wire part is electrically connected with the corresponding signal wire; at least part of the first wiring part is overlapped with part of the signal wires in the plurality of signal wires.

3. The display panel of claim 2, wherein the plurality of signal lines include a plurality of data lines arranged at intervals in the first direction and extending along the second direction, the plurality of fan-out traces being electrically connected to the plurality of data lines in one-to-one correspondence; one end of the second wire part far away from the first wire part is electrically connected with the corresponding data wire; the first wiring part is overlapped with one of the plurality of data lines.

4. The display panel of claim 2, wherein the plurality of signal lines includes at least one power supply voltage signal line, and at least one of the fan-out traces is disposed to overlap the power supply voltage signal line.

5. The display panel according to claim 4, wherein at least a part of the power supply voltage signal lines extend in the second direction, and at least a part of the first wiring portions are disposed to overlap with the power supply voltage signal lines extending in the second direction.

6. The display panel according to claim 4, wherein the power supply voltage signal line includes a first sub power supply voltage signal line and a second sub power supply voltage signal line stacked in a direction perpendicular to the array substrate; the first sub power supply voltage signal line is electrically connected with the second sub power supply voltage signal line; at least one fan-out wire is overlapped with the first sub-power supply voltage signal wire and/or the second sub-power supply voltage signal wire.

7. The display panel of any one of claims 1 to 6, wherein a width of the fan-out trace at an overlapping position is less than or equal to a width of the corresponding signal line.

8. The display panel according to any one of claims 4 to 6, further comprising a shielding layer located on a side of the plurality of fan-out wires away from the plurality of signal wires and disposed corresponding to the plurality of fan-out wires; the shielding layer is electrically connected with the power supply voltage signal line.

9. The display panel of claim 8, wherein the shielding layer comprises a plurality of shielding traces disposed in one-to-one correspondence with the plurality of fan-out traces;

the width of the shielding wire is larger than or equal to the width of the fan-out wire, and smaller than or equal to the width of the signal wire.

10. The display panel of claim 2, wherein the array substrate includes a plurality of scan lines located in the display region and extending along the first direction;

at least part of the second wiring part is overlapped with one of the scanning lines in the direction perpendicular to the array substrate.