CN118819732A - Interrupt virtualization processing method, device, equipment and storage medium - Google Patents
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Abstract
The invention relates to an interrupt virtualization processing method, device, equipment and storage medium, which comprise the steps of writing a target virtual machine identifier and current state information of a target virtual machine entering interrupt processing into a virtual machine control structure; when a control target virtual machine is started, writing current state information of a virtual machine control structure of the target virtual machine into a target shadow register corresponding to a target virtual machine identifier; and the control target virtual machine reads the current state information of the target virtual machine from the target shadow register so as to enable the target virtual machine to recover to the state before interrupt processing according to the current state information. The embodiment of the invention improves the concurrency processing capability.
Description
Technical Field
The present invention relates to the field of virtualization technologies, and in particular, to an interrupt virtualization processing method, device, equipment, and storage medium.
Background
In a specific implementation, interrupt processing is entered when a peripheral device (such as a keyboard, a mouse, a printer, a network interface card, etc.) needs a CPU (Central Processing Unit ) in a physical device to process its requirements, so that the CPU pauses a task currently being executed, so that the requirements of the peripheral device can be satisfied in time. For example, assuming that the CPU is currently executing a task of scanning the hardware of the computer, when the user presses a key on the keyboard, the keyboard controller sends an interrupt request to notify the CPU that there is input data of the keyboard to be processed, and at this time, the CPU pauses the task of scanning the hardware of the computer and enters interrupt processing.
Where interrupt processing is implemented in a virtualized environment, the interrupt processing may be referred to as interrupt virtualization processing. A virtualized environment refers to a computing environment that includes one or more Virtual Machines (VMs) created and managed by a Virtual Machine monitor (VMM, virtual Machine Monitor). In a virtualized environment, in response to an event that triggers interrupt processing by a peripheral device, which requires attention from a virtual machine monitor to a vCPU (Virtual Central Processing Unit ) assigned to the virtual machine, the vCPU enters interrupt processing so that the vCPU preferentially executes events by the peripheral device. However, conventional interrupt handling methods may cause physical device (host) performance bottlenecks for virtual machines, especially when interrupts for multiple virtual machines occur simultaneously.
Disclosure of Invention
The invention aims to provide an interrupt virtualization processing method which can reduce the influence of interrupt processing on the performance of virtual machines of physical equipment when interrupts of a plurality of virtual machines occur simultaneously.
In order to achieve the above object, an embodiment of the present invention provides an interrupt virtualization processing method, which is applied to a physical device, where the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and the virtual machines respectively have corresponding virtual machine identifiers, and the method includes:
Writing a target virtual machine identifier and current state information of a target virtual machine entering interrupt processing into the virtual machine control structure;
when the target virtual machine is controlled to start, writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier;
And controlling the target virtual machine to read the current state information of the target virtual machine from the target shadow register so as to enable the target virtual machine to recover the state before interrupt processing according to the current state information.
Optionally, writing the target virtual machine identifier and the current state information of the target virtual machine entering the interrupt processing into the virtual machine control structure includes:
When the virtual machine monitor triggers a target virtual machine to perform interrupt processing, the current state information of the target virtual machine is controlled to be written into a virtual machine control structure of the target virtual machine before the target virtual machine exits, and the target virtual machine identification and the current state information of the target virtual machine are written into the virtual machine control structure.
Optionally, when the virtual machine monitor triggers the target virtual machine to perform interrupt processing, the controlling the target virtual machine to write current state information of the target virtual machine into a virtual machine control structure of the target virtual machine before exiting, and writing the current state information of the target virtual machine into the virtual machine control structure according to a target virtual machine identifier of the target virtual machine, including:
In the process of executing the virtual machine, if the target virtual machine receives an interrupt signal sent by the virtual machine monitor, triggering the target virtual machine to switch from a virtual machine mode to a virtual machine monitor mode;
before the target virtual machine is controlled to exit, the current state information of the target virtual machine is stored in a virtual machine control structure, and a target virtual machine identification of the target virtual machine is written in the virtual machine control structure.
Optionally, the storing the current state information of the target virtual machine in a virtual machine control structure, and writing the target virtual machine identifier of the target virtual machine into the virtual machine control structure, includes:
storing the current state information of the target virtual machine into a client state area of a virtual machine control structure, and writing a target virtual machine identification of the target virtual machine into an interrupt information field register of the virtual machine control structure.
Optionally, the method further comprises:
and configuring the virtual machine control structure of the virtual machine.
Optionally, the configuring the virtual machine control structure of the virtual machine includes:
configuring a control domain of the virtual machine control structure of the virtual machine;
The guest state area of the virtual machine control structure of the virtual machine is configured.
Optionally, before controlling the target virtual machine to exit, the method further includes:
the target virtual machine identifies an interrupt source and determines an interrupt type number according to the interrupt source;
And inquiring an entry address of a corresponding interrupt service routine from an interrupt descriptor table of the shadow register according to the interrupt type number so as to jump to the interrupt service routine according to the entry address to perform interrupt processing.
Optionally, the method further comprises:
modifying a virtual machine starting instruction of the virtual machine; and when the modified virtual machine starting instruction is executed, reading a virtual machine identifier from a virtual machine control structure of the started virtual machine.
Optionally, the reading, when controlling the target virtual machine to start, a target virtual machine identifier of the target virtual machine from the virtual machine control structure of the target virtual machine includes:
triggering the target virtual machine to switch from a virtual machine monitor mode to a virtual machine mode when the virtual machine starting instruction after the modification is executed controls the target virtual machine to start;
and reading a target virtual machine identification of the target virtual machine from the virtual machine control structure of the target virtual machine.
Optionally, the reading, from the virtual machine control structure of the target virtual machine, a target virtual machine identification of the target virtual machine includes:
And executing a virtual machine reading instruction to read a target virtual machine identification of the target virtual machine from an interrupt information field register of the virtual machine control structure of the target virtual machine.
Optionally, after the writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identification, the method further includes:
Writing other contents of the virtual machine control structure of the target virtual machine into corresponding other registers; the other content includes at least the content of the segment register.
Optionally, the target virtual machine is one or more, and the shadow register is one or more.
The embodiment of the invention also discloses an interrupt virtualization processing device which is applied to physical equipment, wherein the physical equipment comprises a virtual machine monitor, each virtual machine of the physical equipment is configured with a shadow register, each virtual machine is provided with a corresponding virtual machine identifier, and the device is used for realizing the method according to the embodiment of the invention.
The embodiment of the invention also discloses an electronic device, which comprises at least one processor and a memory in communication connection with the at least one processor;
the memory is used for storing a computer program;
The processor is configured to implement the method according to the embodiment of the present invention when executing the program stored in the memory.
Embodiments of the present invention also disclose a computer-readable storage medium having stored thereon a computer program which, when executed by one or more processors, causes the processors to perform the method according to the embodiments of the present invention.
The invention has the beneficial effects that:
The embodiment of the invention is applied to physical equipment, the physical equipment comprises a virtual machine monitor, each virtual machine of the physical equipment is provided with a shadow register, each virtual machine is provided with a corresponding virtual machine identifier, when one or more virtual machines trigger interrupt processing, the virtual machine entering the interrupt processing is used as a target virtual machine, and the current state information of the target virtual machine and the target virtual machine identifier are written into a virtual machine control structure; when the control target virtual machine is started, the current state information of the virtual machine control structure of the target virtual machine is written into a target shadow register corresponding to the target virtual machine identification, and the control target virtual machine reads the current state information of the target virtual machine from the target shadow register so that the target virtual machine is restored to the state before interrupt processing according to the current state information. According to the embodiment of the invention, the physical shadow registers are respectively configured for the processor of each virtual machine of the physical equipment, and when one or more virtual machines enter interrupt processing, the state before interrupt processing can be restored in parallel through the corresponding shadow registers, so that the concurrency processing capacity of the physical equipment is improved, and the influence of interrupt processing on the performance of the virtual machines of the physical equipment is reduced.
Drawings
FIG. 1 is a schematic diagram of an interrupt generation method of a conventional peripheral device in an Arm architecture;
FIG. 2 is a schematic diagram of an interrupt generation method for a new peripheral device in the Arm architecture;
FIG. 3 is a schematic diagram of a hardware interrupt handling process at x 86;
FIG. 4 is a schematic diagram of an implementation of a hardware-assisted virtualization technique under x 86;
FIG. 5 is a schematic diagram illustrating an implementation of interrupt virtualization of a current multi-virtual machine;
FIG. 6 is a flowchart illustrating a method for interrupt virtualization processing according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating an implementation of parallel interrupt virtualization of multiple virtual machines according to an embodiment of the present invention;
FIG. 8 is a schematic illustration of an area of a VMCS provided in an embodiment of the present invention;
FIG. 9 is one of the schematic diagrams of a control domain configuration of a VMCS provided in an embodiment of the present invention;
FIG. 10 is a second schematic diagram of a control domain configuration of a VMCS provided in an embodiment of the present invention;
FIG. 11 is a schematic diagram of a GUEST STATE AREA region provided in an embodiment of the present invention;
fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
Further advantages and effects of the present invention will become readily apparent to those skilled in the art from the disclosure herein, by referring to the accompanying drawings and the preferred embodiments. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be understood that the preferred embodiments are presented by way of illustration only and not by way of limitation.
Referring to fig. 1, a schematic diagram of an interrupt generation method of a conventional Peripheral device in an Arm architecture according to an embodiment of the present invention is shown, where the Peripheral device (Peripheral) is connected to an interrupt controller (interrupt controller) through an interrupt connection line, and the Peripheral device triggers an interrupt by sending an interrupt signal to the interrupt controller. Where IRQ is Interrupt Request, i.e., interrupt request, FIQ is Fast Interrupt Request, i.e., fast interrupt request, privileged execution (PRIVILEGED EXECUTION, PE) may be used to execute IRQ and FIQ privileges.
Referring to fig. 2, a schematic diagram of a method for generating interrupts for a new peripheral device in an Arm architecture according to an embodiment of the present invention is shown, where the peripheral device transmits the interrupts by means of a message (sending an interrupt message (interrupt message)), and the message is transmitted to a bus.
The improvement point of the new scheme is that virtual interrupt generated by the virtual device is transmitted to the interrupt controller in a physical interrupt mode, but in order to achieve the purpose, a hardware device is newly added, the device converts interrupt information of the virtual timer (vTimer) into a physical interrupt signal and then sends the physical interrupt signal to the interrupt controller through a message mechanism, and the interrupt controller sends the interrupt signal to the vCPU (Virtual Central Processing Unit ) to realize interrupt, and the scheme has the following defects that: firstly, new hardware equipment needs to be added, and the virtualization cost is increased; second, the running mechanism of the interrupt virtualization itself is not changed, different virtual machines run virtual interrupts at the same time, the interrupt processing program still can only be executed in series, and the implementation of the hardware virtual mechanism restricts the performance of the interrupt virtualization.
Referring to fig. 3, a schematic diagram of an x86 hardware interrupt processing procedure according to an embodiment of the present invention is provided, where the specific procedure includes:
1) The CPU executes a certain instruction; 2) Generating an interrupt signal in the CPU when the interrupt occurs; 3) Judging the interrupt source in the CPU to generate an interrupt type code N; 4) Current CS/IP/PSW push; 5) Clearing IF and TF; 6) Taking a CS/IP new value (through IDT); 7) Turning to an interrupt service routine; 8) Opening an interrupt; 9) IRET instructions cause the old CS/IP/PSW to pop off the stack; 10 Returns to the interrupted program. Wherein, the CPU comprises CS: a code segment register; IP: instruction Pointer, instruction pointer, IP, also called EIP; FLAGS: a flag register, wherein the flag register includes a Carry Flag (CF), a Zero Flag (ZF), a Sign Flag (SF), an Interrupt Flag (IF), a debug flag (TF), and the like. PSW is Program Status Word, program status word. IRET instructions are instructions returned from an exception handler or Interrupt Service Routine (ISR).
In practice, the interrupt processing flow implemented by the physical device specifically includes: 1. and (5) closing interruption: the CPU closes the interrupt response, namely, no other external interrupt requests are received; 2. saving break points: the instruction address of the interrupt is pushed onto the stack, so that the interrupt can be correctly returned after being processed; 3. identifying an interrupt source: the CPU identifies the source of the interrupt, determines the interrupt type number, and finds the entry address of the corresponding interrupt service routine through an interrupt descriptor table (IDT, interrupt Descriptor Table); 4. and (3) protecting the site: pushing the contents of a Guan Jicun (register to be used in the interrupt service routine) and a flag register to the stack at the place where the interrupt occurs; 5. executing an interrupt service routine: turning to the entry address of the interrupt service routine to begin execution, the interrupt may be reopened at an appropriate time to allow a correspondingly higher priority external interrupt; 6. resume the scene and return: the information pushed onto the stack when the field is protected is bounced back to the original register, and then an execution interrupt return instruction is returned, so that the main program is returned to continue running;
The storage address of the interrupt service routine is located in IDT (interrupt descriptor table), and the corresponding ISR (Interrupt Service Routine ) is found out by interrupting the interrupt vector number (interrupt type number) transmitted to the CPU, where IDT is globally unique, all CPUs share one IDT, after receiving the interrupt, the multi-core CPU will query the IDT for the corresponding ISR (interrupt service routine), because the interrupt service routine of the whole X86 hardware is shared by all kernel programs running on the CPU, and the processing mode of the same interrupt is the same.
The conventional hardware-assisted virtualization implementation is implemented by interrupt injection, although the performance is higher than that of the pure software implementation, but there is still a performance bottleneck, and by taking the example of X86 interrupt injection virtualization, referring to fig. 4, an implementation schematic diagram of an X86 hardware-assisted virtualization technology provided in an embodiment of the present invention includes the following specific procedures:
The first step: the virtual interrupt controller returns the virtual machine from a Guest mode (virtual machine mode) to a host mode (VMM virtual machine monitor mode) through Inter-core interrupt (IPI, inter-Processor Interrupt), and the virtual machine enters a Hypervisor mode at the moment;
and a second step of: writing vmcs (virtual machine control structure area, virtual Machine Control Structure Region) interrupt vector information, mainly interrupt vector table vector information;
And a third step of: starting a virtual machine through vmresume or vmlaunch instructions; wherein vmresume or vmlaunch are instructions for virtualization technology in the x86 architecture, used by a virtual machine monitor (Hypervisor) or virtual machine manager (VMM, virtual Machine Monitor) for startup and management.
The above is the injection process of virtual interrupt, and the factors affecting the performance of the virtual machine are as follows: 1. firstly, the virtual machine is to be exited because of virtual interrupt; 2. the implementation of virtual interrupt injection requires writing interrupt vector related information into the memory area interruption field pointed by the VMCS register; 3. then, the interrupt injection can be executed only when the virtual machine runs next time by scheduling the process of the operating system, and the interrupt injection is executed by firstly restoring the content of the GUEST STATE AREA (client state area) area in the VMCS to a physical CPU register, wherein the content is related to an interrupt and is an IDTR (Interrupt Descriptor Table Register ) register, then an interrupt service routine is found by the IDTR and the vector, and the corresponding interrupt service routine is executed to execute interrupt processing.
In summary, in the above interrupt virtualization, a problem that has a serious impact on performance is that (the virtual machine interrupt serialization, that is, the virtual machine can only perform interrupt processing sequentially), for example, referring to fig. 5, an implementation schematic diagram of the current interrupt virtualization of multiple virtual machines is shown, where the IDTR register (physical CPU-IDTR) is a global register, which is equivalent to that only one virtual machine (vCPU-IDTR) or host machine occupies each time, that is, when one virtual machine uses the IDTR register, the rest virtual machines or host machines can only wait for the next operation, especially if the host machine frequently has interrupt generation, which may cause the virtual machine to need to frequently exit, and the virtual machine needs to frequently wait for the operation of the interrupt service routine, which affects the performance of the virtual machine. Since the IDTR register is a physical global register of the CPU, when a plurality of virtual machines trigger interrupt processing, only one virtual machine in the multi-CPU core can perform interrupt processing, and the parallel is converted into serial, even if different virtual machines run on different CPU cores, that is, a plurality of virtual interrupts of the plurality of virtual machines occur simultaneously, the virtual interrupts also occur sequentially.
In view of the above problems, an embodiment of the present invention provides an interrupt virtualization processing method for multiple virtual machines, where a shadow register of an IDTR is set for a CPU (vCPU) of each virtual machine of a physical device, that is, a set of IDTR registers is set on the physical device, so that even if interrupts of multiple virtual machines occur simultaneously, virtual interrupts can be executed simultaneously, concurrency is guaranteed, and performance is improved.
Referring to fig. 6, a step flow chart of an interrupt virtualization processing method provided in an embodiment of the present invention is applied to a physical device, where the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and the virtual machines respectively have corresponding virtual machine identifiers, and specifically includes the following steps:
And 601, writing a target virtual machine identification and current state information of a target virtual machine entering interrupt processing into the virtual machine control structure.
In an embodiment of the present invention, referring to fig. 7, a schematic diagram of implementing parallel interrupt virtualization of multiple virtual machines in an embodiment of the present invention is provided, where a physical device (host machine) may include multiple virtual machines, each virtual machine has a corresponding vCPU (processor) thereof, a physically existing Shadow register (IDTR Shadow) is set for the vCPU of each virtual machine, and each virtual machine or vCPU has a corresponding virtual machine identifier (CPUID), and the corresponding virtual machine in the physical device may be uniquely found based on the virtual machine identifier. Specifically, the shadow register is IDTR (Interrupt Descriptor Table Register ), a special register in the x86 architecture, for storing the base address and the boundary of the interrupt descriptor table (Interrupt Descriptor Table, IDT), wherein the interrupt descriptor table is a key data structure, is a key component of the operating system kernel for managing interrupts and exception handling, and can be used for storing the entry address of the interrupt service routine (Interrupt Service Routine, ISR), and when the virtual machine touches the interrupt process through the virtual machine monitor, the IDT is used for searching the corresponding entry address to jump to the corresponding interrupt service routine of the line. Therefore, the shadow register in the embodiment of the invention is a set of IDTR registers and corresponds to each virtual machine respectively, so that even if interrupt processing of a plurality of virtual machines occurs simultaneously, the interrupt processing of the virtual machines can be ensured to be executed simultaneously, concurrency is ensured, and performance is improved.
Alternatively, the virtual machine monitor may be a Type2-Hypervisor (second-Type virtual machine monitor), which is a Type of virtualization software running on top of the operating system, unlike Type 1Hypervisor (first-Type virtual machine monitor), which does not run directly on the hardware of the physical device, but rather runs as an application on the operating system of the physical device.
The virtual machine has a VMCS (Virtual Machine Control Structure ), a critical data structure in the x86 architecture, for storing and managing state information of the virtual machine. The VMCS is a mechanism by which the virtual machine monitor controls virtual machine execution, allowing the virtual machine monitor to switch efficiently between virtual machines and hosts while maintaining state isolation and integrity of the virtual machines. Wherein the VMCS contains a plurality of domains (regions), referring to fig. 8, the following regions may be specifically included: CONTROL FIELDS: the virtual machine comprises a plurality of control fields for configuring the execution behaviors of the virtual machine, such as virtual interrupt control, virtual machine exit control and the like; wherein the CONTROL field includes VM-EXIT CONTROL FIELDS (virtual machine exit CONTROL field) and VM-EXIT INFORMATION FIELDS (virtual machine exit information field), wherein VM-EXIT CONTROL FIELDS is used for controlling the behavior of virtual machine exit, and VM-EXIT INFORMATION FIELDS is used for storing related information when the virtual machine exits. Of course, the VMCS may also include the following regions: GUEST STATE AREA area (customer status area): state information of the virtual machine (Guest) at the time of execution is stored, and the state information may include information such as a general register, a segment register, a flag register, an instruction pointer, and a stack pointer, and based on the state information, the state information may be restored to a state before interrupt processing. When the virtual machine exits to the virtual machine monitor state, the current state information of the virtual machine is saved in the VMCS; VM Entry Controls (virtual machine entry control domain): settings to control the virtual machine entry are included, such as whether virtual interrupts are enabled, whether specific instruction execution is allowed, etc. The VMCS operates through a series of instructions that allow the virtual machine monitor to read and write data in the VMCS, so that execution of the virtual machine can be controlled based on the data in the VMCS (e.g., state information of the virtual machine).
In one embodiment of the present invention, the writing, in the step 601, the target virtual machine identifier and the current state information of the target virtual machine entering the interrupt processing into the virtual machine control structure includes:
When the virtual machine monitor triggers a target virtual machine to perform interrupt processing, the current state information of the target virtual machine is controlled to be written into a virtual machine control structure of the target virtual machine before the target virtual machine exits, and a target virtual machine identifier of the target virtual machine is controlled to be written into the virtual machine control structure.
In the embodiment of the invention, when one or more virtual machines are triggered by a Virtual Machine Monitor (VMM) to perform interrupt processing, the virtual machine entering the interrupt processing is taken as a target virtual machine, the current state information of each target virtual machine is controlled to be written into the VMCS of the target virtual machine before exiting, and meanwhile, the target virtual machine identification (CPUID) of the target virtual machine is written into the VMCS of the target virtual machine.
Step 602, when the target virtual machine is controlled to be started, writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier.
In the embodiment of the invention, after the control target virtual machine starts, for example, after the corresponding interrupt service routine completes interrupt processing, the target virtual machine identifier (CPUID) stored before the target virtual machine exits can be obtained from the VMCS of the target virtual machine, and in addition, the current state information of the VMCS of the target virtual machine is written into the target shadow register corresponding to the target virtual machine identifier (CPUID).
And 603, controlling the target virtual machine to read the current state information of the target virtual machine from the target shadow register, so that the target virtual machine resumes the state before interrupt processing according to the current state information.
In the embodiment of the present invention, according to the foregoing, when the target shadow register of the target virtual machine has already saved the current state information of the target virtual machine read from the VMCS, the target virtual machine may be controlled to read the current state information of the target virtual machine from the target shadow register, and then the state before interrupt processing may be restored based on the current state information.
The embodiment of the invention is applied to physical equipment, the physical equipment comprises a virtual machine monitor, each virtual machine of the physical equipment is provided with a shadow register, each virtual machine is provided with a corresponding virtual machine identifier, when one or more virtual machines trigger interrupt processing, the virtual machine entering the interrupt processing is used as a target virtual machine, and the current state information of the target virtual machine and the target virtual machine identifier are written into a virtual machine control structure; when the control target virtual machine is started, the current state information of the virtual machine control structure of the target virtual machine is written into a target shadow register corresponding to the target virtual machine identification, and the control target virtual machine reads the current state information of the target virtual machine from the target shadow register so that the target virtual machine is restored to the state before interrupt processing according to the current state information. According to the embodiment of the invention, the physical shadow registers are respectively configured for the processor of each virtual machine of the physical equipment, and when one or more virtual machines enter interrupt processing, the state before interrupt processing can be restored in parallel through the corresponding shadow registers, so that the concurrency processing capacity of the physical equipment is improved, and the influence of interrupt processing on the performance of the virtual machines of the physical equipment is reduced.
In one embodiment of the present invention, when the virtual machine monitor triggers a target virtual machine to perform interrupt processing, the method includes controlling the target virtual machine to write current state information of the target virtual machine into a virtual machine control structure of the target virtual machine before exiting, and writing a target virtual machine identifier of the target virtual machine into the virtual machine control structure, including:
In the process of executing the virtual machine, if the target virtual machine receives an interrupt signal sent by the virtual machine monitor, triggering the target virtual machine to switch from a virtual machine mode to a virtual machine monitor mode;
Before the target virtual machine is controlled to exit, the current state information of the target virtual machine is stored in a virtual machine control structure, and the target virtual machine identification is written in the virtual machine control structure.
In the embodiment of the present invention, if one or more virtual machines (i.e., target virtual machines) receive an interrupt signal sent by a Virtual Machine Monitor (VMM) during execution of the virtual machines in a physical device, the target virtual machine is triggered to switch from a virtual machine mode (Guset mode) to a virtual machine monitor mode (kernel mode), where before the target virtual machine is controlled to exit, current state information of the target virtual machine may be saved in the VMCS, and a target virtual machine identifier (CPUID) of the target virtual machine is written in the VMCS.
In the above example, the current state information (i.e., the information of the register, the segment register, the flag register, the instruction pointer, the stack pointer, etc.) of the target virtual machine is saved in the VMCS before the target virtual machine exits, so that when the virtual machine is restored to be executed again, the state of the target virtual machine can be restored from using the VMCS and the shadow register, so that the virtual machine can seamlessly continue the previous execution flow, and the stability of the virtualized environment is improved.
In one embodiment of the present invention, the storing the current state information of the target virtual machine in a virtual machine control structure, and writing the target virtual machine identifier into the virtual machine control structure, includes:
Storing the current state information of the target virtual machine into a client state area of a virtual machine control structure, and writing the target virtual machine identification into an interrupt information field register of the virtual machine control structure.
Specifically, in an embodiment of the present invention, the current state information of the target virtual machine is saved into the GUEST STATE AREA area of the VMCS, and the CPUID of the target virtual machine is written to interruption-information field (interrupt information field register) of the VMCS VM-Entry.
In one embodiment of the present invention, the method may further include:
and configuring the virtual machine control structure of the virtual machine.
In a specific implementation, the VMCS of the virtual machine may not perform processes in the embodiment of the present invention, such as storing the CPUID, writing the current state information obtained by the virtual machine into the shadow register, etc., so the embodiment of the present invention may configure the VMCS of the virtual machine before the virtual machine performs the interrupt processing, so that it may implement the logic of executing the interrupt processing in parallel by multiple virtual machines in the embodiment of the present invention. It can be appreciated that embodiments of the present invention do not require excessive development costs since only the VMCS of the virtual machine needs to be configured.
In one embodiment of the present invention, the configuring the virtual machine control structure of the virtual machine includes:
And configuring a control domain of the virtual machine control structure of the virtual machine.
In an embodiment of the present invention, the virtual machine control structure configured with a virtual machine may include an interrupt control domain (control domain), and exemplary interrupt vector configuration contents of the interrupt control domain may include:
1) The control domain for the VMCS is first configured to operate on VMCS via VMREAD, VMWRITE instructions: specifically, referring to FIG. 9, the relevant domain of the VMCS is operated by the VMREAD, VMWRITE instruction, which configures the control domain of VMCS, so set to 0 at [11:10], and the corresponding processor of the server is 64 bits, so configure 1 at [14:13 ].
2) Configuring an interrupt vector number to be injected into the virtual machine: specifically, referring to FIG. 10, when interrupt injection is performed, the interrupt vector number that requires virtual machine execution is written to the 0-7bit, [10:8] bit of the interruption-information field register of the VMCS VM-Entry, designated as 1, representing an external interrupt.
Because of the existence of IDT (shadow page table/interrupt descriptor table) in the shadow register, the content of the GUEST STATE AREA area of the VMCS needs to be loaded into the shadow page table of the virtual machine (vCPU), which is equal to one IDT for each virtual machine, so that it is necessary to explicitly interrupt which vCPU corresponds, and thus the original register needs to be modified, and the modified form is as follows:
Wherein, position [30:26] corresponds to the CPUID of the logical CPU, and therefore, the IDTR register in GUEST STATE AREA corresponding to this VMCS is loaded into the IDTR shadow page table of the shadow register of the physical CPU corresponding to the CPUID.
In one embodiment of the present invention, the configuring the virtual machine control structure of the virtual machine includes:
The guest state area of the virtual machine control structure of the virtual machine is configured.
In an embodiment of the present invention, configuring the virtual machine control structure of the virtual machine may include configuring a GUEST state area, and for example, configuring content in a GUEST STATE AREA (GUEST state area) area in the VMCS may include:
Referring to fig. 11, a schematic diagram of a guist STATE AREA area provided in an embodiment of the present invention is configured by a vmwrite instruction to configure a guist STATE AREA area in the VMCS, such as registers cs (Code Segment, code Segment registers), ss (STACK SEGMENT, stack Segment registers), ds (DATA SEGMENT, data Segment registers), es (Extra Segment registers), and the like, which are not globally unique, where the registers may also include an IDTR register, which is a corresponding block memory address on the host, and the host memory address is used to fill the IDTR register address, and when the vmalunch instruction is executed, the contents of the registers stored in the guist STATE AREA in the VMCS memory address are filled into the registers corresponding to the physical CPU.
In one embodiment of the present invention, before controlling the target virtual machine to exit, the method further includes:
the target virtual machine identifies an interrupt source and determines an interrupt type number according to the interrupt source;
And inquiring an entry address of a corresponding interrupt service routine from an interrupt descriptor table of the shadow register according to the interrupt type number so as to jump to the interrupt service routine according to the entry address to perform interrupt processing.
In the embodiment of the present invention, when the target virtual machine receives the interrupt signal of the VMM, the target virtual machine first needs to identify an interrupt source, where the interrupt source may be an external device, a timer, a software exception, or the like, then based on the interrupt source, an interrupt type number (interrupt vector number) may be determined, where the interrupt type number is a unique identifier, and may be used to index an entry address of a corresponding Interrupt Service Routine (ISR) in an Interrupt Descriptor Table (IDT) of a corresponding shadow register, and then jump to the corresponding ISR to execute interrupt processing logic. In the embodiment, the target virtual machine can accurately process different interrupt sources by identifying the interrupt sources and determining the interrupt type number, so that the interrupt can be correspondingly processed.
In one embodiment of the present invention, the method may further include:
modifying a virtual machine starting instruction of the virtual machine; and when the modified virtual machine starting instruction is executed, reading a virtual machine identifier from a virtual machine control structure of the started virtual machine.
In a specific implementation, a virtual machine starting instruction (vmlaunch instruction) can only start the execution of the virtual machine, where a vmlaunch instruction may be sent to the virtual machine by a Virtual Machine Monitor (VMM) to control the execution flow of the virtual machine, and by modifying the vmlaunch instruction, in the embodiment of the present invention, when starting the virtual machine based on the vmlaunch instruction, the CPUID stored in the VMCS of the virtual machine may be written into the current state information stored in the VMCS in a write shadow register, so as to implement interrupt recovery of the virtual machine.
Specifically, the modified vmlauch instruction will perform the following operations:
1. The CPU switches from kernel mode to guest mode; 2. the [30:26] CPUID among interruption-information field (interrupt information field registers) of VMCS VM-Entry (virtual machine resume execution) is read by vmread instruction; 3. the contents in the GUEST STATE AREA in the VMCS are loaded into the corresponding register of the physical CPU, such as cs is loaded into the cs segment selection register of the physical CPU, ss is loaded into the stack selection register of the physical CPU, wherein the contents in the IDTR in the GUEST STATE AREA area of the VMCS are loaded into the shadow register of the physical CPU core mapped by the virtual machine according to the CPUID above, so that the interrupt processing of the multiple virtual machines can be realized based on the shadow register.
In one embodiment of the present invention, the reading, when controlling the target virtual machine to start, a target virtual machine identifier of the target virtual machine from the virtual machine control structure of the target virtual machine includes:
triggering the target virtual machine to switch from a virtual machine monitor mode to a virtual machine mode when the virtual machine starting instruction after the modification is executed controls the target virtual machine to start;
and reading a target virtual machine identification of the target virtual machine from the virtual machine control structure of the target virtual machine.
In the embodiment of the invention, when the vmlauch instruction for executing the transformation controls the virtual machine to start, the original vmlaunch instruction is caused to operate as follows: the CPU (virtual machine) switches from kernel mode to gust mode, reads the CPUID in the VMCS by vmread instruction, and then, according to the CPUID read from the VMCS, the embodiment of the present invention loads the content in the IDTR in the gust STATE AREA area of the VMCS into the shadow register corresponding to the physical CPU core CPUID mapped by the virtual machine.
In one embodiment of the present invention, the reading, from the virtual machine control structure of the target virtual machine, a target virtual machine identification of the target virtual machine includes:
And executing a virtual machine reading instruction to read a target virtual machine identification of the target virtual machine from an interrupt information field register of the virtual machine control structure of the target virtual machine.
Specifically, the CPU (virtual machine) switches from kernel mode to gust mode, reads the [30:26] CPUID among interruption-information field (interrupt information field registers) of VMCS VM-Entry (virtual machine resume execution) by vmread instruction.
In one embodiment of the present invention, after the writing of the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identification, the method further includes:
Writing other contents of the virtual machine control structure of the target virtual machine into corresponding other registers; the other content includes at least the content of the segment register.
In the embodiment of the present invention, other contents except for the current state information and the CPUID in the GUEST STATE AREA in the VMCS may be loaded into a corresponding register of the physical CPU, for example, cs is loaded into a cs segment selection register of the physical CPU, and ss is loaded into a stack selection register of the physical CPU.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will also appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required to practice the present invention
The embodiment of the invention also discloses an interrupt virtualization processing device which is applied to physical equipment, wherein the physical equipment comprises a virtual machine monitor, each virtual machine of the physical equipment is configured with a shadow register, each virtual machine is provided with a corresponding virtual machine identifier, and the device is used for executing the steps of the method embodiment.
The embodiment of the invention is applied to physical equipment, the physical equipment comprises a virtual machine monitor, each virtual machine of the physical equipment is provided with a shadow register, each virtual machine is provided with a corresponding virtual machine identifier, when the virtual machine monitor triggers the target virtual machine to interrupt, the current state information of the target virtual machine is written into a virtual machine control structure of the target virtual machine before the target virtual machine is controlled to exit, and the target virtual machine identifier of the target virtual machine is written into the virtual machine control structure; when a control target virtual machine is started, reading a target virtual machine identification of the target virtual machine from a virtual machine control structure of the target virtual machine; writing current state information of a virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identification; and the control target virtual machine reads the current state information of the target virtual machine from the target shadow register so as to enable the target virtual machine to recover to the state before interrupt processing according to the current state information. According to the embodiment of the invention, the physical shadow registers are respectively configured for the processors of each virtual machine of the physical equipment, so that when a plurality of virtual machines enter interrupt processing, the state before interrupt processing can be restored in parallel through the corresponding shadow registers, the concurrency processing capacity of the physical equipment is improved, and the influence of interrupt processing on the performance of the virtual machines of the physical equipment is reduced.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
The embodiment of the invention also provides an electronic device, as shown in FIG. 12, comprising a processor 801, a device interface 802, and a memory
803 And a bus 804;
A memory 803 for storing a computer program;
the processor 801, when executing the program stored in the memory 803, implements the following steps:
When the virtual machine monitor triggers a target virtual machine to perform interrupt processing, controlling the target virtual machine to write current state information of the target virtual machine into a virtual machine control structure of the target virtual machine before exiting, and writing a target virtual machine identifier and current state information of the target virtual machine entering interrupt processing into the virtual machine control structure;
when the target virtual machine is controlled to start, reading a target virtual machine identification of the target virtual machine from the virtual machine control structure of the target virtual machine;
writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier;
And controlling the target virtual machine to read the current state information of the target virtual machine from the target shadow register so as to enable the target virtual machine to recover the state before interrupt processing according to the current state information.
The bus mentioned by the above terminal may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, abbreviated as PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, abbreviated as EISA) bus, etc. The bus may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.
The memory may include random access memory (Random Access Memory, RAM) or may include non-volatile memory (non-volatile memory), such as at least one disk memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.
The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, abbreviated as CPU), a network processor (Network Processor, abbreviated as NP), etc.; but may also be a digital signal processor (DIGITAL SIGNAL Processing, DSP), application Specific Integrated Circuit (ASIC), field-Programmable gate array (FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components.
The present invention also provides a storage medium, which when executed by a processor of an electronic device, enables the electronic device to perform the interrupt virtualization processing method of the foregoing embodiment.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
The algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. The required structure for the construction of such devices is apparent from the description above. In addition, the present invention is not directed to any particular programming language. It will be appreciated that the teachings of the present invention described herein may be implemented in a variety of programming languages, and the above description of specific languages is provided for disclosure of enablement and best mode of the present invention.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some or all of the components in a sorting device according to the present invention may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present invention may also be implemented as an apparatus or device program for performing part or all of the methods described herein. Such a program embodying the present invention may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus, the apparatus and the units described above may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
It should be noted that, in the embodiment of the present application, the related processes of obtaining various data are all performed under the premise of conforming to the corresponding data protection rule policy of the country of the location and obtaining the authorization given by the owner of the corresponding device.
Claims (15)
1. An interrupt virtualization processing method, which is applied to a physical device, wherein the physical device comprises a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and the virtual machines respectively have corresponding virtual machine identifiers, and the method comprises:
Writing a target virtual machine identifier and current state information of a target virtual machine entering interrupt processing into the virtual machine control structure;
when the target virtual machine is controlled to start, writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier;
And controlling the target virtual machine to read the current state information of the target virtual machine from the target shadow register so as to enable the target virtual machine to recover the state before interrupt processing according to the current state information.
2. The method of claim 1, wherein writing the target virtual machine identification and current state information of the target virtual machine entering interrupt processing to the virtual machine control structure comprises:
When the virtual machine monitor triggers a target virtual machine to perform interrupt processing, the current state information of the target virtual machine is controlled to be written into a virtual machine control structure of the target virtual machine before the target virtual machine exits, and a target virtual machine identifier of the target virtual machine is controlled to be written into the virtual machine control structure.
3. The method according to claim 2, wherein controlling the writing of current state information of a target virtual machine into a virtual machine control structure of the target virtual machine before the target virtual machine exits and writing a target virtual machine identification of the target virtual machine into the virtual machine control structure when a target virtual machine is triggered by the virtual machine monitor for interrupt processing includes:
In the process of executing the virtual machine, if the target virtual machine receives an interrupt signal sent by the virtual machine monitor, triggering the target virtual machine to switch from a virtual machine mode to a virtual machine monitor mode;
Before the target virtual machine is controlled to exit, the current state information of the target virtual machine is stored in a virtual machine control structure, and a target virtual machine identification of the target virtual machine is written in the virtual machine control structure.
4. The method of claim 3, wherein the saving of the current state information of the target virtual machine into a virtual machine control structure and the writing of the target virtual machine identification of the target virtual machine into the virtual machine control structure comprises:
storing the current state information of the target virtual machine into a client state area of a virtual machine control structure, and writing a target virtual machine identification of the target virtual machine into an interrupt information field register of the virtual machine control structure.
5. The method according to claim 4, wherein the method further comprises:
and configuring the virtual machine control structure of the virtual machine.
6. The method of claim 5, wherein said configuring the virtual machine control structure of the virtual machine comprises:
configuring a control domain of the virtual machine control structure of the virtual machine;
The guest state area of the virtual machine control structure of the virtual machine is configured.
7. The method of claim 1, wherein prior to controlling the target virtual machine to exit, the method further comprises:
the target virtual machine identifies an interrupt source and determines an interrupt type number according to the interrupt source;
And inquiring an entry address of a corresponding interrupt service routine from an interrupt descriptor table of the shadow register according to the interrupt type number so as to jump to the interrupt service routine according to the entry address to perform interrupt processing.
8. The method according to claim 1, wherein the method further comprises:
modifying a virtual machine starting instruction of the virtual machine; and when the modified virtual machine starting instruction is executed, reading a virtual machine identifier from a virtual machine control structure of the started virtual machine.
9. The method of claim 8, wherein the reading the target virtual machine identification of the target virtual machine from the virtual machine control structure of the target virtual machine when controlling the target virtual machine to boot comprises:
triggering the target virtual machine to switch from a virtual machine monitor mode to a virtual machine mode when the virtual machine starting instruction after the modification is executed controls the target virtual machine to start;
and reading a target virtual machine identification of the target virtual machine from the virtual machine control structure of the target virtual machine.
10. The method of claim 9, wherein the reading the target virtual machine identification of the target virtual machine from the virtual machine control structure of the target virtual machine comprises:
And executing a virtual machine reading instruction to read a target virtual machine identification of the target virtual machine from an interrupt information field register of the virtual machine control structure of the target virtual machine.
11. The method of claim 1, wherein after the writing of the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identification, the method further comprises:
Writing other contents of the virtual machine control structure of the target virtual machine into corresponding other registers; the other content includes at least the content of the segment register.
12. The method of claim 1, wherein the target virtual machine is one or more and the shadow register is one or more.
13. Interrupt virtualization processing apparatus, applied to a physical device, where the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and each virtual machine has a corresponding virtual machine identifier, and the apparatus is configured to perform an interrupt virtualization processing method according to any one of claims 1 to 12.
14. An electronic device, comprising:
A processor;
A memory for storing processor-executable instructions;
wherein the processor is configured to execute the instructions to implement the interrupt virtualization processing method of any one of claims 1 to 12.
15. A computer readable storage medium, characterized in that instructions in said storage medium, when executed by a processor of a mobile terminal, enable the mobile terminal to perform the interrupt virtualization processing method according to any one of claims 1 to 12.
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