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CN1187881A - Interrogator for electronic identification system - Google Patents

Interrogator for electronic identification system Download PDF

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Publication number
CN1187881A
CN1187881A CN 96194798 CN96194798A CN1187881A CN 1187881 A CN1187881 A CN 1187881A CN 96194798 CN96194798 CN 96194798 CN 96194798 A CN96194798 A CN 96194798A CN 1187881 A CN1187881 A CN 1187881A
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CN
China
Prior art keywords
oscillator
interrogator
array
clock signal
lag line
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN 96194798
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Chinese (zh)
Inventor
J·斯彻伦
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British Technology Group Inter Corporate Licensing Ltd
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British Technology Group Inter Corporate Licensing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Priority to CN 96194798 priority Critical patent/CN1187881A/en
Publication of CN1187881A publication Critical patent/CN1187881A/en
Pending legal-status Critical Current

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Abstract

An interrogator (10) for use with a passive transponder (12) has a Colpitts oscillator (30, 32, 34, 36, 38) arranged to vary in frequency in accordance with the frequency of a signal from the transponder; a voltage controlled oscillator VCO 42 arranged to vary in frequency in accordance with the Colpitts frequency after a delay of a number of signal cycles, the delay being provided by a loop filter in a phase discriminator (40); and a digital filter (48) arranged to detect the phase difference between the Colpitts oscillator and the VCO. Preferably the digital filter has an input (48) comprising an array of flipflop circuits (52, 54, 56); a delay line (53, 55, 57) associated with each flipflop and providing a time delay which increases along the array, so that when first and second clock signals are provided to each flipflop-delay line pair, if the phase difference between the clock signals is less than the time delay of that delay line the flipflop provides a logical 0 and if the phase difference is greater than the time delay the flipflop provides a logical 1.

Description

The interrogator of electronic recognition system
The present invention relates to electronic recognition system, particularly comprise the system of an interrogator and one or more noncontact transponders.
We comprise the simple citation to an interrogator in the common pending application application No.9505350.0 that submits to March 16 nineteen ninety-five, that this interrogator comprises digital filter and can detect the little variation of the Q factor, and the application's invention can be applied in a kind of like this interrogator.
Interrogator and noncontact transponder are known and such system is disclosed among the open No.0585132 of european patent application of CSIR.In this application, transponder is discerned by the data-signal that utilizes the clock signal simultaneous extraction, but such interrogator can not detect the small frequency variations in having wide, smooth Q factor system.In the EP 0374018 of Etat Francais, what the smart card detection device combined a variable frequency examines Bei Zi (Colpitts) oscillator, and when this detecting device was coupled on the smart card, frequency change was sizable and depends on two electric capacity and an inductance.Such detecting device can not detect small frequency change.
According to the present invention, the interrogator that is used for electronic recognition system comprises and is arranged to first oscillator that makes changeable frequency according to the frequency of received signal; Be arranged to second oscillator that makes changeable frequency at some all after dates of signal that postpone to receive according to the frequency of first oscillator; And the device of the phase differential between detection first and second oscillators.
Described delay can utilize the loop filter in the phase demodulation apparatus to provide.
First oscillator can be sensitive to the variation of impedance and the variation that second oscillator then will be insensitive to impedance.First oscillator can be to be arranged to the unsettled shellfish oscillator of examining.Second oscillator can be a voltage controlled oscillator.
Preferably, interrogator also comprises the phase change pick-up unit such as digital filter, and this device can also Measurement Phase change the frequency that takes place, and such frequency measurement is indicated modulating frequency and therefore indicated the transponder identification signal of noncontact transponder.
Preferably, the input end of digital filter comprises: a multi-resonant oscillating circuit array; A lag line that links to each other with the multi-resonant oscillating circuit array, and so arrange, that is, make by increasing with incremental manner along this multi-resonant oscillating circuit array the time delay that each lag line provided; Provide signal with being used for from examining the shellfish oscillator and second oscillator as first and second clock signals, provide described clock signal to the right device of each multi-resonant oscillating circuit/lag line with being used to, make that working as the clock phase difference between signals provides the output of first logic corresponding to a multi-resonant oscillating circuit that links to each other less than the time by the time delay that lag line provided, with when the described time greater than by time delay that lag line provided the time, this multi-resonant oscillating circuit that links to each other provides the output of second logic.
Preferably, one second multi-resonant oscillating circuit array and the opposite lag line that is connected with first array also are provided, if make the leading second clock signal of first clock signal, then the output of the logic of first array changes, if with the first clock signal hysteresis second clock signal, then the output of the logic of second array changes.
Only present invention is described in the mode of example referring now to accompanying drawing, wherein:
Fig. 1 is from a kind of electronic identification circuit of principle expression;
Fig. 2 represents the part block scheme according to interrogator formation of the present invention;
Fig. 3 (a) and (b) electric current of antenna of expression interrogator and the variation of voltage;
Fig. 4 (a) and the voltage and the frequency output of (b) representing to examine shellfish oscillator respectively, and the error signal of Fig. 4 (c) expression generation;
Fig. 5 represents the operation of phase discriminator; With
Fig. 6 represents to be provided to a kind of arrangement of novelty of the input of digital filter.
In Fig. 1, electronic identification circuit comprises interrogator 10 and passive balise 12.Interrogator is represented as 14, and amplitude modulation, frequency modulation or the phase modulation identification signal 16 of hundreds of MHz are replied in this way for example to utilize this power use-case by known technology for transponder and transponder with 150 to 256KHz frequency delivering power.For example, transponder changes the frequency of signal by total Q factor of change system.
Please disclose a kind of transponder with data transmitting antenna among the No.9505350.0 in the common pending application of submitting to our March 16 nineteen ninety-five, this transponder is modulated by the coil that reduces it, makes the Q factor of interrogator-transponder system change.The structure of antenna is to arrange like this, makes the Q factor wide and smooth, thereby utilizes known technology can not realize the detection of small frequency variations.
Fig. 2 represents a kind of interrogator that can detect small frequency variations under such environment.The primary coil of the antenna 34 of interrogator 10 is connected to the phase inverter be made up of two mosfet transistors 30,32 and the two ends of coil 34 are connected to one of two electric capacity 36,38 respectively.
Each value that constitutes the circuit of examining shellfish oscillator is so selected, and promptly is different from conventional design concept, and oscillator is unsettled.This phase inverter has big driving force and therefore has big energy transmission.
Fig. 3 (a) and (b) be respectively the curve of the initial state of this circuit at the voltage at the two ends of primary coil 34 and the electric current that passes through, reaching a steady state (SS) and electric current rapidly may be up to ± 50mA.
In Fig. 2, be represented as V 3The output terminal of oscillator be connected to phase detector and loop filter 40, the output terminal of phase detector and loop filter is connected to the input circuit 46 of voltage controlled oscillator (VCO) 42 and digital filter 48.VCO42 provides voltage divider 44 and input circuit 46.Digital filter 48 is connected to data extract and passive balise identification circuit 49.
Usually VCO42 comprises electric capacity and electric current injector, does not have coil, and is insensitive to the frequency change of the signal that receives by antenna 34.The frequency that VCO produces is to examine the V that shellfish oscillator produces 38 times of signal frequency and this frequency of frequency divider 44 8 frequency divisions are so that as label V 5Shown in be provided to phase detector 40.Its reason is that digital filter 48 is for each 8 time clock of time clock requirement that receive from examining shellfish oscillator.
When work, an error signal presented by phase detector 40 and VCO42 operates this error of counteracting, locks the VCO frequency on the frequency of examining shellfish oscillator.
Suppose now, the transponder 12 modulated Q factors with the change system, the frequency of examining shellfish oscillator has a spot of change, and this frequency change is measured by error signal.
Modulation is by closure and the switch of opening in the transponder 12, its a part of data transmission line circle of short circuit takes place, this effect is indicated on Fig. 4 (a), the figure shows the voltage at the coil two ends of antenna 34, when switch was closed, though the absolute signal amplitude changes, P-to-P voltage did not change, this shows opposite with the interrogator circuitry of prior art, the absorption of the interrogator detected energy of prior art and the sizable variation that therefore stands peak-to-peak signal.Express the closure of a switch and the effect of opening, the i.e. data bit of a transponder among the figure.
In fact the output that shellfish oscillator is examined in Fig. 4 (b) expression have little frequency change on frequency, be not easy to find out on this figure, but shown to come out that this figure demonstrates output signal (that is V, of phase detector 44 at Fig. 4 (c) 3-V 5) also be VCO42 and input circuit 46 input signals.
Fig. 5 schematically shows the operation of phase detector 40.Show from examining the V of shellfish oscillator input 3, from the V of frequency divider 44 inputs 5And the output V of phase detector 40 3-V 5Over time.These two signals drift about out lentamente.For the sake of clarity, each numerical value is to interrelate with a very large aerial coil in transponder, but such coil will can not be used in the side circuit.
If error correction circuit can promptly be worked, then represented drift is held and will can not occurred, and VCO will promptly follow the signal of examining shellfish oscillator and not have to postpone or corresponding phase change can be not measured.In the existence of phase detector 40 intermediate ring road wave filters this process that slows down, make only just to apply correction, thereby can detect error and detect the variation of the frequency of examining shellfish oscillator thus at several all after dates.
Referring now to Fig. 6, the figure shows and receive two clock signal V 3, V 5So that present input circuit 46 to digital filter 48.The function of this circuit is that meter is shown in the signal V among Fig. 5 3And V 5Rising edge between time and present to digital filter 48.
The figure shows out several multivibrator circuits and each lag line of being arranged among two rows, be sure of, the sort circuit that can be called as clock row's circuit (clock bank circut) all is novel in any application.
Three identical multivibrator circuits 52,54,56 are drawn together in first package, and each and lag line 53,55,57 are in parallel.The input end of clock of each multivibrator and lag line each all provide self-study examination shellfish oscillator (Fig. 2) online 58 on clock signal and the output terminal of multivibrator be connected to digital filter 48.
Second row, promptly first row's mirror image comprises three multivibrator circuits 62,64,66 and lag line 53,65,67, they provide the clock signal from VCO 42 (Fig. 2) on online 68.Each lag line is cross connected to corresponding multivibrator on an other row.
Though in fact three multivibrators of expression and lag line, can be provided with very large number on every row, for example 100 or 200 multivibrators and lag line are so that provide desired precision.
Lag line is arranged like this, and during feasible in the drawings each arranged up and down, every lag line provided with former lag line and differs for example delay of 1ps of a unit, expressed the accumulated delay of P1,2,3ps among the figure.
A row above at first considering is at each clock signal V 3Rising edge, examine the Q end that shellfish period of the day from 11 p.m. to 1 a.m clock signal is written into each multivibrator.If the VCO clock signal drops on by each continuous lag line than examining slow one of shellfish period of the day from 11 p.m. to 1 a.m clock, such as the time between each time delay that lag line 55 and 57 provides, then multivibrator 54 will provide output 1 and multivibrator 56 that an output 0 will be provided; In bigger array, " downstream " multivibrator 54 will all export 1 and " upstream " multivibrator 56 all will export 0.
If the VCO clock signal faster than examining shellfish period of the day from 11 p.m. to 1 a.m clock signal, then following one is arranged multivibrator and lag line indication lag time.Coming of not operation provides indeclinable logic output under each situation.
The output terminal of all multivibrator circuits in two rows all is connected to digital filter 48, this can design by known principle such as 32 floating number wave filters of IEEE, and the time delay between its each clock signal of output expression, therefore should utilize time delay the error signal that produces from their phase differential to be carried out measurement.
In sending the noncontact interrogator of identification signal, the modulation that is illustrated in Fig. 4 (a) causes the increase of the frequency of examining shellfish oscillator along with the open and close of transponder switch and reduces.This system detects the frequency that variation occurs, and this frequency change is the feature modulating frequency of a specific transponder.
Aforesaid interrogator circuitry is rapidly and can be operated on the 14MHz clock that conventional A/D transducer can not be operated on such speed in work.
Advantage according to circuit of the present invention is the characteristic that depends on loop filter, and the VCO correction signal can be very large amount, perhaps on energy or in time.The best input to digital signal processing unit can utilize the loop filter of appropriate characteristics to present.

Claims (12)

1. an interrogator that is used for electronic recognition system is characterized in that, comprises being arranged to first oscillator (30,32,34,36,38) that makes frequency change according to the frequency of received signal.
Be arranged to second oscillator (42) that behind some cycle delays of received signal, makes frequency change according to the frequency of first oscillator; With
Detect the device (40) of the phase differential between first and second oscillators.
2. according to the interrogator of claim 1, it is characterized in that, also be included in the loop filter in the phase detector (40), in order to described delay to be provided.
3. according to the interrogator of claim 1, it is characterized in that first oscillator (30,32,34,36,38) is sensitive to the variation of impedance and the variation that second oscillator (42) is insensitive to impedance.
4. according to the interrogator of claim 3, it is characterized in that first oscillator (30,32,34,36,38) is to be designed to unsettledly examine shellfish oscillator and second oscillator (42) is a voltage controlled oscillator.
5. according to the interrogator of claim 4, it is characterized in that, also comprise the phase change pick-up unit (48) that is designed to determine in the frequency that phase change occurs, therefore can determine the modulating frequency of described received signal.
6. according to the interrogator of claim 5, it is characterized in that, also comprise the device (49) of a passive balise identity of identification from described modulating frequency.
7. according to the interrogator of claim 5, it is characterized in that the phase change pick-up unit comprises digital filter (48).
8. according to the interrogator of claim 7, it is characterized in that comprising,
The input end of described digital filter (48) that comprises the multivibrator circuit (52,54,56) of an array;
Link to each other with each multivibrator circuit and be arranged to the lag line (53,55,57) that incrementally increases along this array time delay of providing by each lag line is provided;
Be used for from examining shellfish oscillator and second oscillator provides signal V 3, V 5As first and second clock signals and be used to provide described clock signal to each multivibrator-lag line right, with the phase differential of box lunch between each clock signal corresponding to less than time delay of providing by lag line the time, the multivibrator circuit that should link to each other provides the output of first logic, with when described time during greater than time delay of providing by lag line, continuous multivibrator circuit provides the device (40,58,68) of second logic output.
9. according to the interrogator of claim 8, it is characterized in that, second array multivibrator circuit (62,64,66) and the opposite lag line that is connected with first array (63,65,67) also are provided, if make that first clock signal is ahead of the second clock signal, if then the logic of first array output change and first clock signal lag behind the second clock signal, then the output of the logic of second array changes.
10. the input end of a digital filter (48) is characterized in that comprising,
The multivibrator circuit of an array (52,54,56);
Link to each other with each multivibrator circuit and be arranged to and make each lag line provide to increase progressively the lag line (53,55,57) that increases time delay along this array; With
Be used to provide first and second clock signals to the right device (58,68) of each multivibrator-lag line, with the phase differential of box lunch between each clock signal corresponding to one during less than time delay of providing by a lag line, the multivibrator circuit that links to each other provides the output of first logic, with when described time during greater than time delay of providing by lag line, continuous multivibrator circuit provides the output of second logic.
11. input end according to the digital filter of claim 10, it is characterized in that, second array multivibrator circuit (62,64,66) and the opposite lag line that is connected with first array (63,65,67) also are provided, if so that the leading second clock signal of first clock signal, if then the output of the logic of first array changes and the first clock signal hysteresis second clock signal, then the output of the logic of second array changes.
12. input end according to the digital filter of claim 11, it is characterized in that, also comprise being arranged to from each multivibrator circuit (52,54,56,62,64,66) received signal and the digital filter (48) of the signal that is relevant to the phase differential between first and second clock signals being provided.
CN 96194798 1995-04-27 1996-04-26 Interrogator for electronic identification system Pending CN1187881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 96194798 CN1187881A (en) 1995-04-27 1996-04-26 Interrogator for electronic identification system

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9508600.5 1995-04-27
GB9511085.4 1995-06-01
CN 96194798 CN1187881A (en) 1995-04-27 1996-04-26 Interrogator for electronic identification system

Publications (1)

Publication Number Publication Date
CN1187881A true CN1187881A (en) 1998-07-15

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Application Number Title Priority Date Filing Date
CN 96194798 Pending CN1187881A (en) 1995-04-27 1996-04-26 Interrogator for electronic identification system

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100424992C (en) * 2001-11-02 2008-10-08 摩托罗拉公司 Cascaded delay locked loop circuit
CN100545674C (en) * 2004-12-30 2009-09-30 塔格马斯特股份公司 The definite response device is with respect to the method for the position of communicator
CN118508953A (en) * 2024-02-07 2024-08-16 上海谭慕半导体科技有限公司 Delay locked loop, control method thereof and readable storage medium

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100424992C (en) * 2001-11-02 2008-10-08 摩托罗拉公司 Cascaded delay locked loop circuit
CN100545674C (en) * 2004-12-30 2009-09-30 塔格马斯特股份公司 The definite response device is with respect to the method for the position of communicator
CN118508953A (en) * 2024-02-07 2024-08-16 上海谭慕半导体科技有限公司 Delay locked loop, control method thereof and readable storage medium

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