CN118760647A - Function expansion device, system on chip, method and product - Google Patents

Abstract

The embodiment of the present application provides a function expansion device, a system on chip, a method and a product, wherein the function expansion device is applied to a system on chip including a control unit, and the function expansion device includes a protocol conversion module, an inter-chip transmission bus and an off-chip function expansion component, wherein the off-chip function expansion component includes an expansion function module; the host of the protocol conversion module is used to obtain the target operation instruction for the expansion function module issued by the control unit on the on-chip bus of the system on chip, and send it to the off-chip function expansion component through the inter-chip transmission bus; the off-chip function expansion component includes a slave of the protocol conversion module, and the slave of the protocol conversion module is used to receive the target operation instruction and send it to the expansion function module of the off-chip function expansion component; the expansion function module is used to execute the target operation after responding to the target operation instruction. The embodiment of the present application aims to improve the efficiency of the functional fault recovery and new function expansion process of the SOC system.

Description

Function expansion device, system on chip, method and product

Technical Field

Embodiments of the present application relate to the technical field of system on chip, and more specifically, to a function expansion device, system on chip, method and product.

Background Art

With the development of integrated circuit technology, more and more functions are integrated in SOC systems (System-on-a-Chip). The realization of various functions depends on various functional IP (Intellectual Property, also known as IP core) modules in the SOC system. These functional modules are generally controlled by the CPU (Central Processing Unit). The communication between the CPU and various functional modules is realized through the on-chip bus.

However, with the increasing number of functional modules, numerous IP modules have brought about a series of uncertainty problems. For example, when an IP module has a design error and cannot be used, the SOC system no longer has the functions provided by the IP module. In addition, for functional modules that are not only mounted on the on-chip bus but also have a large amount of data interaction with other functional modules, if a fault occurs, it is not easy to find a solution to the fault, and the only solution is to re-modify the SOC system and tape out the chip. Moreover, the application environment of the SOC system changes with the development of demand. When it is necessary to support new interfaces or add new IP module functions, the entire SOC system needs to be redesigned, that is, the new function can be upgraded only by re-taping the chip, which results in low efficiency in the functional fault recovery and new function expansion process of the SOC system.

Summary of the invention

The embodiments of the present application provide a function expansion device, a system on chip, a method and a product, which are intended to improve the efficiency of the function failure recovery and new function expansion process of the SOC system.

In a first aspect, an embodiment of the present application provides a function expansion device, which is applied to a system on chip, wherein the system on chip includes a control unit; the function expansion device includes a protocol conversion module, an inter-chip transmission bus and an off-chip function expansion component, wherein the off-chip function expansion component includes an expansion function module;

The host of the protocol conversion module is arranged in the system on chip, and the host of the protocol conversion module is used to obtain the target operation instruction for the extended function module issued by the control unit on the on-chip bus of the system on chip, and send it to the off-chip function extension component through the inter-chip transmission bus;

The off-chip function expansion component includes a slave of the protocol conversion module, and the slave of the protocol conversion module is used to receive the target operation instruction and send it to the expansion function module of the off-chip function expansion component;

The extended function module is used to execute the target operation after responding to the target operation instruction.

Optionally, the inter-chip transmission bus includes:

A clock line, the direction of the clock line is from the host of the protocol conversion module to the slave of the protocol conversion module, and the slave of the protocol conversion module is used to sample and send data according to the clock line;

Two data transmission lines, the direction of the data transmission lines is from the host of the protocol conversion module to the slave of the protocol conversion module;

Two receiving data lines, the direction of the receiving data lines is from the slave of the protocol conversion module to the host of the protocol conversion module.

Optionally, the two transmitting data lines and the two receiving data lines both adopt a double-edge transmission mode.

Optionally, the target operation instruction includes a write operation instruction, and the host of the protocol conversion module includes:

An on-chip bus protocol parsing unit, used to parse the write operation instruction through the on-chip bus, obtain the write address and write data corresponding to the write operation instruction, and send them to the sending data buffer unit;

A sending data buffer unit, used for buffering the write address and write data corresponding to the write operation instruction;

A protocol state machine unit, used for encapsulating the write address and write data corresponding to the write operation instruction into the sending frame data corresponding to the write operation instruction;

The serializer unit is used to send the sending frame data corresponding to the write operation instruction encapsulated by the protocol state machine unit to the slave of the protocol conversion module through the inter-chip transmission bus.

Optionally, the host of the protocol conversion module of the system on chip further includes:

The first verification unit is used to generate a verification value of a write address and write data corresponding to the write operation instruction.

Optionally, the target operation instruction includes a read operation instruction.

The on-chip bus protocol parsing unit is used to obtain the read operation instruction through the on-chip bus, and parse to obtain the read address corresponding to the read operation instruction;

The protocol state machine unit is used to encapsulate the read address corresponding to the read operation instruction into the sending frame data corresponding to the read operation instruction;

The serializer unit is used to send the sending frame data corresponding to the read operation instruction encapsulated by the protocol state machine unit to the slave of the protocol conversion module through the inter-chip transmission bus.

Optionally, the host of the protocol conversion module further includes:

A deserializer unit, configured to obtain serial read data corresponding to the read operation instruction on a data line of the inter-chip transmission bus, and generate received frame data corresponding to the read operation instruction;

A decoding and analysis unit, used for decoding the received frame data corresponding to the read operation instruction to obtain the read data corresponding to the read operation instruction;

A receiving data cache unit, used for caching the read data corresponding to the read operation instruction;

The on-chip bus protocol parsing unit is used to obtain the read data corresponding to the read operation instruction from the received data cache unit and send it to the on-chip bus. The control unit is used to obtain the read data corresponding to the read operation instruction through the on-chip bus.

Optionally, the host of the protocol conversion module further includes:

The second verification unit is used to verify the read data corresponding to the read operation instruction.

Optionally, the host of the protocol conversion module further includes:

The phase adjustment unit is used to adjust the phase difference of the signals transmitted on the two receiving data lines of the inter-chip transmission bus so that the signals on the two receiving data lines are signals within the same period.

Optionally, the host of the protocol conversion module further includes a bus interface control unit;

The on-chip bus protocol parsing unit is used to obtain any operation instruction on the on-chip bus, parse the target address range of the operation instruction, and when the target address range is the address range of the bus interface control unit, send the operation instruction as a bus operation instruction to the bus interface control unit;

The bus interface control unit is used to adjust the parameters of any unit in the host of the protocol conversion module or perform abnormal monitoring on any unit in response to the bus operation instruction.

Optionally, the off-chip function expansion component includes a programmable circuit module, and the programmable circuit module is used to provide an operating environment for the slave of the protocol conversion module and the expansion function module.

In a second aspect, an embodiment of the present application provides a system on chip, which includes a control unit, and the control unit interacts with multiple functional modules based on an internal bus. The system on chip includes the function expansion device described in the first aspect of the embodiment.

In a third aspect, an embodiment of the present application provides a data transmission method, which is applied to the system on chip described in the second aspect of the embodiment, and the method includes:

The host of the protocol conversion module obtains the target operation instruction for the extended function module issued by the control unit on the on-chip bus of the system on chip, and sends it to the off-chip function extension component through the inter-chip transmission bus;

The slave of the protocol conversion module in the off-chip function expansion component receives the target operation instruction and sends it to the expansion function module of the off-chip function expansion component;

The extended function module executes the target operation after responding to the target operation instruction.

In a fourth aspect, an embodiment of the present application provides a computer device, comprising: at least one processor, and a memory, wherein the memory stores a computer program that can be run on the processor, wherein the processor executes the data transmission method of the third aspect of the embodiment when executing the computer program.

In a fifth aspect, an embodiment of the present application provides a non-volatile readable storage medium, wherein the non-volatile readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the data transmission method described in the third aspect of the embodiment is performed.

In a sixth aspect, an embodiment of the present application provides a computer program product, including a computer program/instruction, which, when executed by a processor, implements the data transmission method described in the third aspect of the embodiment.

Beneficial effects:

In the function expansion device provided in this embodiment, the function expansion device includes a protocol conversion module, an inter-chip transmission bus and an off-chip function expansion component, and the off-chip function expansion component includes an expansion function module;

The host of the protocol conversion module obtains the target operation instruction for the extended function module issued by the control unit on the on-chip bus of the system-on-chip, and sends it to the off-chip function extension component through the inter-chip transmission bus; the slave of the protocol conversion module arranged in the off-chip function extension component sends the target operation instruction to the extended function module of the off-chip function extension component after receiving it; the extended function module executes the target operation after responding to the target operation instruction.

When any of the original functional modules in the system on chip fails, or when new functions need to be expanded for the system on chip, the control unit of the system on chip can send the target operation instructions to the expanded functional modules in the off-chip functional expansion component based on the protocol conversion module and the inter-chip transmission bus through the functional expansion device. In the process of functional failure recovery and new function expansion, the corresponding functions can be implemented by the expanded functional modules outside the chip without re-flowing the chip, which can improve the efficiency of the functional failure recovery and new function expansion process of the SOC system.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art.

FIG1 is a schematic diagram showing the structure of a function expansion device provided in an embodiment of the present application;

FIG2 shows a schematic diagram of an inter-chip transmission bus provided in an embodiment of the present application;

FIG3 shows a schematic diagram of the structure of a host of a protocol conversion module provided in an embodiment of the present application;

FIG4 shows a schematic diagram of a phase adjustment unit provided in an embodiment of the present application;

FIG5 shows a schematic diagram of an application of a function expansion device provided in an embodiment of the present application;

FIG6 shows a flowchart of the steps of the data transmission method provided in an embodiment of the present application;

FIG7 shows a schematic diagram of a computer device provided in an embodiment of the present application;

FIG8 shows a schematic diagram of a non-volatile readable storage medium provided in an embodiment of the present application;

FIG9 shows a schematic diagram of a computer program product provided in an embodiment of the present application.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in each embodiment of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for convenience of description, and the specific implementation of the present application should not constitute any limitation, and the various embodiments can be combined with each other and referenced to each other without contradiction.

CPU: Central Processing Unit, central processing unit;

UART: Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver/transmitter;

I2C: Inter-Integrated Circuit, integrated circuit bus, it is a serial communication bus;

SOC: System-on-a-Chip; the core of SOC is a microchip, which contains all the electronic circuits required for a complete functional system on a single integrated circuit, that is, the CPU, internal memory, I/O ports, analog input and output, and additional application-specific circuit blocks are all designed to be integrated on the same chip.

IP: Intellectual Property, also commonly known as IP core, is a circuit module design with independent functions in a chip. It is a pre-designed or even verified integrated circuit, device or component with a certain function. This circuit module design can be applied to other chip designs that contain the circuit module, which can shorten the design cycle and reduce the design workload, thereby improving the success rate of chip design.

GPIO: General-purpose input/output Ports, general-purpose input/output ports, can output high and low levels through port pins or read the pin status as high or low through them.

APB: Advanced Peripheral Bus, peripheral bus. This bus protocol is one of the AMBA bus structures proposed by ARM and has almost become a standard on-chip bus structure.

FPGA: Field Programmable Gate Array, field programmable logic gate array;

CPLD: Complex Programmable Logic Device, is a complex editable logic element;

CRC: Cyclic redundancy check, cyclic redundancy check;

I3C: Improved Inter-Integrated Circuit, is a new serial communication protocol for embedded systems.

With the development of integrated circuit technology, more and more functions are integrated into SOC systems. The realization of various functions depends on various functional IP modules in the SOC system. These functional modules are generally controlled by the CPU, and the communication between the CPU and various functional modules is realized through the on-chip bus.

However, as the number of functional modules increases, numerous IP modules have brought about a series of uncertainty problems. For example, when an IP module has a design error and cannot be used, the SOC system no longer has the functions provided by the IP module. Moreover, for functional modules that are not only mounted on the on-chip bus but also have a large amount of data interaction with other functional modules, if a fault occurs, it is not easy to find a solution to the fault, and the only solution is to re-modify the SOC system and tape out the chip.

Moreover, the application environment of the SOC system changes with the development of demand. When it is necessary to support new interfaces or add new IP module functions, the entire SOC system needs to be redesigned, that is, re-tapeout, to achieve the upgrade of new functions.

In the existing method, the solution to the problem of an IP module that has no data interaction with other modules except the bus is to replace the function of the faulty IP module based on CPU calculation.

One type is interface IP modules, such as UART modules, IIC modules, SPI modules, etc. If the SOC system has GPIO, the CPU can control the input and output of GPIO and simulate the timing of these low-speed communication interfaces, thereby realizing the function of data interaction between these interfaces and external chip interfaces.

The other type is computational IP modules, such as encryption or compression algorithm IP modules. Computational IP modules read data from the on-chip bus and perform calculations, and then write the calculation results back to the on-chip bus. In this scenario, the CPU can also be used to replace the computational IP modules to achieve the same computational functions.

However, the above two IP module solutions require CPU operations to implement corresponding functions, which will greatly reduce the efficiency of CPU operations. For example, when implementing the function of software simulating the UART module, the CPU needs to count to generate a specific baud rate and control the GPIO to continuously change the input and output to send and receive data. If the UART module is used normally, the CPU only needs to operate the on-chip bus once, and a serial port read and write operation can be implemented by reading the corresponding register. That is, only a few instructions need to be executed for the CPU. In the method based on the CPU controlling the GPIO to simulate the function of the UART module, tens of thousands of instructions need to be executed to complete a read and write operation, which occupies the CPU's processing process, resulting in a reduction in the efficiency of the CPU in executing other operations, and the accuracy of the signal generated based on the software is also relatively low.

For IP modules that do not interact with the outside of the chip, the method based on CPU software simulation has similar shortcomings. For example, encryption and decryption operations may involve many multiplication calculations. The corresponding algorithm IP module has a multiplier specifically used for calculations, which can complete the calculations in one or several cycles; however, if CPU software is used to calculate only one multiplication calculation, many instructions are required to complete it. In addition, the CPU also needs to perform data movement tasks. In the end, the implementation time of the algorithm will be greatly increased, and it is likely that the actual application requirements for algorithm speed will not be met.

Therefore, in order to improve the efficiency of the functional failure recovery and new function expansion process of the SOC system, an embodiment of the present application provides a function expansion device.

Referring to Figure 1, a structural schematic diagram of a function expansion device provided in an embodiment of the present application is shown, and the function expansion device can be applied to an on-chip system, and the on-chip system includes a control unit, an on-chip bus and multiple functional modules, and the multiple functional modules are used to interact with the control unit through the on-chip bus for data.

For example, the plurality of functional modules 1-N may be a GPIO module, a UART module, an I2C module, a Timer module, etc. The Timer module is a key hardware component for generating a time reference signal, implementing time management, and executing time-based tasks.

The function expansion device includes a protocol conversion module, an inter-chip transmission bus and an off-chip function expansion component, wherein the off-chip function expansion component includes an expansion function module; the protocol conversion module includes a host of the protocol conversion module and a slave of the protocol conversion module.

Among them, the host of the protocol conversion module is set in the system on chip and connected to the on-chip bus of the system on chip, so that the host of the protocol conversion module can interact with the control unit of the system on chip, such as the CPU; the slave of the protocol conversion module is set in the off-chip function expansion component, and the host and slave of the protocol conversion module interact with data through the inter-chip transmission bus. The slave of the protocol conversion module is used to receive any command request sent by the host of the protocol conversion module and process them, and then return the processing result to the protocol conversion module.

Specifically, the host of the protocol conversion module is used to obtain the target operation instructions for the extended function module issued by the control unit on the on-chip bus of the system-on-chip, and send them to the off-chip function extension component through the inter-chip transmission bus; after receiving the target operation instructions, the slave of the protocol conversion module sends them to the extended function module of the off-chip function extension component, and the extended function module executes the target operation after responding to the target operation instructions.

The off-chip function expansion component includes a programmable circuit module, which is used to provide an operating environment for the slave of the protocol conversion module and the extended function module. By way of example, the programmable circuit module can adopt FPGA or CPLD. Through the programmable FPGA or CPLD, it is possible to adaptively provide a normal operating environment for timely programming of the extended function module. In the actual implementation process, the programmable circuit module of the off-chip function expansion component can also be another SOC system.

The inter-chip transmission bus includes: a clock line, the direction of the clock line is from the host of the protocol conversion module to the slave of the protocol conversion module, and the slave of the protocol conversion module is used to sample and send data according to the clock line; two sending data lines, the direction of the sending data lines is from the host of the protocol conversion module to the slave of the protocol conversion module; two receiving data lines, the direction of the receiving data lines is from the slave of the protocol conversion module to the host of the protocol conversion module.

Furthermore, the two transmit data lines and the two receive data lines of the inter-chip transmission bus both adopt a double-edge transmission mode, that is, data can be sampled or sent at both the rising edge and the falling edge of the clock line, thereby having a data transmission rate that is four times the clock frequency.

2, a schematic diagram of an inter-chip transmission bus provided in an embodiment of the present application is shown. The inter-chip transmission bus includes a timeline, namely, clk, which is directed from a host of a protocol conversion module arranged in an on-chip system to a slave of a protocol conversion module arranged in an off-chip function expansion component; two transmit data lines, tx[0] and tx[1], which are directed from the host of the protocol conversion module to the slave of the protocol conversion module; and two receive data lines, rx[0] and rx[1], which are directed from the slave of the protocol conversion module to the host of the protocol conversion module.

The protocol conversion module is mainly responsible for controlling, encoding, decoding and verifying the inter-chip transmission bus protocol.

3 , a schematic diagram of the structure of the host of the protocol conversion module provided in an embodiment of the present application is shown. The host of the protocol conversion module may include: an on-chip bus protocol parsing unit, a sending data cache unit, a protocol state machine unit, a serializer unit, a deserializer unit, a decoding analysis unit, and a receiving data cache unit.

Specifically, when the target operation instruction is a write operation instruction, the on-chip bus protocol parsing unit parses the write operation instruction through the on-chip bus, according to the timing and data of the on-chip bus signal, to obtain the write address and write data corresponding to the write operation instruction, and sends them to the sending data cache unit.

The transmission data buffer unit is used to buffer the write address and write data corresponding to the write operation instruction parsed by the on-chip bus protocol parsing unit, and wait to be sent out of the chip according to the first-in first-out rule.

The protocol state machine unit is used to encapsulate the write address and write data corresponding to the write operation instruction into the sending frame data corresponding to the write operation instruction.

The serializer unit is used to send the sending frame data corresponding to the write operation instruction encapsulated by the protocol state machine unit to the slave of the protocol conversion module through the inter-chip transmission bus.

After receiving the sending frame data corresponding to the write operation instruction, the slave of the protocol conversion module decodes the sending frame data, generates the write address and write data corresponding to the write operation instruction, and then sends the write address and write data of the write operation instruction to the extended function module; the extended function module writes the target data corresponding to the write data at the position corresponding to the write address according to the write address and write data of the write operation instruction; in the actual implementation process, after the extended function module completes the execution of the write operation instruction, it can also return the operation completion response to the host of the protocol conversion module through the slave of the protocol conversion module.

Specifically, when the target operation instruction is a read operation instruction, the on-chip bus protocol parsing unit is used to obtain the read operation instruction through the on-chip bus, and parse to obtain the read address corresponding to the read operation instruction; in the actual implementation process, the read address corresponding to the read operation instruction obtained by parsing can also be stored in a fifo (First Input First Output) queue, waiting to be sent to the outside of the chip in sequence.

The protocol state machine unit is used to encapsulate the read address corresponding to the read operation instruction into the sending frame data corresponding to the read operation instruction.

The serializer unit is used to send the sending frame data corresponding to the read operation instruction encapsulated by the protocol state machine unit to the slave of the protocol conversion module through the inter-chip transmission bus.

After receiving the sending frame data corresponding to the read operation instruction, the slave of the protocol conversion module decodes the sending frame data, generates a read address corresponding to the read operation instruction, and then sends the read address of the read operation instruction to the extended function module. The extended function module obtains the corresponding read data according to the read operation instruction, and returns the read data corresponding to the read operation instruction to the slave of the protocol conversion module. The slave of the protocol conversion module sends the read data serially to the host of the protocol conversion module through the inter-chip transmission bus.

The deserializer unit in the host of the protocol conversion module is used to obtain serial read data corresponding to the read operation instruction on the data line of the inter-chip transmission bus, and generate receiving frame data corresponding to the read operation instruction.

The decoding and analysis unit is used to decode the received frame data corresponding to the read operation instruction, obtain the read data corresponding to the read operation instruction, and then send it to the received data cache unit.

The received data cache unit is used to cache the read data corresponding to the read operation instruction.

The on-chip bus protocol parsing unit obtains the read data corresponding to the read operation instruction from the received data cache unit and sends it to the on-chip bus. The control unit is used to obtain the read data corresponding to the read operation instruction through the on-chip bus.

The host of the protocol conversion module also includes: a first verification unit and a second verification unit, the first verification unit is connected between the sending data cache unit and the protocol state machine unit, the first verification unit is used to generate a corresponding verification value for the address and data of the write operation instruction or the read operation instruction obtained from the sending data cache unit, and accordingly, the slave of the protocol conversion module is provided with a verification unit for verifying the verification value generated by the first verification unit.

The second verification unit is connected to the decoding and analysis unit and is used to verify the data generated by the decoding and analysis unit to determine whether the received data is correct. Accordingly, a verification generation unit is provided on the slave of the protocol conversion module to generate a verification value for the data to be sent.

In the actual implementation process, the first check unit and the second check unit can be based on the CRC check rules, or other check methods can be selected according to the needs of the actual application, such as a checksum-based method. This embodiment is not limited to this. By checking the data sent to the outside of the chip and the data received from the outside of the chip, the correctness and accuracy of the data transmitted within and outside the chip can be guaranteed.

In a feasible implementation manner, the frame format of the frame data sent by the protocol state machine unit corresponding to any encapsulated operation instruction is shown in Table 1 below.

Table 1 Frame format for sending frame data

Specifically, when there is no frame transmission on the transmit data line or receive data line of the inter-chip transmission bus, it will remain at 0, so the signal line is set to 1 in the first cycle of the frame header and the second cycle of the frame end. The other two bits are 01 to represent the frame header and 10 to represent the frame end.

The frame type field includes 4 bits. The high bit of the 4 bits represents the read and write type, 0 represents the write type, and 1 represents the read type. The low 3 bits represent the size of the data bit, such as 000 represents 1 byte, 001 represents 2 bytes, and 100 represents 4 bytes. 4'b0111 and 4'b1111 represent read and write CRC check error frames, which will be sent only when a CRC check error occurs. The remaining frame type values can be reserved and can be configured according to the actual application requirements. The various frame types and their corresponding meanings are shown in Table 2 below:

Table 2 Various frame types and their corresponding meanings are shown in the following table:

The address field of the frame is fixed to 32 bits, representing the read and write address; and the data frame of the read data returned by the slave of the host of the protocol conversion module does not contain the address field.

Data field of the frame: It is only present in the host write operation frame or the slave return read data frame, and its length is determined by the configuration of the frame type.

CRC calculation bit: 8 bits in length, indicating the calculation result of the frame type, address, and data.

After the protocol state machine unit sends frame data corresponding to any encapsulated operation instruction, the serializer unit places the send frame data on the two send data lines of the inter-chip transmission bus from high to low. For example, tx[1] can be placed at a high position and tx[0] can be placed at a low position. Correspondingly, the deserializer restores the serial data received by the two receive data lines rx[1] and rx[0] of the inter-chip transmission bus into a complete data frame and passes it to the decoding and analysis unit.

In a feasible implementation manner, the host of the protocol conversion module further includes a phase adjustment unit for adjusting the phase difference of signals transmitted on the two receiving data lines of the inter-chip transmission bus so that the signals on the two receiving data lines are within the same cycle.

Since the on-chip system and the off-chip functional expansion components are based on the inter-chip transmission bus, and the on-chip and off-chip signals will pass through system-level components such as signal buffers, ferrite beads, and isolators during the transmission process, or due to circuit board delays, such as uneven routing lengths, long cable lengths, etc., the signal will be delayed during transmission, resulting in inconsistent sampling of the two data lines in the same transmission direction. For example, the rx[0] signal delay is smaller, while the rx[1] delay is larger, resulting in the sampled rx[0] being the data of the previous cycle, while rx[1] is the data of the next cycle, resulting in sampled data confusion. Therefore, in this embodiment, a phase adjustment unit is added to the host of the protocol conversion module.

Referring to Figure 4, a schematic diagram of a phase adjustment unit provided in an embodiment of the present application is shown, wherein the input end of the phase adjustment unit is connected to two receiving data lines of the inter-chip transmission bus, and the output is connected to the deserializer. A plurality of delay units are arranged in the phase adjustment unit, such as delay unit 1 ... delay unit 32. According to the phase difference of the data transmitted on the two receiving data lines, the number of delay units that the data on the two receiving data lines pass through is arbitrated so that the data transmitted on the two receiving data lines are synchronized.

In a feasible implementation, the host of the protocol conversion module also includes a bus interface control unit; the on-chip bus protocol parsing unit is used to obtain any operation instruction on the on-chip bus, parse the target address range of the operation instruction, and when the target address range is the address range of the bus interface control unit, send the operation instruction as a bus operation instruction to the bus interface control unit; the bus interface control unit is used to adjust the parameters of any unit in the host of the protocol conversion module or perform abnormal monitoring on any unit in response to the bus operation instruction.

When the on-chip bus protocol parsing unit receives any operation instruction of the on-chip bus, it can judge the address range of the operation instruction. If the address range of the operation instruction corresponds to an external expansion function module, the operation instruction is parsed and the operation address and/or data obtained by the analysis are written into the sending data cache unit; if the address range of the operation instruction corresponds to that of the bus interface control unit, the object of the operation instruction is the bus interface control unit, and the bus operation instruction is sent to the bus interface unit.

A management controller is provided in the bus interface control unit, which can adjust the parameters of any unit in response to a bus operation instruction. For example, the number of delay levels in the phase adjustment unit is adjusted. For example, register 100 is set as a phase adjustment register. When the bus operation instruction configures 0x80000100 to different parameter values of 0-32, the number of delay units serially connected in the phase adjustment unit can be controlled; or the verification mode of the first verification unit and the second verification unit can be adjusted, etc., or after responding to an operation instruction for characterization monitoring, any unit in the host of the protocol conversion module is monitored for abnormalities, and abnormal data is reported to the control unit of the on-chip system such as the CPU.

The module setting of the slave of the protocol conversion module is similar to that of the host. For example, the host of the protocol conversion module includes an on-chip bus protocol parsing unit, a sending data cache unit, a protocol state machine unit, a serializer unit, a phase adjustment unit, a deserializer unit, a decoding analysis unit, a receiving data cache unit, and a verification unit, etc.

The following examples illustrate the application of the function expansion device provided in this embodiment. Specifically, the application scenario is: in the SOC system, the APB bus is used as the on-chip bus between the CPU and multiple functional modules, namely, multiple IP modules in the SOC system, and the multiple IP modules mounted on the APB bus may include: GPIO module, PWM module, Timer module, I2C module and UART module. At the same time, the host of the protocol conversion module in the function expansion device provided in this embodiment is also mounted on the APB bus.

During the use of the SOC system, an I2C module that communicates with the SOC system has released the next generation of products. In order to support higher performance, the target IP module replaces the I2C interface with the I3C interface. The I3C interface is fully compatible with the I2C interface, but the I3C interface can support more functions and faster transmission speeds than the I2C interface.

Referring to Figure 5, an application schematic diagram of the function expansion device provided in an embodiment of the present application is shown. The upper half of Figure 5 is a schematic diagram of the current expansion. Since the original SOC system does not integrate the new serial communication protocol interface, namely the I3C interface, the communication between the SOC system and the external chip based on the I3C interface can only be carried out in the I2C interface mode, resulting in the performance of the new external chip based on the I3C interface cannot be fully utilized.

As shown in FIG5 , through the function expansion device of this embodiment, the SOC system can realize the communication with the external chip through the new serial communication protocol interface, namely, the I3C interface. Specifically, a programmable device FPGA or CPLD is added, and a host of the protocol conversion module and an expansion function module, namely, an external chip connected with an I3C interface, are set in the programmable device. The I3C interface of the programmable device can communicate with the external chip connected based on the I3C interface, thereby allowing the SOC system to add the function of accessing the I3C interface and allow the SOC system to read and write the target function module outside the chip.

Specifically, the control unit CPU in the SOC system can realize the control of the target functional module. Taking the register read and write operation of the target functional module as an example, the configuration operation performed by the CPU and the data transmission process in the entire path are explained:

Assume that the address range corresponding to the host of the protocol conversion module in the SOC system is: from 0x80000000 to 0x80010000, and inside the host of the protocol conversion module, the address range from 0x80000000 to 0x80008000 is used to configure the registers in the host of the protocol conversion module, such as some debug signals, phase adjustment control functions, etc., and from 0x80008000 to 0x8001000 corresponds to the address range of the target functional module.

When the write address of the write operation instruction of the CPU driving the on-chip bus, i.e., the APB bus, is 0x80008000, and the write data is 0x01, the host of the protocol conversion module first recognizes that the operation is an external chip, and parses the write address 0x80008000 and the write data 0x01, and stores them in the send data buffer unit. After the protocol state machine unit of the subsequent stage detects that the send data buffer unit is not empty, it starts to read the cached data in the send data buffer unit and generate a send data frame. The send data frame generated for the write operation instruction is:

{4’b1101, 4’b 0010, 32’h80008000, 32’h1, crc, 4’b1011}.

The serializer unit transmits data frames from high to low. For the above data, the data sent by tx[1] per cycle is:

1,0,0,1,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,crc[7],crc[5],crc[3],crc[1],1,1;

The data sent by tx[0] per cycle is: 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,crc[6],crc[4],crc[2],crc[0],0,1;

After the slave of the protocol conversion module in the off-chip function expansion component receives the send data frame from the inter-chip transmission bus, the deserializer unit of the slave of the protocol conversion module first restores the complete data frame, and then the decoding and analysis unit of the slave of the protocol conversion module parses the data frame, caches the write address and data, and then the on-chip bus protocol parsing unit in the slave of the protocol conversion module generates the APB master timing and configures it to the external chip, thus completing a complete write operation.

If the read operation instruction issued by the CPU is executed, taking the reading of the 0x80008000 register as an example, the transmission data frame generated by the protocol state machine unit in the host of the protocol conversion module is:

{4’b1101, 4’b0010, 32’h80008000, crc, 4’b1011}

After the slave of the protocol conversion module receives the data frame and parses the read address, the apb master timing generated by the on-chip bus protocol parsing unit in the slave of the protocol conversion module reads the data 0x1 from the register of the external chip based on the I3C interface, and the protocol state machine unit of the slave generates the send data frame returned by the read operation instruction:

{1101, 1010, 32’h1, crc, 1011}.

When the circuit board or programmable device bit stream in the off-chip function expansion component of this embodiment is just generated, the correctness of data reading and writing can be tested first. At this time, you can try to read and write a register of the external chip; if the data read back is incorrect or no data frame is returned for a long time, it may be due to signal delay problems that cause sampling data errors. The signal delay and phase can be changed by continuously modifying the number of delay units in the phase adjustment unit; when the debugging is successful, if there is no hardware change, it can run with the current delay level every time thereafter.

When the read and write function test and debugging of a register of the external chip are successful, data transmission errors may still occur during the actual operation due to signal problems such as interference. When the host or slave of the protocol conversion module determines that the received data frame has a CRC check error, the host/slave can be set to send a special CRC error frame to the slave/host.

Assume that during the above-mentioned write operation to the external chip, when the slave of the protocol conversion module detects that there is a CRC error in the write data frame sent by the host, it immediately sends a frame of {1101,0111 1011} to the host to indicate that there is an error in the transmission of the write data frame; if during the read operation of the external chip, the slave detects that there is an error in the data frame of the read address sent by the host, it will immediately send {1101,1111 1011} to the host. If the host receives an error in the data frame read back from the slave, it will also send a data frame of {1101,1111 1011} to the slave.

The function expansion device provided in this embodiment can send the target operation instructions for the expanded function module on the on-chip bus of the system on chip to the off-chip function expansion component through the inter-chip transmission bus. The expanded function module in the external function expansion component can be any faulty function module originally in the system on chip. When the function module of the system on chip fails, the function of the faulty function module can be implemented by performing target operations on the off-chip function module without re-taping or letting the CPU calculate. The expanded function module can also be an external chip for any new function expansion in the SOC system application process, so that the functions required by the SOC system can be expanded without re-taping, which can improve the efficiency of the SOC system's functional fault recovery and new function expansion process. At the same time, the function expansion device in this embodiment also has the advantages of small interface signal occupancy and simple software implementation, which not only reduces the risk of system chip tape-out, but also improves the scalability of the SOC chip.

6, a flowchart of a data transmission method provided in an embodiment of the present application is shown. The method is applied to the system on chip described in this embodiment, and the method includes the following steps:

S101: The host of the protocol conversion module obtains the target operation instruction for the extended function module issued by the control unit on the on-chip bus of the system on chip, and sends it to the off-chip function extension component through the inter-chip transmission bus;

S102: The slave of the protocol conversion module in the off-chip function expansion component receives the target operation instruction and sends it to the expansion function module of the off-chip function expansion component;

S103: The extended function module executes the target operation in response to the target operation instruction.

Referring to Figure 7, a schematic diagram of a computer device provided in an embodiment of the present application is shown, and the computer device includes: at least one processor 701, and a memory 702, wherein the memory 702 stores a computer program that can be executed on the processor 701, wherein the processor 701 executes the data transmission method described in the embodiment when executing the computer program.

8 , a schematic diagram of a non-volatile readable storage medium provided in an embodiment of the present application is shown, wherein the non-volatile readable storage medium 800 stores a computer program 801 , wherein the computer program 801 performs the data transmission method described in the embodiment when executed by a processor.

9 , a schematic diagram of a computer program product provided in an embodiment of the present application is shown, wherein the computer program product 900 includes a computer program/instruction 901 , which implements the data transmission method described in the embodiment when executed by a processor.

Claims (16)

1. A function expansion device, characterized by being applied to a system on chip, the system on chip comprising a control unit; the function expansion device comprises a protocol conversion module, an inter-chip transmission bus and an off-chip function expansion assembly, wherein the off-chip function expansion assembly comprises an expansion function module;

The host of the protocol conversion module is arranged in the system on chip, and is used for acquiring a target operation instruction aiming at the expansion function module and issued by the control unit on an on-chip bus of the system on chip, and sending the target operation instruction to the off-chip function expansion assembly through the inter-chip transmission bus;

The off-chip function expansion assembly comprises a slave of the protocol conversion module, wherein the slave of the protocol conversion module is used for receiving the target operation instruction and sending the target operation instruction to an expansion function module of the off-chip function expansion assembly;

And the expansion function module is used for executing target operation after responding to the target operation instruction.

2. The function expansion device according to claim 1, wherein the inter-chip transfer bus includes:

the direction of the clock line is from the host computer of the protocol conversion module to the slave computer of the protocol conversion module, and the slave computer of the protocol conversion module is used for sampling and transmitting data according to the clock line;

The two transmitting data lines are arranged in the direction from the host of the protocol conversion module to the slave of the protocol conversion module;

The direction of the two receiving data lines is from the slave machine of the protocol conversion module to the host machine of the protocol conversion module.

3. The function expanding apparatus according to claim 2, wherein the two transmitting data lines and the two receiving data lines each adopt a double-edge transmission method.

4. The function expansion device according to claim 1, wherein the target operation instruction includes a write operation instruction, and the host of the protocol conversion module includes:

The on-chip bus protocol analysis unit is used for analyzing the write operation instruction through the on-chip bus to obtain a write address and write data corresponding to the write operation instruction, and sending the write address and write data to the data sending cache unit;

the sending data caching unit is used for caching the write address and the write data corresponding to the write operation instruction;

A protocol state machine unit, configured to encapsulate a write address and write data corresponding to the write operation instruction into transmission frame data corresponding to the write operation instruction;

and the serializer unit is used for transmitting the transmission frame data corresponding to the write operation instruction after being packaged by the protocol state machine unit to the slave machine of the protocol conversion module through the inter-chip transmission bus.

5. The function expansion device according to claim 4, wherein the host of the protocol conversion module of the system on chip further comprises:

and the first verification unit is used for generating a verification value of the write address and the write data corresponding to the write operation instruction.

6. The function expanding apparatus of claim 4, wherein the target operation instruction comprises a read operation instruction,

The on-chip bus protocol analysis unit is used for acquiring the read operation instruction through the on-chip bus and analyzing to obtain a read address corresponding to the read operation instruction;

The protocol state machine unit is used for packaging the read address corresponding to the read operation instruction into the transmission frame data corresponding to the read operation instruction;

The serializer unit is used for transmitting the frame data corresponding to the read operation instruction packaged by the protocol state machine unit to the slave of the protocol conversion module through the inter-chip transmission bus.

7. The function expansion device according to claim 6, wherein the host of the protocol conversion module further comprises:

The deserializer unit is used for acquiring serial read data corresponding to the read operation instruction on a data line of the inter-chip transmission bus and generating received frame data corresponding to the read operation instruction;

the decoding analysis unit is used for decoding the received frame data corresponding to the read operation instruction to obtain read data corresponding to the read operation instruction;

the received data caching unit is used for caching the read data corresponding to the read operation instruction;

The on-chip bus protocol analysis unit is used for acquiring the read data corresponding to the read operation instruction from the received data caching unit and sending the read data to the on-chip bus, and the control unit is used for acquiring the read data corresponding to the read operation instruction through the on-chip bus.

8. The function expansion device according to claim 7, wherein the host of the protocol conversion module further comprises:

and the second verification unit is used for verifying the read data corresponding to the read operation instruction.

9. The function expansion device according to claim 7, wherein the host of the protocol conversion module further comprises:

And the phase adjusting unit is used for adjusting the phase difference of signals transmitted on the two receiving data lines of the inter-chip transmission bus so that the signals on the two receiving data lines are signals in the same period.

10. The apparatus according to claim 4 or 6, wherein the host of the protocol conversion module further comprises a bus interface control unit;

The on-chip bus protocol analysis unit is used for acquiring any operation instruction on the on-chip bus, analyzing a target address range of the operation instruction, and sending the operation instruction to the bus interface control unit as a bus operation instruction when the target address range is the address range of the bus interface control unit;

the bus interface control unit is used for responding to the bus operation instruction, adjusting the parameter of any unit in the host of the protocol conversion module or monitoring the abnormality of any unit.

11. The apparatus of claim 1, wherein the off-chip functional extension component comprises a programmable circuit module to provide an operating environment for a slave of the protocol conversion module and the extension functional module.

12. A system on chip, characterized in that it comprises a control unit that performs data interaction with a plurality of functional modules based on an on-chip bus, the system on chip comprising the function expanding device according to any of claims 1-11.

13. A data transmission method applied to the system on chip of claim 12, the method comprising:

the host of the protocol conversion module acquires a target operation instruction aiming at the expansion function module and issued by the control unit on an on-chip bus of the on-chip system, and sends the target operation instruction to the off-chip function expansion assembly through an on-chip transmission bus;

The slave of the protocol conversion module in the off-chip function expansion assembly receives the target operation instruction and sends the target operation instruction to an expansion function module of the off-chip function expansion assembly;

and after responding to the target operation instruction, the expansion function module executes target operation.

14. A computer device, comprising: at least one processor, and a memory storing a computer program executable on the processor, wherein the processor performs the data transmission method of claim 13 when the processor executes the computer program.

15. A non-transitory readable storage medium storing a computer program, wherein the computer program when executed by a processor performs the data transmission method of claim 13.

16. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the data transmission method of claim 13.