CN118689827A - Storage expansion system and resource configuration method thereof - Google Patents

Abstract

The present invention provides a storage expansion system and a resource configuration method thereof. A PCIe expansion card is suitable for directly or indirectly connecting N storage expansion devices through M interfaces. A host device includes a PCIe slot, a flash memory and a processor. The flash memory is used to record BIOS. The processor executes BIOS to: determine whether the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot conform to the specific identification code specified by the BIOS; when the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot conform to the secondary vendor identification code and the secondary device identification code specified by the BIOS, stop scanning any PCIe device under the root bridge corresponding to the PCIe slot during the enumeration process, and configure the memory mapping I/O resources to the root bridge according to the expansion support quantity; and allocate the memory mapping I/O resources to the M interfaces of the PCIe expansion card. In this way, it can be avoided that the storage expansion device cannot obtain sufficient memory mapping I/O resources and bus resources due to hot plug events.

Description

Storage expansion system and resource configuration method thereof

Technical Field

The present invention relates to a storage system, and in particular to a storage expansion system and a resource configuration method thereof.

Background Art

There are various buses in computer systems that are used to connect the main processor and other devices and transfer data between them. The bus can be used not only to couple the main processor, random access flash memory (Flash memory) and main memory (DDR), but also to couple other external devices. Currently, the Peripheral Component Interconnect Express (PCIe) bus has been widely used in computer systems on the market today, such as personal computers or servers. PCIe is a newly developed industrial bus standard, which is an improvement on PCI (Peripheral Component Interconnect). The PCIe bus standard is developed and maintained by the Peripheral Component Interconnect Special Interest Group (PCI-SIG).

Existing computer systems can support one or more PCIe slots, so that users can insert various interface cards into these PCIe slots according to different needs, thereby expanding the functions of the computer system. At present, in order for the interface card plugged into the PCIe slot to operate normally, the basic input and output system (BIOS) of the computer system needs to properly configure the PCIe resources. Under the condition of properly configuring the PCIe resources, the operating system of the computer system can effectively communicate with the expansion hardware devices at the rear end of the PCIe slot so that the functions of these expansion hardware devices can be performed normally. On the other hand, when the expansion hardware device at the rear end of the PCIe slot is not allocated with appropriate PCIe resources (for example, due to hot plugging, the appropriate PCIe resources cannot be allocated), it may not only cause the expansion hardware device to fail to function normally or the transmission speed to decrease, but also cause the computer system to freeze. In particular, when the number of expansion hardware devices connected in series or the actual connection timing behind the PCIe slot are uncertain factors, the existing BIOS may allocate insufficient PCIe resources to the PCIe slot, thereby causing the expansion hardware device behind the PCIe slot to be unable to obtain appropriate PCIe resources.

Summary of the invention

The present invention relates to an embodiment of the present invention to provide a storage expansion system and a resource configuration method thereof, which can configure a storage expansion device connected to a host device via a PCIe expansion card and a PCIe slot with appropriate PCIe resources.

An embodiment of the present invention provides a storage expansion system, which includes (but is not limited to) N storage expansion devices, a PCIe expansion card, and a host device. N is an integer greater than 0. The PCIe expansion card has M interfaces and is suitable for directly or indirectly connecting the N storage expansion devices through the M interfaces, where M is an integer greater than 0. The host device includes a PCIe slot, a flash memory, a main memory (DDR) and a processor. The flash memory is used to record and store BIOS. The processor is coupled to the PCIe slot, the main memory and the flash memory, and executes the BIOS to determine whether the secondary vendor identification code and the secondary device identification code of the PCIe expansion card inserted in the PCIe slot are consistent with the secondary vendor identification code and the secondary device identification code specified by the BIOS; when the secondary vendor identification code and the secondary device identification code of the PCIe expansion card inserted in the PCIe slot are consistent with the secondary vendor identification code and the secondary device identification code specified by the BIOS, stop scanning any PCIe device under the root bridge corresponding to the PCIe slot during the enumeration process, and configure memory-mapped input/output (MMI/O) resources to the root bridge according to the expansion support quantity; and allocate the memory-mapped I/O resources to M interfaces of the PCIe expansion card.

An embodiment of the present invention provides a method for configuring resources of a storage system, and the storage expansion system includes a PCIe expansion card, a host device, and N storage expansion devices. The PCIe expansion card has M interfaces, and the host device has a PCIe slot. The method for configuring resources of the storage system includes (but is not limited to): during the execution of the BIOS, determining whether the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot are consistent with the secondary vendor identification code and the secondary device identification code specified by the BIOS; when the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot are consistent with the secondary vendor identification code and the secondary device identification code specified by the BIOS, stopping scanning any PCIe device under the root bridge corresponding to the PCIe slot during the enumeration process, and configuring the memory mapping I/O resources to the root bridge according to the expansion support quantity; and allocating the memory mapping I/O resources to the M interfaces of the PCIe expansion card.

Based on the above, in an embodiment of the present invention, during the execution of BIOS, the host device determines whether the PCIe slot is plugged into a PCIe expansion card for connecting a storage expansion device. When the PCIe slot is plugged into the PCIe expansion card, sufficient memory mapping I/O resources can be reserved for the root bridge corresponding to the PCIe slot, and the reserved memory mapping I/O resources can be distributed downward to the M interfaces of the PCIe expansion card. In this way, regardless of the actual connection timing of the storage expansion device, the storage expansion device directly or indirectly connected to the PCIe expansion card can be configured with appropriate memory mapping I/O resources so that the storage expansion device can function normally.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a storage expansion system according to an embodiment of the present invention;

FIG2 is a schematic diagram of a PCIe expansion card according to an embodiment of the present invention;

3A and 3B are flow charts of a resource configuration method of a storage expansion system according to an embodiment of the present invention;

FIG4 is a schematic diagram of a PCIe topology according to an embodiment of the present invention;

5 is a schematic diagram of transmitting a presence signal and a hardware reset signal according to an embodiment of the present invention;

FIG. 6 is a flow chart of a resource configuration method of a storage expansion system according to an embodiment of the present invention.

Description of Reference Numerals

10: Storage expansion system;

110_1～110_N, 150, 160: storage expansion equipment;

120: PCIe expansion card;

130: host device;

DP1_1~DP1_M: interface;

131: PCIe slot;

132: flash memory;

133: processor;

134: main memory;

B1: Basic Input and Output System;

S_1～S_P: storage device;

121: Gold Finger;

RB1: root bridge;

DP4_1, DP2_1, DP3_1, DP5_1: Downstream interface;

P1～P6: pins;

UP1~UP2: Uplink interface;

R1, R2: Hardware reset signal;

NP1, NP2: signal exists;

S302~S346, S602~S606: steps.

DETAILED DESCRIPTION

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

FIG1 is a block diagram of a storage system according to an embodiment of the present invention. Referring to FIG1 , the storage expansion system 10 includes N storage expansion devices 110_1 to 110_N, a PCIe expansion card 120, and a host device 130. N is an integer greater than 0.

The PCIe expansion card 120 may be implemented as an interface card including a PCIe switch. The PCIe expansion card 120 has M interfaces DP1_1 to DP1_M. The PCIe expansion card 120 is suitable for directly or indirectly connecting N storage expansion devices 110_1 to 110_N through the M interfaces DP1_1 to DP1_M, where M is an integer greater than 0. More specifically, the M interfaces DP1_1 to DP1_M may be downstream ports supporting the PCIe standard. In addition, the PCIe expansion card 120 may also include an upstream port for connecting to the PCIe slot 131.

For example, FIG. 2 is a schematic diagram of a PCIe expansion card according to an embodiment of the present invention. Referring to FIG. 2 , taking M=2 as an example, a PCIe expansion card 120 may have two interfaces DP1_1-DP1_2 and a gold finger 121 supporting the PCIe standard. The present invention does not limit the number of PCIe channels of the gold finger 121. The gold finger 121 is suitable for being inserted into a PCIe slot 131 of a host device 130. In addition, the interfaces DP1_1-DP1_2 are used to directly connect to corresponding storage expansion devices via cables.

It is worth mentioning that the PCIe expansion card 120 can directly or indirectly connect to N storage expansion devices 110_1~110_N. As shown in the example of Figure 1, the storage expansion device 110_1 can be directly connected to the interface DP1_1 of the PCIe expansion card 120. The storage expansion device 110_N can be directly connected to the interface DP1_2 of the PCIe expansion card 120. It should be noted that in an embodiment of the present invention, the N storage expansion devices 110_1~110_N have the function of being connected in series with each other. As shown in the example of Figure 2, the storage expansion device 110_2 can be connected in series to the storage expansion device 110_1, so that the storage expansion device 110_2 is indirectly connected to the interface DP1_1 of the PCIe expansion card 120. However, the connection method of the storage expansion devices 110_1~110_N in Figure 1 is only an exemplary description and is not used to limit the present invention.

In some embodiments, the storage expansion devices 110_1-110_N may be implemented as a Just a Bunch Of Disks (JBOD) device, which may include P storage devices S_1-S_P. P is an integer greater than 0. The storage devices S_1-S_P are, for example, solid state drives (SSD) and/or hard disk drives (HDD), but the present invention is not limited thereto. Each storage expansion device 110_1-110_N may include an upstream interface for connecting to an upper-level device (i.e., a PCIe expansion card 120 or other storage expansion device) and supporting the PCIe standard, and a downstream interface for connecting to a lower-level device (i.e., other storage expansion devices) and the storage devices S_1-S_P and supporting the PCIe standard. In some embodiments, since each storage expansion device 110_1-110_N may include a downstream interface for connecting to a lower-level device (ie, other storage expansion devices), the storage expansion devices 110_1-110_N may be connected in series via cables. For example, the storage expansion devices 110_1-110_N may support daisy-chain connection.

The host device 130 includes a PCIe slot 131, a flash memory 132, a processor 133, and a main memory 134. In some embodiments, the host device 130 can be implemented as a network attached storage (NAS) device or other types of computer systems. An interface card with a PCIe gold finger (such as a PCIe expansion card or other types of expansion cards) can be plugged into the PCIe slot 131. The present invention does not limit the number of PCIe channels of the PCIe slot 131.

The flash memory 132 is used to record and store the basic input and output system (BIOS) B1. The BIOS B1 is a firmware used in the boot process after the host device 130 is booted. In addition, the host device 130 has a main memory 134 (DDR) or other memory elements that can be accessed by the processor 133.

The processor 133 is coupled to the PCIe slot 131 and the flash memory 132, and can be a central processing unit (CPU), a general purpose processor, or other similar components or a combination of the above components. The processor 133 can execute the BIOS B1 and the operating system recorded (stored) in the flash memory 132 to implement the resource configuration method in the embodiment of the present invention.

In some embodiments, during the execution of the BIOS, the processor 133 may determine whether the PCIe slot 131 is plugged with a PCIe expansion card 120 for connecting the N storage expansion devices 110_1-110_N. When the PCIe slot 131 is plugged with a PCIe expansion card 120, the processor 133 stops scanning any PCIe device under the root bridge corresponding to the PCIe slot 131 during the enumeration process, and allocates memory mapping I/O resources to the root bridge according to the expansion support quantity.

That is, in the case where the PCIe device under the root bridge corresponding to the PCIe slot 131 is not scanned, the processor 133 can directly reserve sufficient memory mapping I/O resources for the root bridge corresponding to the PCIe slot 131 according to the expansion support quantity. Then, the processor 133 can allocate the memory mapping I/O resources to the M interfaces DP1_1~DP1_M of the PCIe expansion card 120, so that each storage expansion device 110_1~110_N connected to the PCIe expansion card 120 can successfully obtain a part of the memory mapping I/O resources configured for this root bridge.

In some embodiments, the memory-mapped I/O resources may be memory-mapped input/output (MMI/O) space. In addition to the memory-mapped I/O resources, the processor 133 may also pre-configure sufficient bus resources to the root bridge corresponding to the PCIe slot 131, so that each storage expansion device 110_1 to 110_N connected to the PCIe expansion card 120 may successfully obtain a portion of the bus resources configured for the root bridge. The following examples are listed to clearly illustrate.

3A and 3B are flow charts of a method for resource allocation of a storage expansion system according to an embodiment of the present invention. Referring to FIG3A and FIG3B , the method of this embodiment can be executed by the storage expansion system 10 of FIG1 , and the following will describe the details of each step of FIG3A and FIG3B with the components shown in FIG1 .

In step S302, the host device 130 is powered on, and the processor 133 starts to execute BIOS B1. In step S304, the processor 133 starts to execute the PCI bus driver in BIOS B1. In step S306, the processor 133 checks the PCIe devices behind multiple root bridges during the enumeration process. These root bridges include the root bridge corresponding to the PCIe slot 131. The PCIe enumeration process is used to construct the PCIe topology and allocate PCIe resources (i.e., MMI/O space or bus number) to the PCIe devices. Here, the PCIe device may include a PCIe endpoint device, a PCIe bridge, or a PCIe switch, etc.

In step S308, the processor 133 determines whether the secondary vendor identification code and the secondary device identification code of the PCIe expansion card 120 inserted into the PCIe slot 131 conform to the secondary vendor identification code and the secondary device identification code specified by BIOS B1. Specifically, the processor 133 can determine whether the secondary vendor identification code (SSID) or/and the secondary device identification code (SVID) in the register (Standard registers of PCI Configuration Space Header) of the PCIe expansion card 120 conform to the specific identification code set by BIOS, so as to determine whether the PCIe slot 131 is inserted with the PCIe expansion card 120 suitable for connecting the N storage expansion devices 110_1 to 110_N. In other words, the processor 133 not only determines whether an interface card is inserted into the PCIe slot 131, but also determines the type of the interface card inserted into the PCIe slot 131 through the secondary vendor identification code and the secondary device identification code. Any interface card supporting PCIe (including the PCIe expansion card 120 ) can be plugged into the PCIe slot 131 .

If the judgment in step S308 is yes, in step S310, when the secondary vendor ID and the secondary device ID of the PCIe expansion card 120 inserted into the PCIe slot 131 match the secondary vendor ID and the secondary device ID specified by BIOS B1, the processor 133 stops scanning any PCIe device under the root bridge corresponding to the PCIe slot 131 during the enumeration process, and configures the memory mapping I/O resources to the root bridge corresponding to the PCIe slot 131 according to the expansion support quantity. In other words, when the PCIe expansion card 120 for connecting N storage expansion devices 110_1 to 110_N is inserted into the PCIe slot 131, the processor 133 does not scan down any PCIe device serially connected to the back end of the PCIe slot 131, but can reserve and directly configure the memory mapping I/O resources to the root bridge corresponding to the PCIe slot 131.

In step S312, the processor 133 writes the address range of the MMI/O space into the register of the root bridge corresponding to the PCIe slot 131. The detailed operation of writing the address range of the MMI/O space into the register of the root bridge has been specified in the PCIe standard. Specifically, the processor 133 may write the starting address of the MMI/O space into the memory base register in the configuration space of the root bridge corresponding to the PCIe slot 131, and may write the ending address of the MMI/O space into the memory limit register in the configuration space of the root bridge corresponding to the PCIe slot 131.

To make the concept of the present invention easier to understand, please refer to FIG. 4, which is a schematic diagram of a PCIe topology according to an embodiment of the present invention. In the example of FIG. 4, to make the concept of the present invention easier to understand, M=2 and N=2 are used as an example for description, but the present invention is not limited thereto.

The PCIe slot 131 corresponds to the root bridge RB1, which is connected to the downstream interface DP4_1 of the PCIe slot 131. The PCIe slot 131 is connected to the PCIe expansion card 120 via the downstream interface DP4_1. The storage expansion devices 110_1 and 110_2 are serially connected to the rear end of the PCIe expansion card 120. The storage expansion device 110_2 can be serially connected to the downstream interface DP2_1 of the storage expansion device 110_1, and indirectly connected to the interface DP1_1 of the PCIe expansion card 120. Similarly, the storage expansion device 110_2 also has a downstream interface DP3_1 for connecting to other storage expansion devices. During the enumeration process, when the processor 133 finds that the PCIe expansion card 120 is plugged into the PCIe slot 131, the processor 133 will not follow the depth-first order and stop scanning other PCIe devices at the rear end of the PCIe slot 131. That is, the processor 133 does not scan the PCIe expansion card 120 and the storage expansion devices 110_1 and 110_2. In addition, the processor 133 can allocate enough MMI/O space to the root bridge RB1 according to the expansion support quantity.

In some embodiments, the above expansion support quantity is the maximum serial connection quantity of N storage expansion devices 110_1~110_N. That is, the maximum serial connection quantity represents the maximum number of storage expansion devices that can be serially connected to the PCIe expansion card 120. The maximum serial connection quantity can be a preset value, and this preset value can be designed according to actual needs, and the present invention is not limited to this. For example, assuming that the PCIe expansion card 120 can be designed to serially connect up to 16 storage expansion devices 110_1~110_16, the expansion support quantity is 16. In this case, the processor 133 can configure memory mapping I/O resources sufficient for 16 storage expansion devices 110_1~110_16 to the root bridge corresponding to the PCIe slot 131. For example, assuming that a storage expansion device requires Abyte of MMI/O space, the processor 133 can configure at least 16*A byte of MMI/O space to the root bridge RB1 corresponding to the PCIe slot 131. The processor 133 may record the 16*Abyte MMI/O space in a memory base register and a memory limit register in the configuration space of the root bridge RB1 .

On the other hand, if the determination result of step S308 is no, in step S316, the processor 133 scans all PCIe devices at the back end of the root bridge and calculates the MMI/O space and bus resources required by the root bridge. That is, when the PCIe slot 131 is plugged with other interface cards, the processor 133 can scan all PCIe devices at the back end of the root bridge in a depth-first order and calculate the MMI/O space and bus resources required by all PCIe devices at the back end of the root bridge.

In step S318, the processor 133 writes the bus resources required by the root bridge into the register of the root bridge. The detailed operation of writing the bus resources into the register of the root bridge has been specified in the PCIe standard. Specifically, the processor 133 can write the bus resources required by the root bridge into the subordinate bus number register (Subordinate bus number register) and the secondary bus number register (Secondary bus number register) in the configuration space of the root bridge. Thereafter, in step S320, the processor 133 writes the address range of the MMI/O space into the register of the root bridge. In step S322, the processor 133 writes the address range of the MMI/O space into the registers of other interface cards. Specifically, the processor 133 can write the address range of the MMI/O space into the base address register (Base address register, BAR) of other interface cards.

It can be seen that steps S316 to S322 are steps implemented for other common interface cards, and the detailed operation contents can refer to the PCIe standard. It should be noted that steps S310 to S312 are steps implemented for the PCIe expansion card 120 that can connect multiple storage expansion devices in series.

Afterwards, in step S314, the processor 133 determines whether the last PCIe device is enumerated. If the determination in step S314 is no, the process returns to step S306, and the processor 133 continues to scan the next root bridge. If the determination in step S314 is yes, in step S324, the processor 133 ends the execution of the PCI bus driver in BIOS B1. In step S326, the processor 133 starts the execution of the storage expansion device driver in BIOS B1.

Next, referring to FIG. 3B , in step S328, the processor 133 determines whether the secondary vendor ID and the secondary device ID of the PCIe expansion card 120 plugged into the PCIe slot 131 match the secondary vendor ID and the secondary device ID specified by BIOS B1. If the determination in step S328 is no, in step S330, the processor 133 ends executing the storage expansion device driver in BIOS B1. In step S332, the processor 133 starts the operating system.

On the other hand, if the judgment in step S328 is yes, in step S334, the processor 133 collects the relevant information of the root bridge corresponding to the PCIe slot 131. In step S336, when the PCIe slot 131 is plugged with the PCIe expansion card 120, the processor 133 calculates the number of available buses after the enumeration process is completed. In other words, after the enumeration process is completed, the processor 133 can calculate the number of remaining available buses and bus numbers. Based on the PCIe standard supporting up to 256 buses, the maximum number of buses is 256, which can correspond to bus numbers "0" to "255" respectively. Assuming that after the enumeration process is completed, j buses have been used, there are 256-j buses left that can be configured to the root bridge corresponding to the PCIe slot 131.

In step S338, before allocating bus resources and memory-mapped I/O resources to the M interfaces of the PCIe expansion card, the processor 133 may clear resource configuration settings on the N storage expansion devices 110_1 to 110_N. Specifically, in order to ensure that the correct resource configuration settings can be written into the configuration spaces of the N storage expansion devices 110_1 to 110_N, the processor 133 may first clear the resource configuration settings in the configuration spaces of the N storage expansion devices 110_1 to 110_N. For example, the processor 133 may first clear the record value of the base address register (BAR) in the configuration spaces of the N storage expansion devices 110_1 to 110_N.

In step S340, the processor 133 configures bus resources to the root bridge corresponding to the PCIe expansion card 120 according to the number of available buses and the expansion support number, and allocates the bus resources to the M interfaces DP1_1~DP1_M of the PCIe expansion card 120. As mentioned above, the expansion support number can be the maximum serial connection number of N storage expansion devices 110_1~110_N. For example, assuming that a storage expansion device requires B bus numbers and the expansion support number is 16, the processor 133 can configure at least 16*B bus numbers to the root bridge corresponding to the PCIe slot 131. It can be seen that even if there is no storage expansion device connected in series behind the PCIe expansion card 120, the processor 133 still configures the memory mapping I/O resources and bus resources to the root bridge corresponding to the PCIe expansion card 120 according to the expansion support number. Next, the processor 133 allocates the bus resources of the root bridge corresponding to the PCIe expansion card 120 to the M interfaces DP1_1-DP1_M of the PCIe expansion card 120. Afterwards, in step S342, the processor 133 allocates the MMI/O space of the root bridge corresponding to the PCIe expansion card 120 to the M interfaces DP1_1-DP1_M of the PCIe expansion card 120.

In some embodiments, the processor 133 may evenly distribute the memory-mapped I/O resources to the M interfaces DP1_1 to DP1_M of the PCIe expansion card 120, wherein each of the M interfaces DP1_1 to DP1_M obtains one-Mth of the memory-mapped I/O resources. In addition, the processor 133 may evenly distribute the bus resources to the M interfaces DP1_1 to DP1_M of the PCIe expansion card 120, wherein each of the M interfaces DP1_1 to DP1_M obtains one-Mth of the bus resources. For example, assuming that the processor 133 configures 16*B bus numbers and 16*A bytes of MMI/O space to the root bridge corresponding to the PCIe expansion card 120, the processor 133 may allocate 16*B/M bus numbers and 16*A/M bytes of MMI/O space to each interface DP1_1 to DP1_M. Alternatively, in some other embodiments, the processor 133 may unequally distribute bus resources and memory-mapped I/O resources to the M interfaces DP1_1-DP1_M of the PCIe expansion card 120. That is, the number of bus resources and memory-mapped I/O resources obtained by each interface DP1_1-DP1_M may be different.

To make the concept of the present invention easier to understand, please refer to FIG. 4 again. After the processor 133 directly allocates the MMI/O space and bus resources to the root bridge RB1 according to the expansion support quantity, the processor 133 may allocate the MMI/O space and bus resources allocated to the root bridge RB1 to the interfaces DP1_1 and DP1_2. The processor 133 may symmetrically allocate the MMI/O space and bus resources to the interfaces DP1_1 and DP1_2, so that the interfaces DP1_1 and DP1_2 are allocated the same MMI/O space and bus resources. For example, assuming that the processor 133 directly allocates X bytes of MMI/O space and Y bus numbers to the root bridge RB1, the interfaces DP1_1 and DP1_2 may respectively obtain X/2 bytes of MMI/O space and Y/2 bus numbers. Alternatively, the processor 133 may allocate the MMI/O space and bus resources to the interfaces DP1_1 and DP1_2 asymmetrically, so that the interfaces DP1_1 and DP1_2 are configured with different MMI/O spaces and bus resources. For example, assuming that the processor 133 directly allocates X bytes of MMI/O space and Y bus numbers to the root bridge RB1, the interface DP1_1 may obtain k bytes of MMI/O space and q bus numbers, and the interface DP1_2 may obtain (X-k) bytes of MMI/O space and (Y-q) bus numbers.

Afterwards, in step S344, the processor 133 ends executing the storage expansion device driver in BIOS B1. In step S346, the processor 133 starts the operating system OS. After starting the operating system, the processor 133 executes OS instructions to allocate the memory mapping I/O resources and bus resources obtained by the interfaces DP1_1 to DP1_M to the storage expansion devices 110_1 to 110_N. For example, referring to FIG. 4 again, after starting the operating system, the processor 133 executes OS instructions to allocate the MMI/O space and bus number obtained by the interface DP1_1 to the storage expansion devices 110_1 and 110_2.

It should be particularly noted that the processor 133 has pre-configured sufficient memory-mapped I/O resources and bus resources to the root bridge corresponding to the PCIe slot 131 by executing the BIOS instructions, and distributes the memory-mapped I/O resources and bus resources configured to the root bridge corresponding to the PCIe slot 131 to the M interfaces DP1_1~DP1_M. Therefore, if another storage expansion device can be hot-plugged and connected to one of the M interfaces DP1_1~DP1_M after starting the operating system, the other storage expansion device can still be successfully configured with the memory-mapped I/O resources and bus resources through the operating system.

It should be noted that, in some embodiments, when another storage expansion device is hot-pluggably connected to one of the M interfaces DP1_1 to DP1_M during the execution of the operating system, the other storage expansion device may perform a hardware reset operation. After the hardware reset operation, the operating system of the other storage expansion device obtains a portion of the bus resources allocated to one of the M interfaces DP1_1 to DP1_M and a portion of the memory-mapped I/O resources allocated to one of the M interfaces DP1_1 to DP1_M. Specifically, after the other storage expansion device performs the hardware reset operation, the processor 133 executes OS instructions to allocate the memory-mapped I/O resources and bus resources allocated to one of the interfaces DP1_1 to DP1_M to which the other storage expansion device is connected to the other storage expansion device.

FIG5 is a schematic diagram of transmitting a presence signal and a hardware reset signal according to an embodiment of the present invention. Referring to FIG5, after starting the operating system, the processor 133 has allocated memory-mapped I/O resources and bus resources to all interfaces DP1_1 to DP1_M. After starting the operating system, another storage expansion device 150 can be hot-pluggably connected to the interface DP1_2 of the PCIe expansion card 120.

When another storage expansion device 150 is connected to one of the M interfaces DP1_1 to DP1_M (e.g., interface DP1_2 shown in the example of FIG. 5 ), the other storage expansion device 150 provides a presence signal NP1 to the PCIe expansion card 120 through the pin P3 of the upstream interface UP1, so that the PCIe expansion card 120 sends a hardware reset signal R1 to the other storage expansion device 150 through the pin P2 of the interface DP1_2. Further, the PCIe expansion card 120 can detect whether the storage expansion device 150 is connected to the interface DP1_2 through the pin P1 of the interface DP1_2. In some embodiments, when the pin P1 used to detect the connection status has a low level, the PCIe expansion card 120 can determine that the storage expansion device 150 has been connected to the PCIe expansion card 120. When the pin P1 for detecting the connection status has a high level, the PCIe expansion card 120 can determine that the interface DP1_2 has not been connected to any storage expansion device.

When another storage expansion device 150 receives the hardware reset signal R1, the other storage expansion device 150 will perform a hardware reset operation according to the hardware reset signal R1. After the storage expansion device 150 completes the hardware reset operation, the PCIe expansion card 120 can perform a connection operation defined by the PCIe standard with the storage expansion device 150, so that the storage expansion device 150 can obtain a portion of the bus number configured for the interface DP1_2 and a portion of the MMI/O space configured for the interface DP1_2. In more detail, the PCIe switch, PCIe bridge, and PCIe endpoint device in the storage expansion device 150 can be configured with appropriate MMI/O space and bus number.

Afterwards, another storage expansion device 160 can be hot-pluggably connected to the interface DP5_1 of the storage expansion device 150. Similarly, when another storage expansion device 160 is connected to the interface DP5_1 of the storage expansion device 150, the other storage expansion device 160 provides a presence signal NP2 to the storage expansion device 150 through the pin P4 of the upstream interface UP2. Correspondingly, when the storage expansion device 150 receives the presence signal NP2, the storage expansion device 150 sends a hardware reset signal R2 to the other storage expansion device 160 through the pin P5 of the interface DP5_1. Further, the storage expansion device 150 can detect whether the storage expansion device 160 is connected to the interface DP5_1 through the pin P6 of the interface DP5_1. After the storage expansion device 160 completes the hardware reset operation in response to the hardware reset signal R2, the storage expansion device 150 can perform a connection operation defined by the PCIE standard with the storage expansion device 160, and the PCIe switch, PCIe bridge and PCIe endpoint device in the storage expansion device 160 can be configured with appropriate MMI/O space and bus number.

In addition, based on the above description, it can be known that in some embodiments, when another storage expansion device is connected to an interface of one of the N storage expansion devices 110_1-110_N, the other storage expansion device can provide a presence signal to one of the N storage expansion devices 110_1-110_N through a pin of its upstream interface, so that one of the N storage expansion devices 110_1-110_N can send a hardware reset signal to the other storage expansion device through the pin. Then, the other storage expansion device can perform a hardware reset operation according to the hardware reset signal.

FIG. 6 is a flow chart of a resource configuration method of a storage expansion system according to an embodiment of the present invention. In step S602, during the execution of the BIOS, it is determined whether the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot meet the specific identification code specified by the BIOS. In step S604, when the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot meet the secondary vendor identification code and the secondary device identification code specified by the BIOS, the scanning of any PCIe device under the root bridge corresponding to the PCIe slot is stopped during the enumeration process, and the memory mapping I/O resources are configured to the root bridge according to the expansion support quantity. In step S606, the memory mapping I/O resources are allocated to the M interfaces of the PCIe expansion card. However, each step in FIG. 6 has been described in detail as above, and will not be repeated here.

It should be noted that the processing program of the resource allocation method that can be executed by at least one processor is not limited to the above-mentioned embodiments. For example, a part of the above-mentioned steps can be omitted, and the steps can be executed in other orders. In addition, any two or more of the above-mentioned steps can be combined, and a part of the steps can be modified or deleted. Alternatively, other steps can be executed in addition to the above-mentioned steps.

In summary, during the execution of BIOS, the host device will determine whether the PCIe slot is plugged into a PCIe expansion card for connecting a storage expansion device. When the PCIe slot is plugged into this PCIe expansion card, sufficient memory mapping I/O resources and bus resources can be reserved for the root bridge corresponding to the PCIe slot, and the reserved memory mapping I/O resources and bus resources can be distributed downward to the M interfaces of the PCIe expansion card. In this way, regardless of the actual connection timing of the storage expansion device, the storage expansion device directly or indirectly connected to the PCIe expansion card can be configured with appropriate memory mapping I/O resources and bus resources. In this way, the storage expansion device can function normally, and the hot plug event can be avoided so that the storage expansion device cannot obtain sufficient memory mapping I/O resources and bus resources.

In addition, when a storage expansion device is hot-pluggable and connected to the storage expansion system, the storage expansion device can be allowed to perform a hardware reset operation through the presence signal and the hardware reset signal, so that the storage expansion device that has completed the hardware reset operation can be smoothly configured with appropriate memory mapping I/O resources and bus resources. In this way, hot plug events can be avoided from causing system freezes or other adverse results. In addition, the storage expansion system of the embodiment of the present invention can perform different resource configuration operations for general PCIe interface cards and PCIe expansion cards used to connect storage expansion devices without affecting the resource configuration operations of other general PCIe interface cards. In this way, not only can the flexibility of resource configuration be greatly improved, but also high compatibility is achieved.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims (18)

1. A storage expansion system, comprising: N storage expansion devices, where N is an integer greater than 0; a peripheral component interconnect express (PCIe) expansion card having M interfaces and adapted to directly or indirectly connect the N storage expansion devices through the M interfaces, wherein M is an integer greater than 0; and Host equipment, including: PCIe slot; Flash memory for recording BIOS; and A processor is coupled to the PCIe slot and the flash memory, and executes the BIOS to: Determining whether the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot conform to the specific identification code specified by the BIOS; When the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot match the secondary vendor identification code and the secondary device identification code specified by the BIOS, stop scanning any PCIe device under the root bridge corresponding to the PCIe slot during the enumeration process, and configure memory mapping I/O resources for the root bridge according to the expansion support quantity; and The memory-mapped I/O resources are allocated to the M interfaces of the PCIe expansion card. 2. The storage expansion system according to claim 1 is characterized in that the processor evenly distributes the memory mapping I/O resources to the M interfaces of the PCIe expansion card, and each of the M interfaces obtains one-Mth of the memory mapping I/O resources. 3. The storage expansion system of claim 1 , wherein the processor executes the BIOS to: When the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot match the secondary vendor identification code and the secondary device identification code specified by the BIOS, the number of available buses is calculated after the enumeration process is completed; Allocate bus resources to the root bridge according to the available bus quantity and the expansion support quantity; and The bus resources are allocated to the M interfaces of the PCIe expansion card. 4. The storage expansion system according to claim 3, wherein the processor evenly distributes the bus resources to the M interfaces of the PCIe expansion card, and each of the M interfaces obtains one-Mth of the bus resources. 5. The storage expansion system of claim 3, wherein the processor executes the BIOS to: Before allocating the bus resources and the memory-mapped I/O resources to the M interfaces of the PCIe expansion card, clear resource configuration settings on the N storage expansion devices. 6. The storage expansion system of claim 3, wherein when another storage expansion device is hot-pluggably connected to one of the M interfaces during execution of the operating system, the other storage expansion device performs a hardware reset operation, After the hardware reset operation, the other storage expansion device obtains a portion of the bus resources configured for one of the M interfaces and a portion of the memory-mapped I/O resources configured for one of the M interfaces through the operating system. 7. The storage expansion system according to claim 6 is characterized in that when the other storage expansion device is connected to one of the M interfaces, the other storage expansion device provides a presence signal to the PCIe expansion card through a pin, so that the PCIe expansion card sends a hardware reset signal to the other storage expansion device through the pin, and the other storage expansion device performs the hardware reset operation according to the hardware reset signal. 8. The storage expansion system according to claim 6, characterized in that when the other storage expansion device is connected to the interface of one of the N storage expansion devices, the other storage expansion device provides a presence signal to one of the N storage expansion devices through a pin, so that one of the N storage expansion devices sends a hardware reset signal to the other storage expansion device through the pin, and the other storage expansion device performs the hardware reset operation according to the hardware reset signal. 9 . The storage expansion system according to claim 1 , wherein the expansion support quantity is a maximum cascade quantity of the N storage expansion devices. 10. A resource configuration method for a storage expansion system, wherein the storage expansion system comprises a PCIe expansion card, a host device and N storage expansion devices, the PCIe expansion card has M interfaces, the host device has a PCIe slot, and the method comprises: During the execution of the BIOS, determining whether the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot conform to the secondary vendor identification code and the secondary device identification code specified by the BIOS; When the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot match the secondary vendor identification code and the secondary device identification code specified by the BIOS, stop scanning any PCIe device under the root bridge corresponding to the PCIe slot during the enumeration process, and configure memory mapping I/O resources for the root bridge according to the expansion support quantity; and The memory-mapped I/O resources are allocated to the M interfaces of the PCIe expansion card. 11. The resource configuration method of the storage expansion system according to claim 10, wherein the step of allocating the memory mapping I/O resources to the M interfaces of the PCIe expansion card comprises: The memory-mapped I/O resources are evenly distributed to the M interfaces of the PCIe expansion card, wherein each of the M interfaces obtains one-Mth of the memory-mapped I/O resources. 12. The resource configuration method of the storage expansion system according to claim 10, further comprising: When the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot match the secondary vendor identification code and the secondary device identification code specified by the BIOS, the number of available buses is calculated after the enumeration process is completed; Allocate bus resources to the root bridge according to the available bus quantity and the expansion support quantity; and The bus resources are allocated to the M interfaces of the PCIe expansion card. 13. The resource configuration method of the storage expansion system according to claim 12, wherein the step of allocating the bus resources to the M interfaces of the PCIe expansion card according to the number of available buses comprises: The bus resources are evenly distributed to the M interfaces of the PCIe expansion card, wherein each of the M interfaces obtains one-Mth of the bus resources. 14. The resource configuration method of the storage expansion system according to claim 12, further comprising: Before allocating the bus resources and the memory-mapped I/O resources to the M interfaces of the PCIe expansion card, clear resource configuration settings on the N storage expansion devices. 15. The resource configuration method of the storage expansion system according to claim 12, further comprising: When another storage expansion device is hot-pluggably connected to one of the M interfaces during the execution of the operating system, the other storage expansion device performs a hardware reset operation; and After the hardware reset operation, the other storage expansion device obtains a portion of the bus resources configured for one of the M interfaces and a portion of the memory-mapped I/O resources configured for one of the M interfaces. 16. The resource configuration method of the storage expansion system according to claim 15, wherein when the other storage expansion device is hot-pluggably connected to one of the M interfaces during the execution of the operating system, the step of executing the hardware reset operation by the other storage expansion device comprises: When the other storage expansion device is connected to one of the M interfaces, the other storage expansion device provides a presence signal to the PCIe expansion card through a pin, so that the PCIe expansion card sends a hardware reset signal to the other storage expansion device through a pin; and The other storage expansion device performs the hardware reset operation according to the hardware reset signal. 17. The resource configuration method of the storage expansion system according to claim 15, wherein when the other storage expansion device is hot-pluggably connected to one of the M interfaces during the execution of the operating system, the step of executing the hardware reset operation by the other storage expansion device comprises: When the other storage expansion device is connected to the interface of one of the N storage expansion devices, the other storage expansion device provides a presence signal to one of the N storage expansion devices through a pin, so that one of the plurality of storage expansion devices sends a hardware reset signal to the other storage expansion device through a pin; and The other storage expansion device performs the hardware reset operation according to the hardware reset signal. 18. The resource allocation method of the storage expansion system according to claim 10, wherein the expansion support quantity is the maximum serial connection quantity of the N storage expansion devices.