CN118689827A - Storage expansion system and resource allocation method thereof - Google Patents

Abstract

The invention provides a storage expansion system and a resource allocation method thereof. The PCIe expansion card is adapted to directly or indirectly connect to N storage expansion devices through M interfaces. The host device includes a PCIe slot, a flash memory, and a processor. The flash memory is used for recording BIOS. The processor executes the BIOS to: judging whether the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot accord with the specific identification code specified by the BIOS or not; when the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot conform to the secondary manufacturer identification code and the secondary equipment identification code appointed by the BIOS, stopping scanning any PCIe device under the root bridge corresponding to the PCIe slot in the enumeration process, and configuring memory mapping I/O resources to the root bridge according to the expansion support quantity; and M interfaces for allocating memory mapped I/O resources to PCIe expansion cards. Therefore, the problem that the memory expansion device cannot acquire enough memory mapping I/O resources and bus resources due to a hot plug event can be avoided.

Description

Storage expansion system and resource allocation method thereof

Technical Field

The present invention relates to a storage system, and more particularly, to a storage expansion system and a resource allocation method thereof.

Background

Computer systems have various buses for connecting a host processor and other devices and for transferring data to each other. The bus may be used to couple not only the host processor, but also a random access Flash memory (Flash memory) and a main memory (DDR), as well as other external devices. Currently, peripheral component interconnect express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIe) buses are widely used in computer systems on the market today, such as personal computers or servers. PCIe is a newly developed industry bus standard, an improvement over PCI (Peripheral Component Interconnect). The PCIe bus standard is formulated and maintained by the peripheral component interconnect special interest Group (PERIPHERAL COMPONENT INTERCONNECT SPECIAL INTEREST Group, PCI-SIG).

The existing computer system can support one or more PCIe slots, so that users can insert various interface cards into the PCIe slots according to different requirements, and the functions of the computer system are expanded. Currently, in order to enable an interface card plugged into a PCIe slot to function normally, a Basic Input Output System (BIOS) of a computer system needs to perform appropriate configuration on PCIe resources. Under the condition of properly configuring PCIe resources, the operating system of the computer system can effectively communicate with the expansion hardware devices at the rear end of the PCIe slot, so that the functions of the expansion hardware devices can be normally played. On the contrary, when the expansion hardware device at the back end of the PCIe slot is not allocated to the appropriate PCIe resource (for example, the expansion hardware device cannot be allocated to the appropriate PCIe resource due to the hot plug action), the expansion hardware device may not only fail to function normally or reduce the transmission speed, but also may cause the computer system to crash. In particular, when the number of serial connections or the actual connection timing of the expansion hardware devices at the rear end of the PCIe slot is an uncertain factor, the existing BIOS may configure insufficient PCIe resources to the PCIe slot, so that the expansion hardware devices at the rear end of the PCIe slot may not obtain appropriate PCIe resources.

Disclosure of Invention

The embodiment of the invention provides a storage expansion system and a resource allocation method thereof, which can enable storage expansion equipment connected with host equipment through a PCIe expansion card and a PCIe slot to be allocated with proper PCIe resources.

Embodiments of the present invention provide a storage expansion system that includes, but is not limited to, N storage expansion devices, PCIe expansion cards, and host devices. N is an integer greater than 0. The PCIe expansion card has M interfaces and is adapted to directly or indirectly connect to N storage expansion devices through the M interfaces, where M is an integer greater than 0. Host devices include PCIe slots, flash memory, main memory (DDR), and processors. The flash memory is used for recording and storing the BIOS. The processor is coupled with the PCIe slot, the main memory and the flash memory, and executes the BIOS to judge whether the secondary manufacturer identification code and the secondary device identification code of the PCIe expansion card inserted in the PCIe slot conform to the secondary manufacturer identification code and the secondary device identification code specified by the BIOS; when the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot conform to the secondary manufacturer identification code and the secondary equipment identification code specified by the BIOS, stopping scanning any PCIe device under the root bridge corresponding to the PCIe slot in the enumeration (enumeration) process, and configuring Memory-mapped Input/Output (MMI/O) resources to the root bridge according to the expansion support quantity; and M interfaces for allocating memory mapped I/O resources to PCIe expansion cards.

The embodiment of the invention provides a resource allocation method of a storage system, which comprises a PCIe expansion card, a host device and N storage expansion devices. The PCIe expansion card has M interfaces, and the host device has PCIe slots. The resource allocation method of the storage system includes (but is not limited to): during the execution of the BIOS, judging whether the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot conform to the secondary manufacturer identification code and the secondary equipment identification code specified by the BIOS; when the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot accord with the secondary manufacturer identification code and the secondary equipment identification code appointed by the BIOS, stopping scanning any PCIe device under the root bridge corresponding to the PCIe slot in the enumeration process, and configuring memory mapping I/O resources to the root bridge according to the expansion support quantity; and M interfaces for allocating memory mapped I/O resources to PCIe expansion cards.

Based on the above, in the embodiment of the present invention, during the execution of the BIOS, the host device determines whether the PCIe slot is plugged into the PCIe expansion card for connecting to the storage expansion device. When the PCIe slot is plugged into the PCIe expansion card, enough memory mapping I/O resources can be reserved for the root bridge corresponding to the PCIe slot, and the reserved memory mapping I/O resources are downwards distributed to M interfaces of the PCIe expansion card. Therefore, the storage expansion device directly or indirectly connected with the PCIe expansion card can be configured with proper memory mapping I/O resources no matter what the actual connection time of the storage expansion device is, so that the storage expansion device can normally function.

Drawings

FIG. 1 is a schematic diagram of a storage expansion system according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a PCIe expansion card in accordance with one embodiment of the invention;

FIGS. 3A and 3B are flowcharts illustrating a method for allocating resources of a storage expansion system according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a PCIe topology in accordance with one embodiment of the invention;

FIG. 5 is a diagram illustrating the transmission of the present signal and the hardware reset signal according to one embodiment of the present invention;

FIG. 6 is a flow chart of a method for allocating resources of a storage expansion system according to an embodiment of the invention.

Description of the reference numerals

10, A storage expansion system;

110_1 to 110_N,150, 160;

120, PCIe expansion card;

130, a host device;

the interfaces are DP1_1 to DP1_M;

131:PCIe slots;

132, flash memory;

133, a processor;

134, main memory;

B1, a basic input and output system;

S_1 to S_P are storage devices;

121, golden finger;

RB1, root bridge;

DP4_1, DP2_1, DP3_1 and DP5_1, downlink interfaces;

p1 to P6 are pins;

UP 1-UP 2, an uplink interface;

R1, R2 is a hardware reset signal;

NP1, NP2, presence signal;

s302 to S346, S602 to S606.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a block diagram of a memory system according to an embodiment of the invention. Referring to FIG. 1, the storage expansion system 10 includes N storage expansion devices 110_1-110_N, a PCIe expansion card 120, and a host device 130.N is an integer greater than 0.

PCIe expansion card 120 may be implemented as an interface card that includes a PCIe switch. The PCIe expansion card 120 has M interfaces dp1_1 to dp1_m. The PCIe expansion card 120 is adapted to directly or indirectly connect N storage expansion devices 110_1 to 110_n through M interfaces dp1_1 to dp1_m, where M is an integer greater than 0. More specifically, the M interfaces dp1_1 to dp1_m may be downstream interfaces (downstream ports) supporting the PCIe standard. In addition, PCIe expansion card 120 may also include an upstream interface (upstream port) to connect to PCIe slot 131.

For example, FIG. 2 is a schematic diagram of a PCIe expansion card according to an embodiment of the invention. Referring to fig. 2, taking m=2 as an example, the PCIe expansion card 120 may have two interfaces dp1_1 to dp1_2 and a gold finger 121 supporting PCIe standard. The number of PCIe lanes of the golden finger 121 is not limited by the present invention. The golden finger 121 is adapted to be inserted into a PCIe slot 131 of the host device 130. In addition, the interfaces dp1_1 to dp1_2 are used for being directly connected to the corresponding storage expansion devices respectively through cables.

It should be noted that the PCIe expansion card 120 may directly or indirectly connect the N storage expansion devices 110_1 to 110_n. As shown in the example of fig. 1, the storage expansion device 110_1 may be directly connected to the interface dp1_1 of the PCIe expansion card 120. The storage expansion device 110_N may be directly connected to the interface DP1_2 of the PCIe expansion card 120. It should be noted that, in the embodiment of the present invention, the N storage expansion devices 110_1 to 110_n have a function of being connected in series. As shown in the example of FIG. 2, the storage expansion device 110_2 may be connected in series with the storage expansion device 110_1 such that the storage expansion device 110_2 is indirectly connected to the interface DP1_1 of the PCIe expansion card 120. However, the connection of the storage expansion devices 110_1 to 110_n in fig. 1 is merely exemplary, and is not intended to limit the present invention,

In some embodiments, the storage expansion devices 110_1-110_N may be implemented as a cluster (Just aBunch Of Disks, JBOD) device, which may include P storage devices S_1-S_P. P is an integer greater than 0. The storage devices s_1 to s_p are, for example, solid state disks (Solid STATE DRIVE, SSD) or/and hard disks (HARD DISK DRIVE, HDD), which is not limited in the present invention. Each storage expansion device 110_1-110_N may include an upstream interface for connecting a superior device (i.e., PCIe expansion card 120 or other storage expansion device) and supporting the PCIe standard, and a downstream interface for connecting an inferior device (i.e., other storage expansion device) and storage devices S_1-S_P and supporting the PCIe standard. In some embodiments, since each storage expansion device 110_1-110_N may include a downstream interface for connecting to a next-level apparatus (i.e., other storage expansion devices), the storage expansion devices 110_1-110_N may be connected in series with each other via cables. For example, the storage expansion devices 110_1-110_N may support Daisy-chained (Daisy-chain).

Host device 130 includes PCIe slot 131, flash memory 132, processor 133, and main memory 134. In some embodiments, the host device 130 may be implemented as a network attached storage (Network Attached Storage, NAS) device or other type of computer system. An interface card with PCIe gold fingers (e.g., PCIe expansion card or other type of expansion card) may be plugged into PCIe slot 131. The present invention is not limited to the number of PCIe lanes of PCIe slot 131.

The flash memory 132 is used for recording and storing a Basic Input Output System (BIOS) B1. The BIOS B1 is firmware used in the boot process after the host device 130 is booted. In addition, the host device 130 has a main memory 134 (DDR) or other memory element accessible to the processor 133.

The processor 133 is coupled to the PCIe slot 131 and the flash memory 132, and may be a central processing unit (Central Processing Unit, CPU), a general purpose processor, or other similar components or a combination of the above components. The processor 133 may execute the BIOS B1 and the operating system recorded (stored) in the flash memory 132 to implement the resource allocation method according to the embodiment of the present invention.

In some embodiments, during execution of the BIOS, the processor 133 may determine whether the PCIe slot 131 is plugged into the PCIe expansion card 120 for connecting the N storage expansion devices 110_1-110_N. When the PCIe slot 131 is plugged into the PCIe expansion card 120, the processor 133 stops scanning any PCIe devices under the root bridge corresponding to the PCIe slot 131 in the enumeration (enumeration) process, and configures memory mapped I/O resources to the root bridge according to the number of expansion supports.

That is, without scanning the PCIe devices under the root bridge corresponding to PCIe slot 131, processor 133 may reserve sufficient memory mapped I/O resources to the root bridge corresponding to PCIe slot 131 directly according to the expansion support amount. Then, the processor 133 may allocate the memory mapped I/O resources to the M interfaces dp1_1 to dp1_m of the PCIe expansion card 120, so that each of the storage expansion devices 110_1 to 110_n connected to the PCIe expansion card 120 may successfully obtain a portion of the memory mapped I/O resources allocated to the root bridge.

In some embodiments, the memory mapped I/O resources may be memory mapped input/output (MMI/O) space. In addition, in addition to memory mapped I/O resources, the processor 133 may pre-allocate enough bus resources to the root bridge corresponding to the PCIe slot 131, so that each storage expansion device 110_1 to 110_n connected to the PCIe expansion card 120 may successfully obtain a portion of the bus resources allocated to the root bridge. Examples will be set forth below for clarity.

Fig. 3A and 3B are flowcharts illustrating a method for allocating resources in a storage expansion system according to an embodiment of the invention. Referring to fig. 3A and 3B, the method of the present embodiment may be performed by the storage expansion system 10 of fig. 1, and details of each step of fig. 3A and 3B are described below with reference to the elements shown in fig. 1.

In step S302, the host device 130 is powered on (power on), and the processor 133 starts to execute the BIOS B1. In step S304, the processor 133 starts to execute the PCI bus driver (PCI bus driver) in the BIOS B1. In step S306, the processor 133 checks PCIe devices of the plurality of root bridge backend in the enumeration process. These root bridges include root bridges corresponding to PCIe slots 131. The enumeration process of PCIe is used to build PCIe topology and configure PCIe resources (i.e., MMI/O space or bus numbers) to PCIe devices. Here, PCIe devices may include PCIe endpoint devices, PCIe bridges or PCIe switches, and the like.

In step S308, the processor 133 determines whether the secondary vendor identification code and the secondary device identification code of the PCIe expansion card 120 plugged into the PCIe slot 131 conform to the secondary vendor identification code and the secondary device identification code specified by the BIOS B1. In detail, the processor 133 can determine whether the secondary vendor identifier (Subsystem Identification, SSID) and/or the secondary device identifier (Subsystem Vendor Identification, SVID) in the register (STANDARD REGISTERS of PCI Configuration SPACE HEADER) of the PCIe expansion card 120 match the specific identifier set by the BIOS, so as to determine whether the PCIe slot 131 is plugged into the PCIe expansion card 120 adapted to connect to the N storage expansion devices 110_1-110_n. In other words, the processor 133 not only determines whether an interface card is inserted into the PCIe slot 131, but also determines the type of the interface card inserted into the PCIe slot 131 through the secondary vendor identification code and the secondary device identification code. Any interface card supporting PCIe, including PCIe expansion card 120, may be plugged into PCIe slot 131.

If step S308 determines that the determination in step S310 is yes, when the secondary vendor identifier and the secondary device identifier of the PCIe expansion card 120 plugged in the PCIe slot 131 conform to the secondary vendor identifier and the secondary device identifier specified by the BIOS B1, the processor 133 stops scanning any PCIe devices under the root bridge corresponding to the PCIe slot 131 in the enumeration process, and configures memory mapping I/O resources to the root bridge corresponding to the PCIe slot 131 according to the expansion support number. That is, when the PCIe slot 131 is plugged with the PCIe expansion card 120 for connecting to the N storage expansion devices 110_1 to 110_n, the processor 133 does not scan down any PCIe devices serially connected to the back end of the PCIe slot 131, but may reserve a root bridge corresponding to directly configuring memory mapping I/O resources to the PCIe slot 131.

In step S312, the processor 133 writes the address range of the MMI/O space into the register of the root bridge corresponding to the PCIe slot 131. Detailed operations regarding writing address ranges of MMI/O space to registers of a root bridge have been specified in the PCIe standard. Specifically, the processor 133 may write the starting address of the MMI/O space to the memory base register (memory base register) in the configuration space of the root bridge corresponding to the PCIe slot 131 and may write the ending address of the MMI/O space to the memory limit register (memory LIMIT REGISTER) in the configuration space of the root bridge corresponding to the PCIe slot 131.

To facilitate understanding of the concepts of the present invention, please refer to fig. 4, which is a schematic diagram of a PCIe topology according to an embodiment of the present invention. In the example of fig. 4, in order to make the concept of the present invention easier to understand, m=2 and n=2 are taken as examples, but the present invention is not limited thereto.

The PCIe slot 131 corresponds to the root bridge RB1, and this root bridge RB1 is connected to the downstream interface dp4_1 of the PCIe slot 131. PCIe slot 131 connects to PCIe expansion card 120 via downstream interface dp4_1. The storage expansion devices 110_1 and 110_2 are connected in series to the back end of the PCIe expansion card 120. The storage expansion device 110_2 may be connected in series to the downstream interface DP2_1 of the storage expansion device 110_1 and indirectly connected to the interface DP1_1 of the PCIe expansion card 120. Similarly, the storage expansion device 110_2 also has a downstream interface dp3_1 for connecting to other storage expansion devices. In the enumeration process, when the processor 133 finds that the PCIe expansion card 120 is plugged into the PCIe slot 131, the processor 133 will stop continuing to scan down other PCIe devices at the back end of the PCIe slot 131, without following the depth-first order. That is, the processor 133 does not scan down the PCIe expansion card 120 and the storage expansion devices 110_1, 110_2. Also, the processor 133 may configure sufficient MMI/O space for the root bridge RB1 based on the number of expansion supports.

In some embodiments, the number of expansion supports is the maximum number of concatenations of the N storage expansion devices 110_1-110_N. That is, the maximum number of concatenations represents that the PCIe expansion card 120 can concatenate at most several storage expansion devices. The maximum number of the series connection may be a preset number, which may be designed according to actual requirements, which is not limited in the present invention. For example, assuming that the PCIe expansion card 120 can be designed to concatenate up to 16 storage expansion devices 110_1-110_16, the expansion support number is 16. In this case, the processor 133 may configure enough 16 memory mapped I/O resources used by the storage expansion devices 110_1-110_16 to the corresponding root bridge of the PCIe slot 131. For example, assuming a memory expansion device requires MMI/O space for A bytes, the processor 133 may configure at least 16 MMI/O spaces for A bytes to the corresponding root bridge RB1 of the PCIe slot 131. The processor 133 may record 16 x abyte MMI/O space in the memory base register (memory base register) and memory constraint register (memory LIMIT REGISTER) in the configuration space of the root bridge RB1.

On the other hand, if the determination in step S308 is negative, in step S316, the processor 133 scans all PCIe devices at the back end of the root bridge and calculates MMI/O space and bus resources required by the root bridge. That is, when the PCIe slot 131 is a socket for another interface card, the processor 133 may scan all PCIe devices at the back end of the root bridge in depth-first order and calculate MMI/O space and bus resources required by all PCIe devices at the back end of the root bridge.

In step S318, the processor 133 writes the bus resources required by the root bridge into the registers of the root bridge. Detailed operations regarding writing bus resources to registers of a root bridge have been specified in the PCIe standard. Specifically, the processor 133 may write the bus resources required by the root bridge to the subordinate bus number register (Subordinate bus number register) and the secondary bus number register (Secondary bus number register) in the configuration space of the root bridge. Thereafter, in step S320, the processor 133 writes the address range of the MMI/O space into the register of the root bridge. In step S322, the processor 133 writes the address range of the MMI/O space to the registers of the other interface cards. Specifically, the processor 133 may write the address range of the MMI/O space to the Base register (Base ADDRESS REGISTER, BAR) of the other interface card.

It is understood that steps S316 to S322 are steps performed for other interface cards, and the more detailed operation contents thereof can refer to PCIe standard. It should be noted that steps S310 to S312 are steps performed for the PCIe expansion card 120 configured to connect multiple storage expansion devices in series.

Then, in step S314, the processor 133 determines whether the last PCIe device is enumerated. If the determination in step S314 is negative, the process returns to step S306, and the processor 133 continues to scan the next root bridge. If yes in step S314, in step S324, the processor 133 ends executing the PCI bus driver in the BIOS B1. In step S326, the processor 133 starts to execute the storage expansion device driver in the BIOS B1.

Next, referring to fig. 3B, in step S328, the processor 133 determines whether the secondary vendor identification code and the secondary device identification code of the PCIe expansion card 120 plugged in the PCIe slot 131 conform to the secondary vendor identification code and the secondary device identification code specified by the BIOS B1. If step S328 determines no, in step S330, the processor 133 ends executing the storage expansion device driver in the BIOS B1. In step S332, the processor 133 starts the operating system.

On the other hand, if step S328 determines that it is yes, in step S334, the processor 133 collects information about the root bridge corresponding to the PCIe slot 131. In step S336, when the PCIe slot 131 is plugged into the PCIe expansion card 120, the processor 133 calculates an available bus number after the enumeration process is completed. In other words, after the enumeration process is completed, the processor 133 may calculate the remaining available number of buses and bus numbers. Up to 256 buses are supported based on the PCIe standard, the maximum number of buses is 256, which may correspond to bus numbers "0" to "255", respectively. Assuming that j buses have been used after the enumeration process is complete, 256-j root bridges remain that can be configured for the corresponding PCIe slot 131.

In step S338, the processor 133 may clear the resource configuration settings on the N storage expansion devices 110_1-110_N before allocating bus resources and memory mapped I/O resources to the M interfaces of the PCIe expansion card. Further, to ensure that the correct resource configuration settings can be written into the configuration space of the N storage expansion devices 110_1-110_n, the processor 133 may first clear the resource configuration settings in the configuration space of the N storage expansion devices 110_1-110_n. For example, the processor 133 may first clear the recorded values of the Base address registers (Base ADDRESS REGISTER, BAR) in the configuration space of the N storage expansion devices 110_1-110_n.

In step S340, the processor 133 configures bus resources to the root bridge corresponding to the PCIe expansion card 120 according to the available bus number and the expansion support number, and allocates the bus resources to the M interfaces dp1_1 to dp1_m of the PCIe expansion card 120. As before, the expansion support number may be the maximum number of concatenations of the N storage expansion devices 110_1-110_N. For example, assuming that a storage expansion device requires B bus numbers and the number of expansion support is 16, the processor 133 may configure at least 16×b bus numbers to the root bridge corresponding to the PCIe slot 131. As a result, even if no storage expansion device is connected in series behind the PCIe expansion card 120, the processor 133 still configures the memory mapped I/O resources and bus resources to the corresponding root bridge of the PCIe expansion card 120 according to the expansion support amount. Then, the processor 133 allocates the bus resources allocated to the root bridge corresponding to the PCIe expansion card 120 to the M interfaces dp1_1 to dp1_m of the PCIe expansion card 120. Then, in step S342, the processor 133 allocates the MMI/O space allocated to the root bridge corresponding to the PCIe expansion card 120 to the M interfaces dp1_1 to dp1_m of the PCIe expansion card 120.

In some embodiments, processor 133 may allocate memory mapped I/O resources to M interfaces DP1_1-DP1_M of PCIe expansion card 120 on average, where each of the M interfaces DP1_1-DP1_M obtains one-M-th of the memory mapped I/O resources. In addition, the processor 133 may allocate bus resources to M interfaces DP1_1-DP1_M of the PCIe expansion card 120 on average, wherein each of the M interfaces DP1_1-DP1_M obtains one-M of the bus resources. For example, assuming that the processor 133 configures 16×b bus numbers and 16×a bytes of MMI/O space for the root bridge corresponding to the PCIe expansion card 120, the processor 133 may allocate 16×b/M bus numbers and 16×a/M bytes of MMI/O space for each of the interfaces dp1_1 to dp1_m. Alternatively, in other embodiments, the processor 133 may allocate bus resources and memory mapped I/O resources unevenly to the M interfaces DP1_1-DP1_M of the PCIe expansion card 120. That is, the number of bus resources and memory mapped I/O resources acquired by each interface DP1_1 through DP1_M may be different.

For easier understanding of the inventive concept, please refer to fig. 4 again. After the processor 133 directly allocates MMI/O space and bus resources to the root bridge RB1 according to the expansion support amount, the processor 133 may allocate MMI/O space and bus resources allocated to the root bridge RB1 to the interfaces dp1_1, dp1_2. The processor 133 may symmetrically allocate MMI/O space and bus resources to the interfaces dp1_1, dp1_2 such that the interfaces dp1_1, dp1_2 are configured with the same MMI/O space and bus resources. For example, assuming that the processor 133 directly configures the MMI/O space of X byte and Y bus numbers to the root bridge RB1, the interfaces DP1_1 and DP1_2 can obtain the MMI/O space of X/2byte and Y/2 bus numbers, respectively. Alternatively, the processor 133 may asymmetrically allocate MMI/O space and bus resources to the interfaces DP1_1, DP1_2 such that the interfaces DP1_1, DP1_2 are configured with differing MMI/O space and bus resources. For example, assuming that the processor 133 directly configures the MMI/O space of X byte and Y bus numbers to the root bridge RB1, the interface DP1_1 may acquire the MMI/O space of k byte and q bus numbers, and the interface DP1_1 may acquire the MMI/O space of (X-k) byte and (Y-q) bus numbers.

Then, in step S344, the processor 133 ends executing the storage expansion device driver in the BIOS B1. In step S346, the processor 133 starts the operating system OS. After the operating system is started, the processor 133 executes the OS instruction to allocate the memory mapped I/O resources and bus resources acquired by the interfaces dp1_1 to dp1_m to the storage expansion devices 110_1 to 110_n. For example, referring back to FIG. 4, after the OS is started, the processor 133 executes OS instructions to allocate MMI/O space and bus numbers acquired by the interface DP1_1 to the storage expansion devices 110_1, 110_2.

It should be noted that, the processor 133 executes the BIOS instruction to pre-allocate enough memory mapped I/O resources and bus resources to the root bridge corresponding to the PCIe slot 131, and allocates the memory mapped I/O resources and bus resources allocated to the root bridge corresponding to the PCIe slot 131 to the M interfaces dp1_1 to dp1_m. Therefore, if another storage expansion device is connected to one of the M interfaces dp1_1 to dp1_m in a hot-pluggable manner after the operating system is started, the other storage expansion device can still be successfully configured to the memory mapped I/O resources and the bus resources through the operating system.

It should be noted that in some embodiments, when another storage expansion device is hot-pluggable to one of the M interfaces dp1_1 to dp1_m during execution of the operating system, the other storage expansion device may perform a hardware reset operation. After the hardware reset operation, another storage expansion device operating system acquires a portion of the bus resources allocated to one of the M interfaces dp1_1 to dp1_m and a portion of the memory mapped I/O resources allocated to one of the M interfaces dp1_1 to dp1_m. Specifically, after the other storage expansion device performs the hardware reset operation, the processor 133 executes the OS instruction to allocate the memory mapped I/O resource and the bus resource configured by one of the interfaces dp1_1 to dp1_m connected to the other storage expansion device.

FIG. 5 is a diagram illustrating the transmission of the present signal and the hardware reset signal according to one embodiment of the present invention. Referring to FIG. 5, after the operating system is started, the processor 133 has allocated memory mapped I/O resources and bus resources to all of the interfaces DP1_1 through DP1_M. After the operating system is started, another storage expansion device 150 is hot-pluggable connected to interface dp1_2 of PCIe expansion card 120.

When the other storage expansion device 150 is connected to one of the M interfaces dp1_1 to dp1_m (e.g., the interface dp1_2 shown in the example of fig. 5), the other storage expansion device 150 provides the presence signal NP1 to the PCIe expansion card 120 through the Pin (Pin) P3 of the UP interface UP1, so that the PCIe expansion card 120 sends the hardware reset signal R1 to the other storage expansion device 150 through the Pin P2 of the interface dp1_2. Further, the PCIe expansion card 120 may detect whether the storage expansion device 150 is connected to the interface dp1_2 through the pin P1 of the interface dp1_2. In some embodiments, when pin P1 for detecting the connection status has a low level, the PCIe expansion card 120 may determine that the storage expansion device 150 is already connected to the PCIe expansion card 120. When pin P1 for detecting the connection status has a high level, PCIe expansion card 120 may determine that interface DP1_2 is not yet connected to any storage expansion device.

When the other storage expansion device 150 receives the hardware reset signal R1, the other storage expansion device 150 performs a hardware reset operation according to the hardware reset signal R1. After the storage expansion device 150 completes the hardware reset operation, the PCIe expansion card 120 may perform a PCIe standard defined connection action with the storage expansion device 150, so that the storage expansion device 150 may obtain a portion of the bus number configured to the interface dp1_2 and a portion of the MMI/O space configured to the interface dp1_2. In more detail, the PCIe switches, PCIe bridges, and PCIe endpoint devices within the storage expansion device 150 may be configured with appropriate MMI/O space and bus numbers.

Thereafter, another storage expansion device 160 may be hot-swappably connected in series to the interface dp5_1 of the storage expansion device 150. Similarly, when the other storage expansion device 160 is connected to the interface dp5_1 of the storage expansion device 150, the other storage expansion device 160 provides the presence signal NP2 to the storage expansion device 150 through the pin P4 of the UP interface UP 2. Correspondingly, when the storage expansion device 150 receives the presence signal NP2, the storage expansion device 150 sends a hardware reset signal R2 to the other storage expansion device 160 through the pin P5 of the interface dp5_1. Further, the storage expansion device 150 can detect whether the storage expansion device 160 is connected to the interface dp5_1 through the pin P6 of the interface dp5_1. After the storage expansion device 160 completes the hardware reset operation in response to the hardware reset signal R2, the storage expansion device 150 may perform a connection operation defined by PCIE standard with the storage expansion device 160, and the PCIE switch, PCIE bridge, and PCIE endpoint device in the storage expansion device 160 may be configured with appropriate MMI/O space and bus numbers.

In addition, as can be seen from the above description, in some embodiments, when another storage expansion device is connected to the interface of one of the N storage expansion devices 110_1 to 110_n, the other storage expansion device can provide the presence signal to one of the N storage expansion devices 110_1 to 110_n through a pin of the upstream interface thereof, so that one of the N storage expansion devices 110_1 to 110_n can send the hardware reset signal to the other storage expansion device through the pin. Thus, another storage expansion device can execute the hardware reset operation according to the hardware reset signal.

FIG. 6 is a flow chart of a method for allocating resources of a storage expansion system according to an embodiment of the invention. In step S602, during the execution of the BIOS, it is determined whether the secondary vendor identification code and the secondary device identification code of the PCIe expansion card plugged into the PCIe slot conform to the specific identification code specified by the BIOS. In step S604, when the secondary vendor identifier and the secondary device identifier of the PCIe expansion card plugged in the PCIe slot conform to the secondary vendor identifier and the secondary device identifier specified by the BIOS, scanning of any PCIe devices under the root bridge corresponding to the PCIe slot is stopped in the enumeration process, and memory mapped I/O resources are allocated to the root bridge according to the number of expansion supports. In step S606, memory mapped I/O resources are allocated to M interfaces of the PCIe expansion card. However, the steps in fig. 6 are described in detail above, and will not be described again here.

The processing procedure of the resource allocation method executable by the at least one processor is not limited to the above embodiment. For example, some of the above steps may be omitted, or the steps may be performed in other orders. Any two or more of the above steps may be combined, and a part of the steps may be modified or deleted. Or other steps may be performed in addition to the above steps.

In summary, during the execution of the BIOS, the host device determines whether the PCIe slot is plugged into the PCIe expansion card for connecting to the storage expansion device. When the PCIe slot is plugged into the PCIe expansion card, enough memory mapped I/O resources and bus resources can be reserved for the root bridge corresponding to the PCIe slot, and the reserved memory mapped I/O resources and bus resources are downwards distributed to M interfaces of the PCIe expansion card. Therefore, the storage expansion device directly or indirectly connected with the PCIe expansion card can be configured with proper memory mapping I/O resources and bus resources regardless of the actual connection time of the storage expansion device. Therefore, the storage expansion device can normally function, and the problem that the storage expansion device cannot acquire enough memory mapping I/O resources and bus resources due to a hot plug event can be avoided.

In addition, when the storage expansion device is connected to the storage expansion system in a hot-pluggable manner, the storage expansion device can carry out hardware reset operation through the presence signal and the hardware reset signal, so that the storage expansion device which completes the hardware reset operation can be smoothly configured with proper memory mapping I/O resources and bus resources. Therefore, the system is prevented from being halted or other bad results caused by the hot plug event. In addition, the storage expansion system of the embodiment of the invention can carry out different resource configuration operations on the common PCIe interface card and the PCIe expansion card used for connecting the storage expansion device, and the resource configuration operations of other common PCIe interface cards are not influenced. Therefore, the flexibility of resource allocation can be greatly improved, and the method has high compatibility.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (18)

1. A storage expansion system, comprising:

N storage expansion devices, wherein N is an integer greater than 0;

A peripheral component interconnect express (PCIe) expansion card having M interfaces and adapted to directly or indirectly connect the N storage expansion devices through the M interfaces, wherein M is an integer greater than 0; and

A host device, comprising:

PCIe slots;

Flash memory for recording BIOS; and

A processor, coupled to the PCIe slot and the flash memory, executing the BIOS to:

Judging whether the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot conform to the specific identification code specified by the BIOS or not;

When the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot conform to the secondary manufacturer identification code and the secondary equipment identification code appointed by the BIOS, stopping scanning any PCIe device under a root bridge corresponding to the PCIe slot in the enumeration process, and configuring memory mapping I/O resources to the root bridge according to the expansion support quantity; and

The memory mapped I/O resources are allocated to the M interfaces of the PCIe expansion card.

2. The storage expansion system of claim 1, wherein the processor allocates the memory mapped I/O resources to the M interfaces of the PCIe expansion card on average, each of the M interfaces taking one-M-th of the memory mapped I/O resources.

3. The storage expansion system of claim 1, wherein the processor executes the BIOS to:

when the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot conform to the secondary manufacturer identification code and the secondary equipment identification code specified by the BIOS, calculating the number of available buses after the enumeration process is finished;

configuring bus resources to the root bridge according to the available bus quantity and the expansion support quantity; and

And distributing the bus resources to the M interfaces of the PCIe expansion card.

4. The storage expansion system of claim 3, wherein said processor allocates said bus resources to said M interfaces of said PCIe expansion card on average, each of said M interfaces taking one-M-th of said bus resources.

5. The storage expansion system of claim 3, wherein the processor executes the BIOS to:

And clearing the resource configuration settings on the N storage expansion devices before allocating the bus resources and the memory mapped I/O resources to the M interfaces of the PCIe expansion card.

6. The storage expansion system of claim 3, wherein when another storage expansion device is hot-pluggable to one of said M interfaces during execution of the operating system, said another storage expansion device performs a hardware reset operation,

After the hardware reset operation, the other storage expansion device obtains a part of the bus resources allocated to one of the M interfaces and a part of the memory mapped I/O resources allocated to one of the M interfaces through the operating system.

7. The system of claim 6, wherein when the other storage expansion device is connected to one of the M interfaces, the other storage expansion device provides a presence signal to the PCIe expansion card via a pin to enable the PCIe expansion card to send a hardware reset signal to the other storage expansion device via the pin, the other storage expansion device performing the hardware reset operation according to the hardware reset signal.

8. The storage expansion system of claim 6, wherein when the other storage expansion device is connected to the interface of one of the N storage expansion devices, the other storage expansion device provides a presence signal to the one of the N storage expansion devices via a pin, so that the one of the N storage expansion devices sends a hardware reset signal to the other storage expansion device via the pin, and the other storage expansion device performs the hardware reset operation according to the hardware reset signal.

9. The storage expansion system of claim 1, wherein the expansion support number is a maximum number of concatenations of the N storage expansion devices.

10. A method for configuring resources of a storage expansion system, wherein the storage expansion system comprises a PCIe expansion card, a host device and N storage expansion devices, the PCIe expansion card has M interfaces, the host device has a PCIe slot, and the method comprises:

During the execution of the BIOS, judging whether the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot conform to the secondary manufacturer identification code and the secondary equipment identification code appointed by the BIOS;

When the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot conform to the secondary manufacturer identification code and the secondary equipment identification code appointed by the BIOS, stopping scanning any PCIe device under a root bridge corresponding to the PCIe slot in the enumeration process, and configuring memory mapping I/O resources to the root bridge according to the expansion support quantity; and

The memory mapped I/O resources are allocated to the M interfaces of the PCIe expansion card.

11. The method of claim 10, wherein the step of allocating the memory mapped I/O resources to the M interfaces of the PCIe expansion card comprises:

And averagely distributing the memory mapping I/O resources to the M interfaces of the PCIe expansion card, wherein each M interface obtains one M-half of the memory mapping I/O resources.

12. The method of resource allocation for a storage expansion system of claim 10, further comprising:

when the secondary manufacturer identification code and the secondary equipment identification code of the PCIe expansion card inserted in the PCIe slot conform to the secondary manufacturer identification code and the secondary equipment identification code specified by the BIOS, calculating the number of available buses after the enumeration process is finished;

configuring bus resources to the root bridge according to the available bus quantity and the expansion support quantity; and

And distributing the bus resources to the M interfaces of the PCIe expansion card.

13. The method of claim 12, wherein allocating the bus resources to the M interfaces of the PCIe expansion card according to the number of available buses comprises:

And averagely distributing the bus resources to the M interfaces of the PCIe expansion card, wherein each M interface acquires one-M of the bus resources.

14. The method of resource allocation for a storage expansion system of claim 12, further comprising:

And clearing the resource configuration settings on the N storage expansion devices before allocating the bus resources and the memory mapped I/O resources to the M interfaces of the PCIe expansion card.

15. The method of resource allocation for a storage expansion system of claim 12, further comprising:

Executing a hardware reset operation by another storage expansion device when the other storage expansion device is hot-pluggable connected to one of the M interfaces during execution of the operating system; and

After the hardware reset operation, a portion of the bus resources allocated to one of the M interfaces and a portion of the memory mapped I/O resources allocated to one of the M interfaces are acquired by the other memory expansion device.

16. The method of claim 15, wherein the step of performing the hardware reset operation by the another storage expansion device when the another storage expansion device is hot-pluggable connected to one of the M interfaces during execution of the operating system comprises:

When the other storage expansion device is connected to one of the M interfaces, the other storage expansion device provides a presence signal to the PCIe expansion card through a pin so that the PCIe expansion card sends a hardware reset signal to the other storage expansion device through the pin; and

And executing the hardware reset operation by the other storage expansion device according to the hardware reset signal.

17. The method of claim 15, wherein the step of performing the hardware reset operation by the another storage expansion device when the another storage expansion device is hot-pluggable connected to one of the M interfaces during execution of the operating system comprises:

when the other storage expansion device is connected to the interface of one of the N storage expansion devices, the other storage expansion device provides a presence signal to the one of the N storage expansion devices through a pin so that the one of the plurality of storage expansion devices sends a hardware reset signal to the other storage expansion device through the pin; and

And executing the hardware reset operation by the other storage expansion device according to the hardware reset signal.

18. The resource allocation method of the storage expansion system according to claim 10, wherein the expansion support number is a maximum concatenation number of the N storage expansion devices.