CN118645475B

CN118645475B - Method for forming semiconductor device

Info

Publication number: CN118645475B
Application number: CN202411127334.5A
Authority: CN
Inventors: 郭帅
Original assignee: Shenzhen Shengweixu Technology Co ltd
Current assignee: Shenzhen Shengweixu Technology Co ltd
Priority date: 2024-08-16
Filing date: 2024-08-16
Publication date: 2024-10-29
Anticipated expiration: 2044-08-16
Also published as: CN118645475A

Abstract

The disclosure provides a method for forming a semiconductor device, and relates to the technical field of semiconductors. The forming method comprises the following steps: providing an initial semiconductor structure comprising a substrate, wherein the substrate comprises a first region and a second region, the first region is formed with a P-type transistor, the second region is formed with an N-type transistor, the P-type transistor comprises a first grid electrode, a first source electrode and a first drain electrode, and the N-type transistor comprises a second grid electrode, a second source electrode and a second drain electrode; forming a first metal silicide layer on top of the first grid electrode, the first source electrode, the first drain electrode, the second grid electrode, the second source electrode and the second drain electrode respectively; and forming a stress layer which covers the surface of the initial semiconductor structure with the first metal silicide layer in a conformal manner, wherein the stress layer comprises silicon element and nitrogen element, and the ratio of the silicon element to the nitrogen element is greater than 3:4. By forming a stress layer with higher silicon content in the device, the stress in the P-type transistor and the N-type transistor can be balanced, and the resistance of the metal silicide layer in the device can be reduced.

Description

Method for forming semiconductor device

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor device.

Background

In the field of Semiconductor devices, as the characteristic line width of an integrated circuit is reduced below the nanometer level, the acting force between the internal film layers of the device is also changed, especially in the manufacturing process of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor, complementary Metal Oxide Semiconductor) device, after forming a Metal silicide, a layer of CESL (Contact Etch Stop Layer, via etching stop layer) film layer is formed on a silicon wafer, and the film layer can exert a stress effect on the device structure below the film layer, and the stress can change the crystal lattice so as to influence the mobility of carriers in the device, so that the influence of the stress generated by the same film layer on the carrier mobility of a PMOS (Positive-channel-Metal-Oxide-Semiconductor) device and an NMOS (N-Metal-Oxide-Semiconductor) device is different.

In a CMOS device, the formation of metal silicide is affected by not only temperature but also stress generated by a stress film, and under the action of different stresses, the phase transition temperatures of the atomic structures in the metal silicide are different, so that in the same CMOS device, the temperatures of the P-type transistor and the N-type transistor for completing the phase transition are different, and under the temperature condition that part of the metal silicide is in phase transition, the other part of the metal silicide has agglomeration defects, so that the manufacturing defects of the device are caused, and the yield of the device is further affected.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

In view of the above, a method for forming a semiconductor device is provided, which can balance stress on an N-type transistor and a P-type transistor by simultaneously covering a stress layer with a higher silicon element content on the N-type transistor and the P-type transistor, and can reduce the resistance of a metal silicide layer, thereby improving the performance and reliability of the device.

Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.

According to an aspect of the present disclosure, there is provided a method of forming a semiconductor device, the method comprising:

Providing an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate, the substrate comprises a first region and a second region, a P-type transistor is formed in the first region, an N-type transistor is formed in the second region, the P-type transistor comprises a first grid, a first source electrode and a first drain electrode which are positioned on two sides of the first grid, and the N-type transistor comprises a second grid, a second source electrode and a second drain electrode which are positioned on two sides of the second grid;

forming first metal silicide layers on top of the first grid electrode, the first source electrode, the first drain electrode, the second grid electrode, the second source electrode and the second drain electrode respectively;

And forming a stress layer which covers the surface of the initial semiconductor structure with the first metal silicide layer in a conformal manner to form a target semiconductor structure, wherein the stress layer comprises silicon element and nitrogen element, and the ratio between the silicon element and the nitrogen element is larger than 3:4.

In an exemplary embodiment of the present disclosure, the method further comprises:

performing first heat treatment on the target semiconductor structure to diffuse silicon element in the stress layer into the first metal silicide layer to form a second metal silicide layer;

wherein the resistivity of the second metal silicide layer is smaller than the resistivity of the first metal silicide layer.

In an exemplary embodiment of the disclosure, the first heat treatment includes a laser annealing treatment, a temperature of the first heat treatment is greater than 700 ℃, and a time of the first heat treatment is 10 ns-100 ms.

In one exemplary embodiment of the present disclosure, the forming a first metal silicide layer includes:

forming a metal layer which is conformal and covers the surface of the initial semiconductor structure;

Performing a second heat treatment on the initial semiconductor structure with the metal layer to diffuse metal ions in the metal layer into the N-type transistor and the P-type transistor;

And removing the residual metal layer.

In an exemplary embodiment of the present disclosure, the temperature of the second heat treatment is less than 750 ℃.

In an exemplary embodiment of the present disclosure, after the forming of the metal layer, the method further includes:

and forming a barrier layer which is conformal to cover the surface of the metal layer.

and forming an isolation structure in the substrate, wherein the isolation structure is used for isolating the P-type transistor and the N-type transistor.

In an exemplary embodiment of the present disclosure, before forming the metal layer, the method further includes:

forming a passivation layer which covers the surface of the initial semiconductor structure in a conformal manner;

Forming a photoresist layer on the passivation layer;

and etching the passivation layer by taking the photoresist layer as a mask to form a sub-passivation layer, wherein the sub-passivation layer covers the surface of the isolation structure.

In an exemplary embodiment of the present disclosure, after the forming of the second metal silicide layer, the method further includes:

An insulating layer is formed that covers the target semiconductor structure and fills a gap between the P-type transistor and the N-type transistor.

In an exemplary embodiment of the present disclosure, a ratio between the silicon element and the nitrogen element in the stress layer is 7:8 to 15:8.

In one exemplary embodiment of the present disclosure, the stress layer is formed using a plasma enhanced chemical vapor deposition method, a chemical vapor deposition method, or an atomic layer deposition method.

In one exemplary embodiment of the present disclosure, the precursors forming the stress layer include silane and ammonia; or precursors for forming the stress layer include silane and nitrogen.

According to the method for forming the semiconductor device, the first metal silicide layer is formed on the N-type transistor and the P-type transistor, the stress layer is formed on the first metal silicide layer, the proportion between silicon elements and nitrogen elements in the stress layer is larger than 3:4, so that the silicon content in the stress layer is higher, on one hand, the stress in the P-type transistor and the N-type transistor can be balanced through the stress layer, and on the other hand, the phase transition temperature of the metal silicide in the P-type transistor and the metal silicide in the N-type transistor can be balanced due to the fact that the silicon content in the stress layer is higher, the uniform metal silicide layer with smaller resistivity is formed, the formation of agglomeration defects is avoided, and the yield of the device is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a flowchart of a method of forming a semiconductor device in an exemplary embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of an initial semiconductor structure in an exemplary embodiment of the present disclosure.

Fig. 3 is a schematic structural view of an initial semiconductor structure with a passivation layer in an exemplary embodiment of the present disclosure.

Fig. 4 is a schematic structural view of an initial semiconductor structure with a sub-passivation layer in an exemplary embodiment of the present disclosure.

Fig. 5 is a schematic view of a device structure for forming a metal layer in an exemplary embodiment of the present disclosure.

Fig. 6 is a schematic view of a device structure for forming a barrier layer in an exemplary embodiment of the present disclosure.

Fig. 7 is a schematic view of a device structure for forming a first metal silicide layer in an exemplary embodiment of the present disclosure.

Fig. 8 is a schematic structural diagram of a target semiconductor structure in an exemplary embodiment of the present disclosure.

Fig. 9 is a schematic view of a device structure for forming a second metal silicide layer in an exemplary embodiment of the present disclosure.

Fig. 10 is a schematic view of a device structure for forming an insulating layer in an exemplary embodiment of the present disclosure.

Wherein reference numerals are as follows:

100. A substrate; 210. an N-type transistor; 211. a second gate; 11. a second gate oxide layer; 12. a second gate layer; 13. a second gate protection layer; 131. an insulating material layer; 132. a dielectric layer; 212. a second source electrode; 213. a second drain electrode; 220. a P-type transistor; 221. a first gate; 21. a first gate oxide layer; 22. a first gate layer; 23. a first gate protection layer; 222. a first source electrode; 223. a first drain electrode; 310. a first metal silicide layer; 320. a second metal silicide layer; 330. a metal layer; 400. a stress layer; 500. a barrier layer; 600. a passivation layer; 610. a photoresist layer; 601. a sub-passivation layer; 700. an insulating layer; 1000. an isolation structure; A. a first region; B. a second region.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.

In the related art, CMOS devices are widely used in modern microelectronics as an integrated circuit technology, particularly in microprocessors, memories and other digital logic circuits, which combine N-type metal-oxide-semiconductor (NMOS) transistors and P-type metal-oxide-semiconductor (PMOS) transistors. The CMOS device has the characteristics of low power consumption, high performance and the like.

With the continuous progress of semiconductor technology, the size of CMOS devices is continuously reduced, and higher requirements are put on the CMOS process. At present, in order to reduce the problems of short channel effect and the like caused by the miniaturization of the size of a device, a metal silicide layer is generally arranged on the surface of the device, and silicon ions in the device can be diffused into the formed metal silicide layer through a further heat treatment process to form a metal silicide layer with smaller resistivity so as to reduce the contact resistance of the device.

After the metal silicide layer is formed, a CESL film layer is formed on the device to provide a basis for the subsequent manufacture of the device, the CESL film layer can exert a stress effect on the device, particularly on a P-type transistor, the source and drain electrodes of the P-type transistor can be formed by using a silicon germanium (SiGe) process, the carrier migration quantity in the silicon germanium film layer is greatly improved under the action of stress, but the stress can influence the phase change of the metal silicide layer, wherein for the P-type transistor, the larger the stress is, the lower the phase change temperature of the metal silicide layer is, the lower the temperature of the metal silicide layer can be used for forming the metal silicide layer with a low resistance phase, the higher the temperature is required for the N-type transistor to finish the conversion of the metal silicide layer with the low resistance phase, and the increase of the temperature can lead to agglomeration defects of the metal silicide layer with the low resistance phase formed in the P-type transistor area, so that the performance of the device is influenced.

Based on this, the embodiment of the present disclosure provides a forming method of a semiconductor device, as shown in fig. 1, in combination with fig. 2 to 10, the forming method including: step S10 to step S30.

Wherein, step S10: providing an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate 100, the substrate 100 comprises a first area A and a second area B, the first area A is formed with a P-type transistor 220, the second area B is formed with an N-type transistor 210, the P-type transistor 220 comprises a first grid electrode 221, a first source electrode 222 and a first drain electrode 223 which are positioned at two sides of the first grid electrode 221, the N-type transistor 210 comprises a second grid electrode 211, and a second source electrode 212 and a second drain electrode 213 which are positioned at two sides of the second grid electrode 211;

Step S20: forming first metal silicide layers 310 on top of the first gate 221, the first source 222, the first drain 223, the second gate 211, the second source 212, and the second drain 213, respectively;

Step S30: and forming a stress layer 400, wherein the stress layer 400 is conformally covered on the surface of the initial semiconductor structure with the first metal silicide layer 310 to form a target semiconductor structure, and the stress layer 400 comprises silicon element and nitrogen element, and the ratio of the silicon element to the nitrogen element is greater than 3:4.

According to the method for forming the semiconductor device, the first metal silicide layer 310 is formed on the N-type transistor 210 and the P-type transistor 220, the stress layer 400 is formed on the first metal silicide layer 310, the proportion between silicon elements and nitrogen elements in the stress layer 400 is larger than 3:4, so that the silicon content in the stress layer 400 is higher, on one hand, the stress in the P-type transistor and the N-type transistor can be balanced through the stress layer 400, and on the other hand, the phase change temperature of the metal silicide in the P-type transistor and the N-type transistor can be balanced due to the higher silicon element content in the stress layer 400, a uniform metal silicide layer with smaller resistivity is formed, the formation of agglomeration defects is avoided, and the yield of the device is improved.

The following describes in detail each step of the method for forming a semiconductor device provided in the embodiments of the present disclosure with reference to the accompanying drawings:

in an embodiment provided by the present disclosure, as shown in fig. 2, in step S10, an initial semiconductor structure is provided, the initial semiconductor structure including a substrate 100, the substrate 100 including a first region a formed with a P-type transistor 220 and a second region B formed with an N-type transistor 210.

In the embodiment provided in the present disclosure, the substrate 100 may include at least one first area a and at least one second area B, where each first area a and each second area B may be defined and divided on the substrate 100 according to the actual structural requirement of the device, and although in the embodiment of the present disclosure, one P-type transistor 220 is formed on one first area a, and one second area B is formed on one N-type transistor 210, this is illustrated by way of example, but the number and arrangement of the first area a, the second area B, and the P-type transistor 220, and the N-type transistor 210 on the substrate 100 are not limited.

The substrate 100 may be a semiconductor substrate, for example, a Silicon (Si) substrate, a germanium (Ge) substrate, a Silicon germanium (Ge Si) substrate, SOI (Silicon on insulator ), SOS (Silicon on Sapphire-on-Sapphire), or GOI (germanium on insulator ). In some embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs), or the like. The embodiments provided in the present disclosure are described by taking the substrate 100 as a P-type silicon (Si) substrate as an example, and of course, other types of substrates 100 may be modified or improved correspondingly in the embodiments of the present disclosure, which are all within the protection scope of the present disclosure.

The substrate 100 includes a first region a, which may be an N-type well formed on the substrate 100, in which a P-type transistor 220 is formed, and the P-type transistor 220 includes a first gate 221, and a first source 222 and a first drain 223 located at both sides of the first gate 221.

As shown in fig. 2, forming the P-type transistor 220 in the first region a may include: performing epitaxial growth on the first region A of the substrate 100 to form an epitaxial film layer which is matched with the crystal of the substrate 100; doping a P-type impurity element into the substrate 100 having the epitaxial film layer to form a first source electrode 222 and a first drain electrode 223 on the substrate 100; forming a first gate oxide layer 21 between the first source electrode 222 and the first drain electrode 223; forming a first gate layer 22 on the first gate oxide layer 21; a first gate protection layer 23 is formed on a sidewall formed by the first gate layer 22 and the first gate oxide layer 21, the first gate layer 22, and the first gate protection layer 23 form a first gate 221.

The P-type impurity element may be a group III element, for example, boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc., in this disclosure, in order to achieve a better doping effect, to increase the diffusion speed of the impurity element In the silicon substrate 100, which is beneficial to control the manufacturing process, boron (B) element may be selected as the P-type impurity element, but specific doping elements In the P-type transistor 220 may select other elements according to the process requirement and the device design requirement.

The epitaxial film may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD) or molecular beam epitaxy (Molecular Beam Epitaxy, MBE), etc., and the dimensions of the epitaxial film formation and the method employed may be selected and adjusted according to the actual design requirements of the device.

The first gate oxide layer 21 may be silicon dioxide (SiO ₂) or other high-K dielectric material layer, such as one or more of hafnium oxide (HfO ₂), zirconium oxide (ZrO ₂), aluminum oxide (Al ₂O₃), lanthanum oxide (La ₂O₃) or yttrium oxide (Y ₂O₃). It may be formed by one or more of Chemical Vapor Deposition (CVD), atomic layer Deposition (Atomic Layer Deposition, ALD), sputtering (Sputtering), molecular Beam Epitaxy (MBE), or Plasma Enhanced Chemical Vapor Deposition (PECVD), and the specific forming method may be adaptively selected and adjusted according to the characteristics of the material of the first gate oxide layer 21, etc.

The first gate layer 22 is formed on a surface of the first gate oxide layer 21, and the first gate layer 22 may be polysilicon (poly) or other metal material, such as one or more of aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), cobalt (Co), nickel (Ni), ruthenium (Ru), or iridium (Ir). Which may be formed by one or more of Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), sputtering (Sputtering), photolithography (Photolithography), or Etching (Etching), and may be selected according to characteristics of the material of the first gate layer 22, and the like. In the embodiment provided in the present disclosure, the first gate layer 22 is illustrated as polysilicon, but it should be noted that the first gate layer 22 in the present disclosure may be made of materials other than polysilicon.

The first gate protection layer 23 is formed on a sidewall formed by the first gate oxide layer 21 and the first gate layer 22. The first gate protection layer 23 may include at least one insulating material layer 131 and at least one dielectric layer 132 sequentially formed along a sidewall direction far from the first gate layer 22, and of course, the first gate protection layer 23 may also be formed by one insulating material layer 131 or one dielectric layer 132 according to actual structural requirements of the device. If the number of the insulating material layers 131 and the dielectric layers 132 is plural, the insulating material layers 131 and the dielectric layers 132 are sequentially and alternately distributed on the sidewalls of the first gate layer 22 in a direction away from the sidewalls of the first gate layer 22.

The insulating material layer 131 in the first gate protection layer 23 may be silicon dioxide (SiO ₂) or other high dielectric constant material layer, such as one or more of hafnium oxide (HfO ₂), zirconium oxide (ZrO ₂), aluminum oxide (Al ₂O₃), lanthanum oxide (La ₂O₃) or yttrium oxide (Y ₂O₃). It may be formed by one or more of Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), sputtering, molecular Beam Epitaxy (MBE), plasma Enhanced Chemical Vapor Deposition (PECVD), or physical vapor deposition (Physical Vapor Deposition, PVD), etc., and the specific forming method may be adaptively selected and adjusted according to the characteristics of the material, etc., of the insulating material layer 131.

The dielectric layer 132 may be made of silicon nitride (Si ₃N₄), which may be formed by Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD), or other materials and processes for forming the dielectric layer 132 according to the actual structure of the device.

The substrate 100 includes a second region B, which may be a P-type well formed on the substrate 100, in which an N-type transistor 210 is formed, and the N-type transistor 210 includes a second gate 211, and a second source 212 and a second drain 213 located at both sides of the second gate 211.

As shown in fig. 2, forming the N-type transistor 210 in the second region B may include: doping an N-type impurity element into the second region B of the substrate 100 to form a second source electrode 212 and a second drain electrode 213 on the substrate 100; forming a second gate oxide layer 11 between the second source electrode 212 and the second drain electrode 213; forming a second gate layer 12 on the second gate oxide layer 11; a second gate protection layer 13 is formed on a sidewall formed by the second gate layer 12 and the second gate oxide layer 11, the second gate layer 12, and the second gate protection layer 13 form a second gate 211.

The N-type impurity element may be a group V element, for example, phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc., and the specific doping element in the N-type transistor 210 may be selected from other elements according to the process requirement and the device design requirement. In addition, the second gate 211 in the N-type transistor 210 includes the second gate oxide layer 11, the second gate layer 12 and the second gate protection layer 13, and the materials and manufacturing processes used for the second gate 211 and the film layers in the first gate 221 are the same or substantially the same, which will not be repeated here.

In an embodiment provided by the present disclosure, as shown in fig. 2, before forming the P-type transistor 220 and the N-type transistor 210 on the substrate 100, the method further includes: an isolation structure 1000 is formed within the substrate 100, the isolation structure 1000 being used to space the P-type transistor 220 and the N-type transistor 210. The isolation structure 1000 may be a shallow trench isolation structure formed in the substrate 100, which may prevent current leakage between devices and improve performance and reliability of the devices. Specifically, a region for forming the isolation structure 1000 may be defined on the substrate 100 by a photolithography process, and a shallow trench may be etched in the defined region by dry or wet etching; filling the shallow trench with an insulating material such as silicon oxide (SiO ₂) to form an isolation film layer in the shallow trench; a planarization process is then performed to expose the surface of the substrate 100. The number of the isolation structures 1000 is at least one, and when the number thereof is plural, the plurality of isolation structures 1000 may be distributed in an array on the substrate 100.

In the embodiment provided in the present disclosure, in order to avoid damage or destruction to the isolation structure 1000 in the subsequent manufacturing process of the device, which affects the reliability of the device, after forming the P-type transistor 220 and the N-type transistor 210 on the substrate 100, as shown in fig. 3, the forming method further includes: forming a passivation layer 600, wherein the passivation layer 600 covers the surface of the initial semiconductor structure in a conformal manner; forming a photoresist layer 610 on the passivation layer 600; the passivation layer 600 is etched using the photoresist layer 610 as a mask to form a sub-passivation layer 601, and the sub-passivation layer 601 covers the surface of the isolation structure 1000. By forming the sub-passivation layer 601 on the surface of the isolation structure 1000, as shown in fig. 4, the isolation structure 1000 can be prevented from being damaged in a subsequent process, and the integrity of the isolation structure 1000 is ensured.

The sub-passivation layer 601 is etched by the passivation layer 600, and the two materials are the same, and can be made of silicon nitride (Si ₃N₄) and other materials, wherein the passivation layer 600 can be formed by Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD), and of course, the material of the passivation layer 600 can also be formed by other materials and processes according to the actual structural requirements of the device.

In the embodiment provided in the present disclosure, in step S20, as shown in fig. 7, the first metal silicide layer 310 is formed on top of the first gate 221, the first source 222, the first drain 223, the second gate 211, the second source 212, and the second drain 213, respectively.

Wherein, as shown in fig. 5, forming the first metal silicide layer 310 includes: forming a metal layer 330, wherein the metal layer 330 covers the surface of the initial semiconductor structure in a conformal manner; performing a second heat treatment on the initial semiconductor structure having the metal layer 330 to diffuse metal ions in the metal layer 330 into the N-type transistor 210 and the P-type transistor 220; the remaining metal layer 330 is removed.

After forming the metal layer 330, in order to avoid the influence of external impurities on the metal layer 330, in particular, to avoid the oxidation of the metal layer 330 by oxygen, the method further includes, after forming the metal layer 330, as shown in fig. 6: a barrier layer 500 is formed, the barrier layer 500 conformally covering the surface of the metal layer 330. The barrier layer 500 may be one or more of materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), etc., which may be formed by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), etc., and specific materials and forming processes of the barrier layer 500 may be adaptively selected and adjusted according to device process design. Taking the barrier layer 500 as titanium nitride (TiN) as an example, the thickness of the barrier layer 500 may be 5nm to 15nm, for example, the thickness of the barrier layer 500 may be 5nm, 8nm, 10nm, 13nm, 15nm, etc., and the thickness of the barrier layer 500 may be selected according to the actual requirements of the device process.

Wherein, in order to convert the silicon element in the substrate 100 from the crystalline state to the amorphous structure, i.e. increase the dissociability of the silicon ions, the silicon ions may enter into other film layers by diffusion, etc., before forming the metal layer 330, the method may further include: the silicon ions in the substrate 100, particularly the first gate layer 22, the second gate layer 12, and the first source electrode 222, the first drain electrode 223, the second source electrode 212, and the second drain electrode 213, are activated by ion implantation, and in a subsequent process, the silicon ions in the film layer may combine with other ions to form different molecular structures.

In addition, in order to increase the reaction area of the first gate electrode 221 and the second gate electrode 211, a portion of the first gate protection layer 23 and a portion of the second gate protection layer 13 may be appropriately removed to expose sidewalls of the tops of the first gate electrode layer 22 and the second gate electrode layer 12. Furthermore, in order to provide a foundation for the subsequent process, the device can be cleaned to remove pollutants on the surface of the device, so that the cleanliness of the surface of the device is ensured, and a good structural foundation is provided for the formation of the subsequent film.

The metal layer 330 is formed on the surface of the initial semiconductor structure, wherein the metal layer 330 may be a cobalt (Co) film, and the metal layer 330 may also be made of metallic nickel (Ni), and the disclosure describes the metal layer 330 as a cobalt (Co) film, and other metal materials may be adaptively deformed or adjusted to obtain subsequent processing steps.

The thickness of the metal layer 330 (cobalt) may be 5nm to 20nm, for example, 5nm, 10nm, 15nm, 20nm, etc. The metal layer 330 may be formed on the surface of the initial semiconductor structure by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or other method. The initial semiconductor structure having the metal layer 330 is subjected to a second heat treatment such that metal ions within the metal layer 330 diffuse into the N-type transistor 210 and the P-type transistor 220 having free silicon ions to form a first metal silicide layer 310 on top of the first gate 221, the first source 222, the first drain 223, the second gate 211, the second source 212 and the second drain 213.

After forming the first metal silicide layer 310, the remaining metal layer 330 and the barrier layer 500 need to be removed. The barrier layer 500 may be removed by dry etching or wet etching, and then the remaining metal layer 330 is removed, and the removal method may be selected according to actual process requirements.

The first metal silicide layer 310 may include silicon cobaltate (Co ₂ Si) and silicon cobaltate (CoSi), and the thickness of the first metal silicide layer 310 may be 5nm to 30nm, for example, may be 5nm, 8nm, 15nm, 20nm, 22nm, 25nm, 29nm or 30nm, and the thickness of the first metal silicide layer 310 may be different according to the ratio between the silicon cobaltate (Co ₂ Si) and the silicon cobaltate (CoSi) in the first metal silicide layer 310. Herein, thickness refers to the dimension of the film layer in a direction perpendicular to the substrate 100, wherein the thickness may refer to one of a maximum thickness, a minimum thickness, or an average thickness, and any of the three thicknesses may be employed for comparison and measurement of different film layer thicknesses.

The temperature of the second heat treatment is less than 750 ℃, specifically, the second heat treatment process may include a first sub heat treatment and a second sub heat treatment, wherein the first sub heat treatment includes: at the temperature of 250-410 ℃, cobalt ions in the metal layer 330 are used as diffusion sources, so that the cobalt ions are doped into the N-type transistor 210 and the P-type transistor 220, especially at the positions of the top parts of the first gate 221, the first source 222, the first drain 223, the second gate 211, the second source 212 and the second drain 213, which are close to the surfaces, the concentration of the cobalt ions is higher, and more silicon cobaltate (Co ₂ Si) is formed. The second sub-heat treatment includes: at a temperature of 410-700 ℃, cobalt ions continue to serve as diffusion sources, further diffuse into the N-type transistor 210 and the P-type transistor 220, and form cobalt silicon oxide (CoSi) in the first gate 221, the first source 222, the first drain 223, the second gate 211, the second source 212 and the second drain 213. After the second heat treatment, the silicon cobaltate (Co ₂ Si) and the silicon cobaltate (CoSi) may exist in the first metal silicide layer 310 at the same time, and the resistivity of the silicon cobaltate (Co ₂ Si) and the silicon cobaltate (CoSi) are both high, and the resistance of the formed first metal silicide is also high. The temperature ranges of the first sub-heat treatment and the second sub-heat treatment in the second heat treatment are shown as exemplary embodiments only, and in the actual heat treatment process, the temperature ranges are not strictly limited, and can be adaptively adjusted according to the actual process requirements.

Along with the further increase of the temperature of the heat treatment, for example, after the temperature is increased to more than 700 ℃, at this time, silicon ions in the device are diffused into the first metal silicide layer 310 as a diffusion source, and the formed silicon di-cobalt oxide (Co ₂ Si) and silicon cobalt oxide (CoSi) are continuously combined with the silicon ions to form cobalt di-silicide (CoSi ₂), the resistivity of the cobalt di-silicide (CoSi ₂) is smaller than that of the silicon di-cobalt oxide (Co ₂ Si) and the silicon cobalt oxide (CoSi), the resistance of the cobalt di-silicide (CoSi ₂) is smaller, so that the contact resistance can be effectively reduced, and the overall electrical performance of the device is improved.

However, the inventors have found that, in the CMOS device, after the stress layer 400 is formed, the carrier mobility inside the N-type transistor 210 and the P-type transistor 220 also have a large difference due to the stress, and at the same time, the diffusion efficiency of the silicon ions inside the P-type transistor 220 and the N-type transistor 210 into the first metal silicide layer 310 is different under different stresses, so that the phase transition temperatures of the metal silicide layers are also different. When the first metal silicide layer 310 in the N-type transistor 210 undergoes a phase transition, a higher temperature condition is required, and under this temperature condition, the P-type transistor 220 has completed the phase transition process, so that a metal silicide film layer with a low resistance phase is formed, especially after the stress layer 400 is formed on the device, the metal silicide film layer with a low resistance phase in the P-type transistor 220 is agglomerated due to the dual effects of high temperature and stress, so that an agglomeration defect is formed, and a metal silicide film layer with better performance cannot be formed, thereby reducing the overall performance of the device. Wherein phase transition refers to the conversion of molecules from silicon di-cobalt oxide (Co ₂ Si) or silicon cobalt oxide (CoSi) to cobalt di-silicide (CoSi ₂) within a metal silicide layer.

Therefore, in order to avoid the difference of the process conditions of the metal silicide film formation in the first region a and the second region B of the substrate 100, in step S30, as shown in fig. 8, a stress layer 400 is formed, and the stress layer 400 is conformally covered on the surface of the initial semiconductor structure having the first metal silicide layer 310 to form a target semiconductor structure, wherein the stress layer 400 includes silicon and nitrogen elements, and the ratio between the silicon and nitrogen elements is greater than 3:4. Because the silicon element content in the stress layer 400 is higher, the tensile stress in the film layer can be improved, the compressive stress generated in the P-type transistor 220 is balanced, the agglomeration defect of the metal silicide film layer in the P-type transistor 220 is avoided, meanwhile, the electron mobility in the N-type transistor 210 can be improved through the stress generated by the stress layer 400, in addition, the silicon element in the stress layer 400 can be further used as a silicon source to diffuse into the first metal silicide layer 310, and the formation of the metal silicide film layer with low resistance phase is facilitated.

In the embodiments provided in the present disclosure, the ratio between the silicon element and the nitrogen element in the stress layer 400 may be 7:8 to 15:8, for example, the silicon-nitrogen ratio may be 7:8, 8:8, 9:8, 10:8, 11:8, 12:8, 13:8, 14:8, 15:8, etc., such as the stress layer 400 may be Si ₄N₄、Si₅N₄, etc. The thickness of the stress layer 400 may be 10nm (nanometers) to 60nm, for example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, and the like.

The precursors for forming the stress layer 400 may include silane (SiH ₄) and ammonia (NH ₃) in the reaction process SiH ₄+NH₃→Si_xN_y+H₂ +.. The precursors for forming the stress layer 400 may also include silane (SiH ₄) and nitrogen (N ₂) in the reaction process SiH ₄+N₂→Si_xN_y+H₂ ∈, wherein X+.gtoreq.Y. In the above two embodiments, the hydrogen generated during the reaction may be discharged or collected for recycling. The precursor can also be a substance comprising silicon ions and nitrogen ions, the reaction process is Si ⁺+N^—→Si_xN_y, wherein X is more than or equal to Y, and the specific substance type of the precursor can be different types of substances according to the change of the forming method.

It should be noted that, in order to control the composition and performance of the stress layer 400 during the reaction, an auxiliary gas or a doping element, such as hydrogen, oxygen, etc., may be introduced to improve the performance of the stress layer 400. In addition, other precursor combinations may be used to form the stress layer 400 with higher silicon content, but the corresponding process and reaction conditions such as temperature, pressure, flow rate, etc. are used.

The stress layer 400 may be formed by Chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), atomic Layer Deposition (ALD), atomic Layer Epitaxy (ALE), sputtering, sol-gel, or the like. For example, chemical Vapor Deposition (CVD) may be used to effectively control the silicon content within stress layer 400 by using precursors, by adjusting the flow ratio of the precursors and the reaction conditions (e.g., temperature, pressure, etc.); plasma Enhanced Chemical Vapor Deposition (PECVD) may introduce plasma on a CVD basis to reduce deposition temperature and improve film quality, more precisely controlling the composition and structure of the stress layer 400; atomic Layer Deposition (ALD) can precisely control the thickness and composition of stress layer 400 by alternately introducing precursors of silicon and nitrogen and performing self-limiting surface reactions in each cycle; sputtering can form a stress layer 400 by sputtering a material onto the surface of the device under the bombardment of high-energy particles by using a target material of silicon and nitrogen, and the silicon content of the stress layer 400 can be controlled by adjusting sputtering parameters; the sol-gel method may prepare a precursor solution of the stress layer 400 having a high silicon content through a sol-gel process, then apply the solution on the surface of the device through spin coating, dipping, spraying, or the like, and form the stress layer 400 through heat treatment.

The first metal silicide layer 310 may include a mixed form of silicon di-cobalt oxide (Co ₂ Si), silicon cobalt oxide (CoSi) or silicon di-cobalt oxide (Co ₂ Si) and silicon cobalt oxide (CoSi), and at the same time, since the temperature may reach about 700 ℃ during the second sub-heat treatment, under the temperature condition, silicon ions in the device substrate 100 are actually diffused into the first metal silicide layer 310 in the form of a diffusion source, and cobalt di-silicide (CoSi ₂) with a low resistance phase is also present in the first metal silicide layer 310, but due to the diffusion of silicon ions being affected by the boundary suppression effect and the temperature condition, cobalt di-silicide (CoSi ₂) with a low resistance phase is present at the bottom of the first metal silicide layer 310 and cannot diffuse to the top thereof, i.e., the top of the first metal silicide layer 310 is still present in the form of silicon di-cobalt oxide (Co ₂ Si) or silicon cobalt oxide (CoSi) with a high resistance phase.

In order to reduce the resistivity in the metal silicide layer, as shown in fig. 9, the forming method further includes: performing a first heat treatment on the target semiconductor structure to diffuse silicon element in the stress layer 400 into the first metal silicide layer 310 to form a second metal silicide layer 320; wherein the resistivity of the second metal silicide layer 320 is less than the resistivity of the first metal silicide layer 310. The second metal silicide film layer may include cobalt disilicide (CoSi ₂), and the thickness of the second metal silicide layer 320 may be 15nm to 55nm, for example, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, and the like.

Because the silicon content in the stress layer 400 is higher, the stress layer 400 can be used as a silicon source, i.e. silicon ions in the stress layer 400 diffuse into the first metal silicide film layer under the process condition of the first heat treatment, so as to increase the content of silicon ions at the top of the first metal silicide layer 310, and promote the transition of the metal silicide from high resistance to low resistance. Meanwhile, silicon ions in the device diffuse into the first metal silicide layer 310 at the same time, and by the simultaneous action of two silicon sources, the second metal silicide layer 320 with uniform cobalt disilicide (CoSi ₂) is formed, so that the agglomeration defect formed in the P-type transistor 220 due to the dual action of stress and high temperature is improved, the stress between the P-type transistor 220 and the N-type transistor 210 is balanced, and the formed second metal silicide layer 320 has smaller resistivity and better electrical performance.

The first heat treatment can comprise laser annealing treatment, wherein the temperature of the first heat treatment is higher than 700 ℃, and the time of the first heat treatment is 10 ns-100 ms. Since the first heat treatment process is required to promote diffusion of silicon ions in the device and silicon ions in the stress layer 400 into the first metal silicide layer 310, high temperature conditions need to be provided, for example, the temperature of the first heat treatment may be 750 ℃, 800 ℃, 850 ℃, 900 ℃, 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃ or even higher. The time of the first heat treatment can also be different according to the temperature in the temperature condition, and the time of the first heat treatment can be from nanosecond level to millisecond level, for example, the time of the first heat treatment can be properly shortened under the condition of higher temperature; at lower temperatures, the treatment time can be increased appropriately. The first heat treatment may be a laser annealing process, which may rapidly heat to 1100 ℃ or above and activate silicon atoms into lattice sites within the first metal silicide layer 310, thereby changing the phase resistance of the metal silicide, and which may reduce thermal damage to surrounding film layers.

In an embodiment provided by the present disclosure, in order to prevent capacitive coupling and short circuit between the P-type transistor 220 and the N-type transistor 210, after forming the second metal silicide layer 320, as shown in fig. 10, the forming method may further include: an insulating layer 700 is formed, the insulating layer 700 covering the target semiconductor structure and filling the gap between the P-type transistor 220 and the N-type transistor 210. After forming the insulating layer 700, the forming method may further include: the insulating layer 700 is planarized.

The insulating layer 700 may be a silicon dioxide (SiO ₂) or other high dielectric constant material layer, such as one or more of hafnium oxide (HfO ₂), zirconium oxide (ZrO ₂), aluminum oxide (Al ₂O₃), lanthanum oxide (La ₂O₃) or yttrium oxide (Y ₂O₃), which may be formed by one or more of Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), sputtering, molecular Beam Epitaxy (MBE), plasma Enhanced Chemical Vapor Deposition (PECVD) or Physical Vapor Deposition (PVD), and the specific forming method may be adaptively selected and adjusted according to the material characteristics of the insulating layer 700.

Planarization of the insulating layer 700 may be performed using a Chemical Mechanical Polishing (CMP) process to provide a good structural basis for subsequent processing while ensuring isolation reliability of the device.

According to the method for forming the semiconductor device, the first metal silicide layer 310 is formed on the N-type transistor 210 and the P-type transistor 220, and the stress layer 400 with high silicon content is formed on the first metal silicide layer 310, so that on one hand, the pressure in the PMOS and the NMOS can be balanced through the stress layer 400, on the other hand, the phase change temperature of the metal silicide in the PMOS and the NMOS can be balanced due to high silicon element content in the stress layer 400, a uniform metal silicide layer with low resistivity is formed, the formation of agglomeration defects is avoided, and the yield of the device is improved.

It should be noted that although the steps of the method of forming a semiconductor device in the present disclosure are depicted in a particular order in the figures, this does not require or imply that the steps must be performed in that particular order or that all of the illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.

The embodiment of the present disclosure also provides a semiconductor device, as shown in fig. 10, which may be manufactured using the method for forming a semiconductor device described above. The semiconductor device has a metal silicide film layer with smaller resistivity, and the stress layer 400 can balance the stress between the P-type transistor 220 and the N-type transistor 210 in the semiconductor device, so that the whole device has better performance and higher yield.

The semiconductor device provided by the present disclosure can be applied to a dynamic random access Memory (Dynamic Random Access Memory, DRAM), a static random access Memory (Static random access Memory, SRAM), a Flash Memory (Flash Memory), and the like. Of course, the method can also be applied to other non-enumerated storage devices, and the non-enumerated storage devices are not listed here.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A method of forming a semiconductor device, comprising:

forming an isolation structure in the substrate, wherein the isolation structure is used for isolating the P-type transistor and the N-type transistor;

Forming a photoresist layer on the passivation layer;

Etching the passivation layer by taking the photoresist layer as a mask to form a sub-passivation layer, wherein the sub-passivation layer covers the surface of the isolation structure;

Forming a stress layer which covers the surface of the initial semiconductor structure with the first metal silicide layer in a conformal manner to form a target semiconductor structure, wherein the stress layer comprises silicon elements and nitrogen elements, and the ratio between the silicon elements and the nitrogen elements is greater than 3:4;

2. The method of forming a semiconductor device according to claim 1, wherein the first heat treatment includes a laser annealing treatment, the temperature of the first heat treatment is greater than 700 ℃, and the time of the first heat treatment is 10ns to 100ms.

3. The method of forming a semiconductor device according to claim 1, wherein the forming a first metal silicide layer comprises:

And removing the residual metal layer.

4. The method for forming a semiconductor device according to claim 3, wherein a temperature of the second heat treatment is less than 750 ℃.

5. The method for forming a semiconductor device according to claim 4, wherein after the forming of the metal layer, the method further comprises:

6. The method of forming a semiconductor device of claim 1, wherein after the forming the second metal silicide layer, the method further comprises:

7. The method of forming a semiconductor device according to claim 1, wherein a ratio between silicon element and nitrogen element in the stress layer is 7:8 to 15:8.

8. The method of forming a semiconductor device according to any one of claims 1 to 7, wherein the stress layer is formed by a plasma enhanced chemical vapor deposition method, a chemical vapor deposition method, or an atomic layer deposition method.

9. The method for forming a semiconductor device according to any one of claims 1 to 7, wherein a precursor for forming the stress layer includes silane and ammonia; or precursors for forming the stress layer include silane and nitrogen.